Circuit Design and Efficiency testing of CMOS-derived

Voltage Multiplier devices and comparative analysis

with respect to non-CMOS Voltage Multiplier circuits

Application to Adaptive Piezoelectric Energy Harvesting Circuits

Proposal submitted towards the course BITS C313 (Lab Oriented Project)
during Semester I, 2010-11

by

Sarthak Phadke
2008A3PS158G
2nd Year Undergraduate
Department of Electrical, Electronics and Instrumentation
BITS Pilani, Goa Campus

under

Dr. Iven Jose, Assistant Professor

Department of Electrical, Electronics and Instrumentation

5th April 2010

 ABSTRACT
Adaptive Piezoelectric Crystal Circuits attempt to generate micro-scale power by
making use of vibrations produced in piezoelectric crystals due to pressure
changes generated by human motion. In such type of a device, the strain
developed in a piezoelectric crystal such as Quartz due to human footfall is
converted into an output voltage that can then be used to charge energy storage
devices like batteries. The piezoelectric crystal essentially behaves like a crystal
oscillator and produces a nearly sinusoidal signal, which must be rectified and
level shifted (multiplied) before using it as an input to the storage device.

Efficient ac/dc rectification of low voltages is critical for the realization of fully
functional vibrational energy harvesting systems. This project attempts to perform
output efficiency tests on some of the common CMOS-based Voltage Multiplier
integrated circuits when supplied with low voltages less than 5 V. Fabrication of
the internal circuit design for the various CMOS ICs will be performed on a
breadboard/ printed circuit board to analyze the various circuital losses that occur
during the voltage multiplication. Finally, a simple diode-capacitor based n-level
voltage multiplier circuit will be constructed and its efficiency compared with the
CMOS devices to weigh the losses in the active circuital elements.

For vibrational energy harvesters, one specific need is ac/dc converter circuits that
can operate at low input power and low voltage with acceptable efficiency
(threshold assumed >70% for normal operation). Most attention has been focused
on circuits for piezoelectric harvesters, whose output voltage level is generally
higher (typically >1 V).