DESIGN OF CPU INTERFACE

BY
RAMAKRISHNA B
SARATCHAND A
NAGESH BS
RAKESH K

UNDER THE GUIDANCE OF

PRASHANT KUMAR SHETTY
 CPU CPU write

CPU write data

write data CPU read

read data Interface CPU read data

FIFO CPU
CPU ack

address
 Interface

reg_wm1 Reg A

reg_wm2 CPU write data

Reg B

reg_wm3 Reg C

FIFO write data Hysteresis Reg CPU read data

 Status register

over/under flow error Write control signal

water level 1 signal Read control signal
water level 2 signal
water level 3 signal