Tony PHD

1
Abstract
High-Efficiency Low-Voltage DC-DC Conversion for Portable

Applications
by
Anthony John Stratakos
Doctor of Philosophy in Engineering-Electrical Engineering

and Computer Sciences
University of California, Berkeley
Professor Robert W. Brodersen, Chair
Motivated by emerging portable applications that demand ultra-low-power
hardware to maximize battery run-time, high-efficiency low-voltage DC-DC conversion
is presented as a key low-power enabler. Recent innovations in low-power digital
CMOS design have assumed that the supply voltage is a free variable and can be set to
any arbitrarily low level with little penalty. This thesis introduces and demonstrates an
array of DC-DC converter design techniques which make this assumption more viable.
The primary design challenges to high-efficiency low-voltage DC-DC
converters are summarized. Design techniques at the power delivery system, individual
control system, and circuit levels are described which help meet the stringent
requirements imposed by the portable environment. Design equations and closed-form
expressions for losses are presented. Special design considerations for the key dynamic
voltage scaling enabler, called the dynamic DC-DC converter are given. The focus
throughout is on low-power portable applications, where small size, low cost, and high
energy efficiency are the primary design objectives.

Abstract 2
The design and measured results are reported on three prototype DC-DC
converters which successfully demonstrate the design techniques of this thesis and the
low-power enabling capabilities of DC-DC converters in portable applications. Voltage
scaling for low-power throughput-constrained digital signal processing is reviewed and
is shown to provide up to an order of magnitude power reduction compared to existing
3.3 V standards when enabled by high-efficiency low-voltage DC-DC conversion. A
new ultra-low-swing I/O strategy, enabled by an ultra-low-voltage and low-power DC-
DC converter, is used to reduce the power of high-speed inter-chip communication by
greater than two orders of magnitude. Dynamic voltage scaling is proposed to
dynamically trade general-purpose processor throughput for energy-efficiency, yielding
up to an order of magnitude improvement in the average energy per operation of the
processor. This is made possible by a new class of voltage converter, called the dynamic
DC-DC converter, whose primary performance objectives and design considerations are
introduced in this thesis.
Robert W. Brodersen, Chairman of Committee

Table of Contents iii
Table of Contents
Chapter 1: Introduction ....................................................................................................1
1.1 Motivation......................................................................................................................1
1.2 The Challenge of Lower-Voltage DC-DC Conversion ..................................................3
1.2.1 Low-Voltage and High-Current.................................................................................................4
1.2.2 Low-Voltage and Low-Current .................................................................................................5
1.3 Research Goals and Contributions.................................................................................7
1.4 Thesis Organization .......................................................................................................8
Chapter 2: DC-DC Conversion as a Low-Power Enabler ...........................................10

2.1 Voltage Scaling for Low-Power...................................................................................11
2.1.1 Multiple Supply Voltages ........................................................................................................13
2.1.2 Architectural Voltage Scaling..................................................................................................14
2.1.3 Voltage Scaling with Vt Reduction .........................................................................................17
2.1.4 Discussion ...............................................................................................................................18
2.2 Dynamic Voltage Scaling for Energy-Efficient GPP ...................................................18
2.2.1 Typical Processor Usage .........................................................................................................19
2.2.1.1 Sleep Mode ............................................................................................................20
2.2.1.2 Slow Clocks ...........................................................................................................21
2.2.2 Dynamic Voltage Scaling ........................................................................................................22
2.2.3 Discussion ...............................................................................................................................24
2.3 Low-Swing Interconnect..............................................................................................25
2.3.1 Discussion ...............................................................................................................................27
2.4 Voltage Regulation Enhances Battery Run-Time ........................................................28
2.4.1 A Piecewise Linear Model to a Low-Rate Battery Discharge Curve......................................30
2.4.2 Models for Battery Loading Conditions..................................................................................32
2.4.3 Case Study: An Analog Load with Supply-independent Biasing ...........................................33
2.4.3.1 Run directly from the cell ......................................................................................34
2.4.3.2 Run through a linear regulator ...............................................................................34
2.4.3.3 Run through a switching regulator.........................................................................34
2.4.4 Case Study: A Throughput-constrained Digital CMOS Load.................................................35
2.4.4.1 Run directly from cell ............................................................................................35
2.4.4.2 Run through a linear regulator ...............................................................................35
2.4.4.3 Run through a switching regulator.........................................................................36
2.4.5 Results .................................................................................................................. ...................36
2.4.6 Converter Size vs. Extra Battery Size .................................................................................... .39
Chapter 3: DC-DC Converter Fundamentals ...............................................................42

3.1 Introduction to Switching Regulators ..........................................................................42
3.1.1 Buck Converter .......................................................................................................................43
Table of Contents iv
3.2 DC-DC Requirements in Portable Systems .................................................................45

3.2.1 High Energy Efficiency...........................................................................................................45
3.2.2 Low Cost .................................................................................................................................46
3.2.3 Small Size................................................................................................................................47
3.2.4 Low Noise ...............................................................................................................................48
3.3 PWM Operation ...........................................................................................................49
3.3.1 Output Filter Design................................................................................................................50
3.3.2 Sources of Dissipation.............................................................................................................53
3.3.2.1 Conduction Loss ....................................................................................................53
3.3.2.2 Gate-Drive Loss .....................................................................................................54
3.3.2.3 Timing Errors.........................................................................................................54
3.3.2.4 Stray Inductive Switching Loss .............................................................................56
3.3.2.5 Quiescent Operating Power ...................................................................................57
3.4 PFM Operation ............................................................................................................58
3.4.1 Output Filter Design................................................................................................................60
3.4.2 Sources of Dissipation.............................................................................................................63
3.4.2.1 Conduction Loss ....................................................................................................63
3.4.2.2 Gate-Drive Loss .....................................................................................................64
3.4.2.3 Switch Transitions and Timing Errors...................................................................64
3.4.2.4 Stray Inductive Switching Loss .............................................................................69
3.4.2.5 Quiescent Operating Power ...................................................................................69
3.5 Other Topologies..........................................................................................................70
3.6 Alternatives to Switching Regulators ..........................................................................73
3.6.1 Linear Regulators ....................................................................................................................73
3.6.2 Switched-Capacitor Converters...............................................................................................74
Chapter 4: DC-DC Design Techniques for Portable Applications..............................79

4.1 Converter Miniaturization............................................................................................79
4.1.1 High Frequency Operation ......................................................................................................80
4.1.2 Minimum Inductor Selection ..................................................................................................81
4.1.3 High Integration ......................................................................................................................83
4.2 Circuit Techniques for High Efficiency .......................................................................84
4.2.1 Synchronous Rectification ......................................................................................................84
4.2.1.1 Synchronous Rectifier Control ..............................................................................85
4.2.2 Zero-Voltage Switching...........................................................................................................86
4.2.3 Adaptive Dead-Time Control ..................................................................................................89
4.2.4 Dynamic Power Transistor Sizing...........................................................................................93
4.2.5 Reduced Swing Gate-Drive.....................................................................................................95
4.2.5.1 Zero-Order Analysis ..............................................................................................96
4.2.5.2 First-Order Analysis ..............................................................................................97
4.2.5.3 Scaling Vt ............................................................................................................101
4.2.5.4 CMOS Gate-Drive Design...................................................................................102
4.2.5.5 Optimum Vg ........................................................................................................111
4.2.5.6 Reduced Gate-Swing Circuit Implementation .....................................................112
4.2.6 Ultra-Low-Power PWM Control...........................................................................................114
4.2.7 PWM-PFM Control for Improved Energy Efficiency ..........................................................115
Table of Contents v
4.3 System-Level Considerations ....................................................................................116

4.3.1 Converter Topology Selection...............................................................................................117
4.3.1.1 Transformer-Coupled Topologies........................................................................118
4.3.2 Effects of Conversion Ratio ..................................................................................................119
4.3.3 Highest Integration ................................................................................................................121
4.3.4 Exploiting Subsystem Voltages .............................................................................................122
4.3.5 Shared Resources ..................................................................................................................122
Chapter 5: Design Considerations for Dynamic DC-DC Converters .......................124

5.1 Dynamic Converter Definitions.................................................................................124
5.2 DVS System Example ...............................................................................................128
5.3 Dynamic DC-DC Converter Performance Objectives...............................................130
5.3.1 Tracking Energy ....................................................................................................................130
5.3.2 Tracking Time .......................................................................................................................134
5.3.3 Regulation Energy.................................................................................................................135
5.3.4 Output Voltage Ripple ...........................................................................................................138
5.4 Impact of Performance Metrics on Power Circuit Design.........................................141
5.5 Impact of Performance Metrics on System Performance ..........................................142
5.6 Summary of Previous Work.......................................................................................144
Chapter 6: Prototype DC-DC Converters ...................................................................147

6.1 Processor Power Delivery System .............................................................................148
6.1.1 Supply Voltage Selection ......................................................................................................148
6.1.2 Shared Resources ..................................................................................................................150
6.1.3 Highest Integration ................................................................................................................150
6.2 An Ultra-Low-Voltage DC-DC Converter.................................................................150
6.2.1 Control System Design..........................................................................................................151
6.2.2 Circuit Implementation .........................................................................................................155
6.2.2.1 Master Control .....................................................................................................155
6.2.2.2 Vref-VLO Comparator ........................................................................................157
6.2.2.3 iNMOS Comparator.............................................................................................160
6.2.2.4 Master Bias ..........................................................................................................166
6.2.2.5 Voltage Reference................................................................................................167
6.2.3 Power Train Design...............................................................................................................168
6.2.4 Simulation Results.................................................................................................................169
6.2.5 Measured Results ..................................................................................................................171
6.3 Prototype Dynamic Voltage Scaling DC-DC Converter............................................177
6.3.1 System and Algorithm Description .......................................................................................177
6.3.1.1 PWM Control.......................................................................................................179
6.3.1.2 PFM Control ........................................................................................................181
6.3.1.3 Start-Up................................................................................................................182
6.3.1.4 System Simulation Results ..................................................................................183
6.3.2 Load Specifications ...............................................................................................................185
Table of Contents vi
6.3.3 External Component Selection..............................................................................................186

6.3.4 Frequency Detector ...............................................................................................................188
6.3.5 Loop Filter.............................................................................................................................191
6.3.6 Current Comparators .............................................................................................................193
6.3.6.1 PMOS current limit..............................................................................................193
6.3.6.2 NMOS current limit .............................................................................................194
6.3.6.3 NMOS zero-current detection..............................................................................195
6.3.6.4 PMOS zero-current detection ..............................................................................197
6.3.7 Power FETs ...........................................................................................................................198
6.3.8 Summary of Expected Efficiency..........................................................................................200
6.3.9 Layout, Assembly, and Test ..................................................................................................202
6.3.10 Measured Results ................................................................................................................206
6.3.10.1 Start-Up..............................................................................................................207
6.3.10.2 Tracking Performance and Current Limit..........................................................207
6.3.10.3 Regulation Performance ....................................................................................211
6.3.10.4 Synchronous Rectifier Control ..........................................................................216
6.3.10.5 Low Swing I/O Transceiver...............................................................................216
6.3.11 Conclusion...........................................................................................................................218
6.4 A ZVS PWM DC-DC Converter ...............................................................................219
6.4.1 Prototype Description............................................................................................................219
6.4.1.1 External Component Selection ............................................................................221
6.4.1.2 Adaptive Dead-Time Control ..............................................................................222
6.4.1.3 FET Sizing and Gate-Drive Design .....................................................................223
6.4.2 Measured Results ..................................................................................................................225
Chapter 7: Conclusions .................................................................................................228

7.1 Conclusions................................................................................................................228
7.2 Summary of Research Contributions .........................................................................229
7.3 Future Research Directions........................................................................................230
References.......................................................................................................................231
Acknowledgments vii
Acknowledgments
It has been an honor and a privilege to study at Berkeley. There are many
people to thank: Those who inspired me, those who provided technical guidance, and
those whose friendship made even the most difficult times more enjoyable. Most of the
people I list below have provided inspiration, guidance, and friendship. To these
people, I am particularly grateful.
Before anyone else, I must thank my brother. From early childhood to today, I
have excelled mainly by following his example. I will always admire him and he will
always be my best friend.
I thank my parents for giving me unconditional love, guidance, and support.
From both Mom and Dad, I learned methodical and analytical thought. Sorry Dad: Any
creativity I have came from Mom!
Jolie Kerns continued to feed my creative side and has offered the
encouragement to make it through the last three years. I’m not sure I would have made
it without her. With my own parents 3000 miles away, Trish and Gary have provided a
home away from Berkeley, and a comfortable spot on the couch.
From our very first 140 problem set through our theses, Dave Lidsky and I
have been partners and best friends. We grew together, but perhaps I more than he: He
taught me to find the essence of a design, a talk, or a paper, and showed me how to get
the most out of grad school − by learning a little bit from every person around me. We
also had a lot of good times; I think my right arm is six inches longer than the left from
throwing every imaginable type of spherical object at Dave and his pet rodent,
Satchnomo. (Yes, Eleta, that was Dave’s dog you smelled every night and weekend and
summer day.) And you meant “back” rather than “backside”, right?
Acknowledgments viii
Andy Abo was my housemate and close friend for six years. We endured a lot
of school-induced pain together, but always survived. I thank him for his friendship,
good humor, and turkey tacos. Andy also taught me an important trait: Moderation. But
has he really never seen a great movie? My parting advice to him: Stay off the court!
As Dave and Andy helped me to grow, Chris Rudell did all he could to stunt
that growth. With four years as housemates, and countless trips to the RSF and Tilden
Park, I can guarantee that I have heard every one of his hilarious stories and seen every
uncanny imitation (except one) a dozen times.
Sekhar Narayanaswami and I probably would have graduated a year earlier if
we hadn’t (wasted? ... I don’t think so) so much time watching sports together. Sekhar
shared good music, good books, videotapes, and many laughs. He is underrated as a
physical comic − he’s second only to Chris.
Jeff Weldon and I shared trips to the RSF, Arinell’s, Lo Cocco; NBA; the city.
He’s the one with whom I thoroughly appreciated the finer points of going to school in
the Bay Area. He also served as my fashion consultant. Thanks Jeff, I will never wear a
brown belt with black shoes again.
The atmosphere in 550 was ideal. It was populated almost entirely by
exceptional people. I learned something from each of the following: Arthur Abnous,
Arya Behzad, Paul Haskell, Srenik Mehta, Keith Onondera, Craig Teuscher, Marco
Zuniga. We will be friends forever. Special thanks to the 920 Keeler founders, Srenik
Mehta and Arya Behzad, and to Katerina Pappas for renting us such an awesome house.
I am grateful to Rhett Davis for helping with the design of the DVS chip.
I learned a lot by working with Tom Burd and Anantha Chandrakasan. They
provided the low-power applications which drove my research and gave me lots of good
advice. I’ll also remember Tom’s bachelor party forever. It is either that or Chris’ 30th
birthday party which I rank as the single best night of my grad school career.
Acknowledgments ix
Andy Burstein, Cormac Conroy, Greg Uehara, and Sam Sheng were critical to
my development as an IC designer. Andy was also an inspirational teacher, cunning
satirist, and outstanding cook.
Brian Acker and Charlie Sullivan were colleagues and friends. Brian helped
me in the lab, inspired and validated a great deal of my work, and showed me some
good mountain bike trails in Tilden Park. Charlie was a mentor. I could go to him with
any problem, technical or other, and come away with the answers I needed. We also had
a lot of fun traveling together in Taiwan.
Bob Brodersen provided creative advice, research focus, and first class
facilities (Did your advisor rent the Monterey Bay Aquarium for a research retreat
dinner?). He taught me to design power circuits from a system and IC design
perspective. It’s what allowed me to differentiate my work.
While Bob was my advisor, Seth Sanders was my informal co-advisor. He
provided guidance and strong technical support. While I learned a considerable amount
about power circuit, control system, and analog IC design from Seth, I may be most
grateful for his contributions to my writing style. Thanks for making me feel like an
integral member of your research group.
I am especially grateful to Jan Rabaey and Bob Meyer for teaching me so much
about digital and analog circuits. Through their instruction, I learned to think
intuitively about circuits, and learned how to pursue research. Because they both have
strong personalities and good senses of humor, their lectures were usually a lot of fun,
too.
Tom Boot, Heather Brown, Peggye Brown, Ruth Gjerde, Elise Mills, Carol
Sitea and Kevin Zimmerman made sense of the confusion that is UC Berkeley. I feel
like they all went out of their way to help me at various times.
1.1 Motivation 1
Chapter 1
Introduction
1.1 Motivation
Current trends in consumer electronics demand progressively lower-voltage
supplies. Portable electronic equipment, such as laptop computers and cellular phones,
require ultra-low-power circuitry to maximize battery run-time. Perhaps the most
effective way to reduce power dissipation and maintain computational throughput in
such systems is to run the digital CMOS circuits at the lowest possible supply voltage
and compensate for the resulting decrease in performance with architectural, logic-
style, circuit, and other technology optimizations [Chandrakasan94b]. Such
optimizations can be performed at design time, where a well-known computational
throughput requirement can be met at some minimum voltage [Chandrakasan92], or at
run-time, dynamically adjusting the supply voltage to trade performance for energy
efficiency [Burd95], [Chandrakasan96], [Wei96], [Kuroda98]. In either case, this low-
power design strategy assumes that the supply voltage is a free variable and can be set
to any arbitrarily low level with little penalty. In portable electronic systems, high-
efficiency low-voltage DC-DC conversion is required to efficiently generate each low-
voltage supply from a single battery source.

1.1 Motivation 2
Consider, for example, the multimedia Infopad terminal [Brodersen92],
[Sheng92], [Chandrakasan93], [Truman98]. The custom hardware in the InfoPad
terminal, including the digital baseband circuitry, and speech, pen, and text/graphics I/
O chipset [Chandrakasan94a], is designed to operate at each component’s optimum
supply voltage to minimize its power consumption. Thus, a number of low-voltage
(from 1.5 V to 1.1 V), low-current (as low as 5 mA) DC power supplies must be
supported by a single battery source. Because the system also requires supplies of +/- 5
V and 8 V to power the flat panel display, RF transceiver circuitry, and microprocessor
subsystem, a total of six voltage converters are needed to generate all of the voltages
from a single 9 V battery source. These converters consume 42% of the overall power
and 12% of the system volume of the Infopad [Truman98], and cost as much as 54
dollars 1 .
Voltage regulation as an interface between the battery source and load can
further enhance battery run-time. A circuit may be designed such that its optimum
operating voltage is the end-of-life voltage of a specific cell, apparently minimizing its
power consumption without the use of a DC-DC converter. This not only makes the
circuit design challenging (the voltage of a typical AA-type lithium ion cell may vary
by as much as +/- 20% of its nominal value throughout its discharge), but because the
cell discharge characteristic is not flat, the circuit will consume greater than its
minimum operating power from the cell throughout the majority of its discharge. If a
DC-DC converter is inserted between the cell and the load, and the converter’s output
voltage is maintained down to the end-of-life cell voltage, the circuit will consume its
minimum operating power independent of the cell voltage, substantially extending
system run-time (by as much as 50% for a digital CMOS circuit powered by a single
lithium ion cell).
1. Cost estimate based on IC and all external components purchased through a distributor in 1000 quantity.
1.2 The Challenge of Lower-Voltage DC-DC Conversion 3
Since battery capacity is limited in any portable electronic device, power
minimization is crucial. DC-DC converters must dissipate minimal energy to extend
battery run-time. Power management schemes are used in most low-power hardware:
Unused circuitry is powered-down and gated clocks are employed to reduce power
consumption during idle mode [Chandrakasan94b], [Ikeda95], [Kunii95]. Such
techniques may present severe load variations (up to several orders of magnitude), and
the system may idle for a large fraction of the overall run-time. This implies the need
for a high conversion efficiency not only under full load, but over a large load
variation. Furthermore, in the ultra-low-power applications common to portable
systems, the quiescent operating power (control power) of the regulator must be kept to
an even lower level to ensure that it does not contribute significantly to the overall
dissipation. For example, a multimedia chipset has been demonstrated in
[Chandrakasan94a] which supports speech I/O, pen input and full motion video, and
consumes less than 5 mW at 1.1 V. The control circuit for a converter supplying this
chipset must have substantially lower quiescent power.
The portability requirement places severe constraints on physical size and
mass. While high-efficiency DC-DC conversion can substantially improve system run-
time in virtually any battery-operated application, this same enhancement of run-time
may also be achieved by simply increasing the capacity of the battery source. However,
particularly if voltage conversion is performed by highly-integrated CMOS converters
custom-designed to their individual loads, their volume will typically be much smaller
than the volume of the additional battery capacity required to achieve the equivalent
extension of run-time.
1.2 The Challenge of Lower-Voltage DC-DC Conversion
There are two fundamentally different classes of application for lower-voltage
DC-DC conversion, each with a unique set of challenges: Low-voltage and high-
current; and low-voltage and low-current. While both are summarized below, this thesis
is concerned primarily with applications designed for ultra-low-power hand-held
devices where high efficiency is crucial to maximize battery run-time, and small
physical size is of critical importance.
1.2.1 Low-Voltage and High-Current
New low-voltage, high-current DC-DC converters are required to deliver
power to next-generation microprocessors. With each new generation of processor, a
greater number of smaller-geometry transistors are integrated on a single chip.
Although voltages continue to scale downward, rapidly approaching 1.5 V and below,
both clock speed and physical capacitance increase with decreasing feature size,
creating an alarming increase in current with decreasing voltage.
One projection of high-performance processor trends shows a near-term
demand for as much as 40 A at 1.0 V 2 , an effective impedance of only 25 mΩ. If the
converter supplying this current had an effective series resistance of only 10 mΩ due to
the sum of the on-resistance of the FETs, all series resistance associated with bonding
and packaging, and the equivalent series resistance of the filter inductor and its
interconnection, the converter would be only 60% efficient − before all other losses
were considered. The resistance from ten squares of standard one ounce printed circuit
board copper would alone contribute nearly 25% loss. Such problems are unlikely to be
solved with clever circuit design. New parallel power supply architectures, flip-chip
solder bump and micro-BGA assembly technologies, and chip- and board-level
interconnection techniques are required to properly address this problem.
2. Based on scaled Pentium Pro current and voltage demands of 13 A at 2.4 V [Intel97]. Assumes process
technology scaled to 0.18µm with appropriate voltage scaling and an increase in average chip power consis-
tent with technology scaling trends [Rabaey96].
Worse still, is the rate at which such a processor demands its current. It can
transition from sleep mode to full operation in a time scale of nanoseconds, presenting
a load step as high as 40 A to the output of the DC-DC converter. This transient requires
a huge amount of bypass capacitance to maintain a stable voltage at the processor pins.
Today’s desktop processors requires a capacitance as high as units of millifarads (mF)
for adequate bypass decoupling [Arbetter98]. With the higher current demand and
tighter voltage tolerance of next generation processors, this capacitance seems destined
to exceed 10 mF, with an ESR requirement of less than 1 mΩ. This problem is currently
being addressed at the circuit-level, with the introduction of the active clamp [Wu97]
and the glitchcatcher [MAX1624].
1.2.2 Low-Voltage and Low-Current
One important class of low-voltage, low-current applications are those
presented by specialty digital signal processing ASICs for portable electronic devices.
Here, the digital IC is typically designed to meet a certain throughput constraint, often
dictated by some real-time application (such as video or audio). It is therefore amenable
to the voltage scaling techniques presented in Section 2.1, and unlike a general purpose
processor, its current consumption scales with its voltage supply, resulting in lower
power consumption and extended battery run-time.
Complex DSP functions, such as video compression, have been implemented at
power levels as low as several milliwatts [Chandrakasan94a]. Although, such small
power seems insignificant in nearly any real-world application, in many cases, it is not.
Consider a cellular phone or pager in standby mode. While the higher-power RF and IF
receiver components are pulsed with a small duty cycle, a variety of specialty and
general-purpose digital functions are performed continuously. As a result, the low-
power digital hardware is often the limiting factor in standby battery run-time.
A DC-DC converter supplying such a load must, itself, be far lower power than
that load. This presents a number of challenges, many of which require circuit
innovation. For example, a 1 MHz PWM converter powered by a single lithium ion cell
would dissipate over 25% of its 1 mW load power by switching only 20 pF of
capacitance. It is feasible that the connection of the external filter inductor alone would
introduce this capacitance. Resonant techniques (Section 4.2.2) are often necessary to
eliminate this dissipation in such a low-power application.
Perhaps the most important design consideration for high-efficiency low-
voltage DC-DC conversion is simply to make high efficiency a primary design
objective. This requires an understanding of all of the mechanisms of loss in the
converter and judicious use of a collection of techniques to effectively minimize theses
losses. The primary mechanisms of loss for a DC-DC converter are comprehensively
listed in Section 3.3.2 for PWM operation and in Section 3.4.2 for PFM operation. In
Chapter 4, techniques to eliminate, minimize, or reduce these losses are introduced.
Portable applications also demand that the DC-DC converter be of minimal
form factor, another challenge at lower voltage and current levels. As shown in Figure
1.1, for a fixed battery voltage, the value of filter inductance practically needed in a
8
Normalized Parameters
Lithium Ion battery

Value of L
Digital load, Io α Vo
6
% Losses in L
4
1 2 3
Output voltage, Vo
Fig. 1.1: The effect of lower voltage and current on the external filter inductor.
1.3 Research Goals and Contributions 7
DC-DC converter design increases at lower voltages and currents, and the relative loss
due to the equivalent series resistance of the inductor also increases. High quality
inductors of large value and low current capability are an anomaly − their physical size
does not scale proportionally to their power handling. They are often not amenable to
planar configurations, and therefore, usually dominate the overall form factor of the
DC-DC converter. In Section 4.1.1 and Section 4.1.2, two circuit-level techniques are
described which offer significantly reduced inductance requirements. Although
emerging technologies, such as microfabricated magnetics [Sullivan93], will eventually
shrink these inductors to chip-scale sizes, even they will require some measure of
circuit innovation to be most effectively exploited.
1.3 Research Goals and Contributions
The goal of this research is to design and implement DC-DC converters as low-
power and low-voltage enablers. This includes the development and demonstration of
an array of system- and circuit-level design techniques to increase the usefulness of
DC-DC converters in nearly any portable electronic application. Several key research
contributions which address these goals are highlighted below:
• Developed a series of design techniques which decrease the size, cost, and energy
dissipation of low-voltage DC-DC converters. These include new ideas, such as:
Minimum inductor design; adaptive dead-time control; dynamic transistor
sizing; optimal gate-drive strategies; and ultra-low-power digital PWM control;
and the new application of existing ideas: High-frequency operation;
synchronous rectification; soft-switching; and others.
• Demonstrated the concept of adaptive dead-time control with a 6 V to 1.5 V, 500
mA prototype DC-DC converter.

1.4 Thesis Organization 8
• Successfully demonstrated a high-efficiency DC-DC converter with the lowest
reported output voltage and power levels: Greater than 70% efficiency at 0.2 V
and less than 1 mW.
• Developed a new class of converter, called a dynamic DC-DC converter, which
enables as much as an order of magnitude battery run-time improvement for a
general-purpose processor system. This included the identification of the key
system- and circuit-level design considerations, and a successful prototype
build.
1.4 Thesis Organization
Chapter 2 introduces DC-DC conversion as a low-power technology enabler.
Several approaches to voltage scaling for low-power are reviewed. Aggressive voltage
scaling to several hundred mV is proposed for a low-swing interchip bus transceiver.
Dynamic scaling of the voltage supply is proposed to trade performance for energy-
efficiency at run-time. A mathematical model is developed to estimate the overall
battery run-time enhancements that can be effected by DC-DC converters.
In Chapter 3, low-voltage CMOS implementations of the three basic switching
regulator topologies − buck, boost, and buck-boost − are introduced. The requirements
imposed on these regulators by the portable environment are described. Design
equations and closed-form expressions for losses are presented for both pulse-width and
pulse-frequency modulation schemes. Also introduced are alternative regulator
topologies which may find use in ultra-low-power applications where voltage
conversion or regulation is required, but the inclusion of a magnetic component is
prohibitive.
Chapter 4 describes a number of design techniques which address the
challenges of low-voltage and low-power DC-DC conversion. Design techniques at the

1.4 Thesis Organization 9
power system, individual control system, and circuit levels are presented which reduce
the overall size, cost, and energy dissipation of a single DC-DC converter, or an entire
battery-power distribution system.
Design considerations for dynamic DC-DC converters are presented in Chapter
5. Four key performance metrics are introduced, and their impact on dynamic DC-DC
converter design and the entire dynamic voltage scaling (DVS) system are discussed.
An example DVS system is shown.
Chapter 6 details the design, implementation, and measured results of three
separate prototype converters. These prototypes were built to examine the feasibility of
the power system, control system, and circuit-level optimizations of Chapter 4, and to
demonstrate the low-power techniques of Chapter 2.
Chapter 7 provides concluding remarks and recommends future research
directions.
10
Chapter 2
DC-DC Conversion as a
Low-Power Enabler
Portable electronic equipment demands ultra-low-power hardware to maximize
battery run-time. Perhaps the most effective low-power technique is to operate each
digital CMOS subsystem at its optimum voltage, realizing a quadratic reduction in
power dissipation with decreasing supply voltage. This comes at the expense of
decreased circuit speed, and therefore requires the introduction of a number of
architecture, circuit, process technology, and other voltage scaling techniques to
achieve an acceptable level of computational throughput [Chandrakasan94b]. Such
optimizations can be performed at design time, where a well-known computational
throughput requirement can be met at some minimum voltage [Chandrakasan92], or at
run-time, dynamically adjusting the supply voltage to trade performance for energy
efficiency [Burd95], [Chandrakasan96], [Wei96], [Kuroda98]. In either case, this low-
power design strategy assumes that the supply voltage is a free variable and can be set
to any arbitrarily low level with little penalty. In portable electronic systems, high-
efficiency low-voltage DC-DC conversion is required to efficiently generate each low-
voltage supply from a single battery source.
This chapter describes a number of low-power digital CMOS design
techniques which are enabled by DC-DC converters, and the potential battery run-time
2.1 Voltage Scaling for Low-Power 11
enhancements effected by DC-DC converters in portable electronic systems. In Section
2.1, the fundamental trade-off between the speed and power dissipation of a digital
CMOS circuit through the voltage supply is presented. Several approaches to
minimizing power dissipation while meeting a desired computational performance
objective are reviewed. Section 2.2 introduces the concept of dynamically scaling the
supply voltage to realize the speed-versus-power trade-off for systems with variable
throughput requirements at run-time. In Section 2.3, aggressive voltage scaling is
proposed to dramatically decrease the power dissipation involved in driving the large
capacitive loads of off-chip busses. Section 2.4 introduces voltage regulation as an
interface between the battery source and the load in a portable electronic system. A
mathematical model is developed which illustrates the potential run-time enhancements
that are enabled by simply regulating the battery source voltage with a DC-DC
converter.
2.1 Voltage Scaling for Low-Power
The energy dissipation per switching event of a properly designed digital
CMOS circuit is dominated by the dynamic component [Horowitz94]:
2
E = C ⋅ V dd (Eq 2-1)
where C is effective capacitance fully charged and discharged over a voltage swing V dd ,
from a power supply of potential V dd . From (Eq 2-1), it is clear that a reduction of the
power supply voltage yields a quadratic savings in energy dissipation per computational
event.
However, this comes at the expense of computational throughput as the
propagation delay of a digital CMOS gate increases with decreasing V dd . Thus, as

illustrated in Figure 2.1, there is a fundamental trade-off between the energy consumed
by a switching event, and the rate at which such an event occurs.
With short channel MOS devices, carrier velocity saturation under high
electric fields results in reduced current drive. As a consequence, at sufficiently high
voltages, there is little penalty in delay, but large potential power savings from supply
voltage scaling [Kakumu90]. As V dd approaches the MOS device threshold voltage
0.5 um CMOS technology

15
SPICE simulation results
13
11
Normalized energy, delay
Delay per operation
Energy per operation

7
1.0 1.5 2.0 2.5 3.0
Vdd [Volts]
Fig. 2.1: Energy and speed trade-off with voltage.

(around 0.7-0.9 V for the data in Figure 2.1) a large increase in circuit delay, with little
energy saving, is seen for a small decrease in supply voltage. It is in the region between
these two extremes that performance and energy consumption are readily traded if the
supply voltage is made a free variable by a DC-DC converter.
2.1.1 Multiple Supply Voltages
One voltage scaling approach, which achieves power savings without
compromising computational throughput, operates the timing critical parts of the chip
at a high supply voltage, and reduces the voltage supply of the circuits not on the
critical path [Usami95], [Raje95], [Chang96], [Igarashi97]. This scheme, often called
clustered voltage scaling [Usami95], is conceptually illustrated in Figure 2.2. Here, the
speed critical circuitry is run at the high supply voltage, V ddH , while those circuits not
on the critical path are run at a lower supply voltage, V ddL . Communication from V ddL
to V ddH is accomplished through the level conversion circuit of Figure 2.3
For minimum power, greater than two separate voltages may be used per IC
[Chang96]. The primary limitation is the power introduced by the level converters.
VddH
Critical Path
VddH
Speed-critical
Circuitry
Arithmetic
Block
VddL VddH
Low-power Level
Circuitry Converter
Fig. 2.2: Conceptual illustration of using multiple supply voltages to reduce power dissipation.
VddH
VddL
in 0
out
VddL VddH
in out 0
Fig. 2.3: Level converter from VddL to VddH.
While each circuit block operated at lower voltage will effect some power savings, as
the number of separate voltage supplies increases, the overhead power of the additional
circuitry required to convert signals between these voltages begins to outweigh the
power reduction from voltage scaling.
2.1.2 Architectural Voltage Scaling
For a fixed computational throughput, lower power dissipation can be traded
for increased silicon area by exploiting parallel and pipelined architectures. Hardware
may be duplicated to reduce the clock frequency of each processing element. This
allows the supply voltage to be scaled and often results in a significant reduction in
power dissipation.
The duplicate hardware may be accessed in a parallel or pipelined fashion, or
some combination of the two. The example of an adder-comparator datapath is used as
an illustration [Chandrakasan92]. The reference datapath is shown in Figure 2.4. Three
input vectors, A, B, and C, are clocked into the datapath at a rate 1/T. The minimum
clock period, T, is set by the maximum propagation delay through the adder and
comparator. (The delay, set-up, and hold times of the registers are assumed negligible.)
The resulting output, (A+B) > C, is generated at the full throughput, 1/T. The total
adder
A Σ
comparator
(A+B) > C
1/T
1/T
1/T
Fig. 2.4: Simple reference datapath.
power dissipation is determined by the switching of the adder, comparator, and three
registers at a frequency 1/T.
A parallel implementation of this datapath is shown in Figure 2.5. Here, the
entire datapath is duplicated so that each may be clocked at a reduced frequency 1/2T.
This enables the supply voltage to be scaled, conserving power. However, the addition
of the multiplexer, clocked at the full throughput 1/T, does add some additional
overhead power. For the identical function, (A+B) > C generated at 1/T, the total power
dissipation is, in effect, now determined by the switching of an adder, comparator, three
registers, and a multiplexer at 1/T − switching over a supply voltage where the
maximum propagation delay through the adder and comparator is 2T. For example, if
the reference datapath is operated at 3.3 V, Figure 2.1 indicates that the parallel
implementation can run at 1.8 V. This yields a power dissipation of only 30% that of the
reference design.
Figure 2.6 shows a pipelined implementation of the same datapath. Here,
samples are produced at a clock rate 1/T that is determined by the maximum delay
adder
comparator
1/2T
A
1/2T
(A+B) > C
mux
B 1/T
1/2T
adder
comparator
C
1/2T
1/2T
1/2T
Fig. 2.5: Parallel datapath implementation.
through either the adder or the comparator. This means that for a fixed throughput, 1/T,
the supply voltage can be scaled relative to the reference case, conserving power.
The primary limitation to architectural voltage scaling is the overhead power
introduced by the duplicate hardware. In parallel implementations, this is usually
determined by the full-speed multiplexer. In pipelined implementations, duplication of
registers increases power dissipation.

adder
A Σ
comparator
(A+B) > C
1/T 1/T
1/T
1/T
Fig. 2.6: Pipelined datapath implementation.
2.1.3 Voltage Scaling with Vt Reduction
Since the energy per computational event ideally scales as V dd 2 while circuit
speed is related to (V dd -V t ) rather than V dd , lower power dissipation can be achieved
without compromise of throughput by appropriately scaling device threshold voltages,
V t , together with the voltage supply, V dd [Liu93], [Chandrakasan94b], [Frank97].
Using simple first-order theory, it can be shown that a circuit running at a
supply voltage of V dd = 1.5 V with V t = 1.0 V will have nearly identical performance to
the same circuit running at V dd = 0.9 V with V t = 0.5 V [Chandrakasan94b]. However,
the circuit running at V dd = 0.9 V will consume roughly one third the power.
Voltage scaling with threshold voltage reduction is limited primarily by
subthreshold leakage currents in the lower threshold devices, which increase
exponentially with decreasing V t . For sufficiently low V t , subthreshold leakage can
result in significant static power dissipation. [Chandrakasan94b] shows an optimal

2.2 Dynamic Voltage Scaling for Energy-Efficient GPP 18
combination of V dd = 0.9 V, V t = 0.5 V for a 20 MHz 16-bit ripple carry adder in a 1.2
µm CMOS process.
2.1.4 Discussion
All three of these approaches to voltage scaling have been successfully
demonstrated to reduce power dissipation in commercial and academic research ICs.
However, the discussions above assume that the voltage supply is a free variable and
can be set to any arbitrarily low level with little penalty. In portable electronic systems,
high-efficiency low-voltage DC-DC conversion is necessary to efficiently generate
each low-voltage supply from a single battery source.
2.2 Dynamic Voltage Scaling for Energy-Efficient GPP
General-purpose processors (GPPs) are occasionally required to process
instructions as rapidly as possible. This means that peak performance cannot be
sacrificed for lower power, rendering most voltage scaling techniques impractical for
such applications. As a result, the power consumption of GPPs continues to grow in
relation to their surrounding subsystems, and is beginning to represent the largest
component of power in many portable computing systems.
Typical processor usage patterns can be exploited to reduce average power
dissipation with little sacrifice in peak performance. Since the processor spends a large
fraction of time idling, and performs mainly low throughput and high latency processes,
it can be shut down for the majority of its cycles, significantly reducing power. Two
such power management techniques, summarized in the following subsections, are
successfully employed in many modern-day processors [Ikeda95], [Kunii95]. A new
power management technique introduced in this section, called Dynamic Voltage
Scaling, further decreases average power dissipation by reducing the energy per
operation of the lower throughput tasks − those tasks which otherwise dominate the
time-averaged power consumption of the processor.
2.2.1 Typical Processor Usage
Figure 2.7 shows a heuristic model of the throughput demands of a single-user
microprocessor subsystem [Burd96]. In this figure, desired computational throughput is
plotted versus time, and it is indicated that peak processor throughput (limited by the
peak performance of the processor) is demanded only a small percentage of the time.
The processor spends most of its time idling, and performs the majority of its cycles on
low-throughput and high-latency processes.
Below, three power management techniques are described which exploit
typical processor usage statistics to conserve power. To determine the relative merits of
these power management techniques, a metric is necessary to compare the resulting
energy efficiency of the processor. Here, the metric of:
(average energy per operation) x (minimum delay per operation) (Eq 2-2)
Compute-intensive and
low-latency processes
Desired Throughput
Ceiling: Set by top speed

of the processor
time
Single-user systems Background and

not always computing high-latency processes
Fig. 2.7: Processor usage model in portable electronic devices [Burd96].

is used. This metric is similar to that proposed in [Horowitz94] to compare low-power
designs. Since the peak performance of the processor is, itself, a key specification,
average power and average energy per operation are poor metrics. Either can be reduced
at the expense of performance; the former by reducing the clock frequency; the latter by
reducing the voltage supply. For a fixed peak throughput, the minimum metric of (Eq 2-
2) indicates the largest number of operations that can be performed from a fixed battery
capacity − the most energy-efficient design. For a fixed number of operations, the
minimum metric indicates the maximum throughput of the processor − the highest-
performance design.
To further facilitate this comparison, a reference processor design is used
[Burd95]. A maximum clock frequency, f MAX = 100 MHz, is achieved at 3.3 V, where
the energy per operation is E MAX = 4.5 nJ. The relative delay and energy per operation
scale with voltage as shown in Figure 2.1. Although the processor must occasionally
deliver peak throughput to service certain operations, the majority of its energy is
consumed on low throughput and high latency processes. For the purposes of this
analysis, it is assumed that 99% of the operations in a typical application can be
performed at 5 MHz, while the other 1% of the operations are performed at f MAX . The
average energy per operation is then:
(0.99) (energy / op @ 5 MHz) + (0.01) (energy / op @ 100 MHz) (Eq 2-3)
2.2.1.1 Sleep Mode
The most obvious technique for reducing the power consumption of the
processor is to shut it down when it idles. In Figure 2.8, all operations are computed at
the maximum clock speed, f MAX . Lower throughput tasks are performed by waking the
processor up, computing as soon as possible, then shutting down.

Excess throughput
Peak
Throughput
Delivered
Desired
time
Fig. 2.8: Processor power management: Wake up → compute ASAP → sleep mode
[Burd96].
In the ideal case, the processor can shut down or wake up immediately and
with no energy overhead, and dissipates no power when it idles. In this way, the average
power dissipation is proportional to the average throughput requirement. However,
since the processor operates from a constant supply voltage, despite the fact that the
average power scales with decreasing throughput requirements, the energy per
operation is unchanged. Evaluation of the metric of (Eq 2-2) results in a figure of merit
equal to:
(1 / fMAX) x (EMAX) = (10 ns) (4.5 nJ) = 45 nJ ⋅ ns (Eq 2-4)
2.2.1.2 Slow Clocks
Some portable computer systems include a user-controlled low-power mode on
top of sleep mode. In this scheme, illustrated in Figure 2.9, the clock frequency of the
processor is reduced below f MAX to further decrease the average power dissipation.
Evaluation of the metric of (Eq 2-2), with a clock frequency reduction to f clk = f MAX / 2
results in:
(2 / fMAX) x (EMAX) = (20 ns) (4.5 nJ) = 90 nJ ⋅ ns (Eq 2-5)

Peak
Throughput fCLK Desired
Reduced Delivered
time
Fig. 2.9: The processor is set to a low-power state [Burd96].
Comparison of (Eq 2-5) with (Eq 2-4) shows that this technique results in an even less
energy-efficient design.
2.2.2 Dynamic Voltage Scaling
While the GPP power management techniques described above do serve to
reduce the average power dissipation of the processor, they do not take advantage of the
lower throughput requirements to scale the energy per operation. Because the majority
of operations are still performed on lower throughput tasks, the circuits usually
complete operations far faster than required, and according to the data in Figure 2.1, are
unnecessarily wasteful of energy. If instead, the clock and the voltage are dynamically
scaled together to meet the real-time computational demands of the user as in Figure
2.10, lower energy per operation can be achieved on the lower throughput tasks
[Nielsen94], [Chandrakasan96], [Wei96], [Namgoong97].
This is shown in Figure 2.11, where the data in Figure 2.1 is redrawn to display
energy per operation versus delivered throughput. The gray line plots this data for a
fixed 3.3 V power supply voltage; for a fixed voltage supply, regardless of the
processor throughput, the energy per operation is unchanged. The solid black line
shows the same data for a scaled supply voltage − one that ensures that the circuit delay
Peak
Throughput
Delivered = Desired
time
Fig. 2.10: The clock and voltage are scaled dynamically.
Constant supply voltage

1.0
3.3V
Energy / operation
~10x Energy
0.5 Reduction
Reduce supply voltage,

slow circuits down.
1.05V
0
0 0.5 1.0
Throughput (α fCLK)
Fig. 2.11: Energy per operation versus throughput for a digital CMOS circuit.
just meets the throughput requirements of the clock. At the 1.05 V operating point, a
9.9x improvement in energy per operation can be realized. While this requires a 20x
reduction in clock frequency, in many portable electronic systems, this operating point
yields sufficient throughput for the majority of operations. As a result, a nearly 9.9x
reduction in battery energy consumption can be achieved.
Consider the reference processor design introduced in Section 2.2.1. The
maximum throughput, f MAX = 100 MHz, is maintained at 3.3 V for the required 1% of
the operations. At this operating point, the energy per operation is 4.5 nJ. However, the
remaining 99% of the operations require computation at only 5 MHz, allowing a circuit
delay of twenty times the 10 ns minimum. From Figure 2.1, the processor can achieve
this throughput from a 1.05 V supply, yielding a reduction in energy per operation to
only 0.4 nJ. Thus, with:
fMAX = 100 MHz (Eq 2-6)
and
EAVE = (0.99) (0.4 nJ) + (0.01) (4.5 nJ) = 0.44 nJ (Eq 2-7)
the figure of merit in (Eq 2-2) evaluates to:
(10 ns) (0.44 nJ) = 4.4 nJ ⋅ ns (Eq 2-8)
providing an order of magnitude improvement in energy-efficiency over existing power
management techniques.
2.2.3 Discussion
To dynamically trade performance for decreased energy consumption at system
run-time, a new type of DC-DC converter, called a dynamic DC-DC converter or
tracking converter, is required. A dynamic DC-DC converter is quite different from a
conventional static DC-DC converter. Whereas a static DC-DC converter must maintain
a substantially DC output, a dynamic DC-DC converter must be capable of rapidly
slewing its output.
Dynamic voltage scaling is advantageous only when the majority of processor
energy is consumed on low throughput and high latency processes. Otherwise, DVS
effects no substantial energy savings. In addition, the energy saved by DVS must be
conserved by the dynamic DC-DC converter. This means that adaptations in the output
2.3 Low-Swing Interconnect 25
voltage must be energy efficient, and since the majority of energy in a DVS system is
consumed at a low-throughput, low-power operating point, the converter must also be
highly efficient at this operating point.
Chapter 5 details these and other DVS system and circuit-level considerations.
Chapter 6 describes a prototype dynamic DC-DC converter.
2.3 Low-Swing Interconnect
The power dissipation associated with driving large capacitive off-chip busses
is often a primary limitation to low-power operation of general-purpose processors.
Consider, for example, the energy-efficient microprocessor subsystem in [Burd95].
Dynamic voltage scaling has been proposed to reduce the energy consumption of the
major components of this subsystem − the processor core and the memory ICs. The
resulting system is expected to consume no more than 450 mW at 100 MIPS and 3.3 V,
and a small fraction of that in its most energy-efficient mode of operation (2 mW at 5
MIPS and 1.05 V). However, these figures neglect the dissipation associated with
interchip communication.
The processor drives an external 32-bit bus, with nearly 50 pF of capacitance
per bit, at the full system throughput. Assuming an activity factor of 25%, if each bit is
fully driven from rail-to-rail, the associated power dissipation would be:
2
P bus = ( 32 bits ) ⋅ ( 50 pF ) ⋅ ( 0.25 ) ⋅ ( 3.3 V ) ⋅ ( 100 MHz ) = 435 mW (Eq 2-9)
in the highest-throughput mode, and:
2
P bus = ( 32 bits ) ⋅ ( 50 pF ) ⋅ ( 0.25 ) ⋅ ( 1.05 V ) ⋅ ( 5 MHz ) = 2.2 mW (Eq 2-10)
in the most energy-efficient mode. In both cases, this approximately doubles the power
dissipation of the processor subsystem.
A number of remedies, including a variety of reduced swing bus architectures
[Nakkagone93], [Bellaouar95] and charge recycling schemes [Hiraki94],
[Yamauchi94], have been proposed for this problem. While many of these techniques
have been demonstrated with some success, they either add too much complexity to the
system, or are not as conservative with power as they might be. An alternative scheme
is proposed here.
Voltage scaling for low-power is the underlying concept of the low-swing I/O
bus transceivers [Burd95]. Figure 2.12 shows a block diagram of the approach. The
incoming signal is driven off-chip by an NMOS buffer running at an ultra-low supply
voltage, V LO . The gates of NMOS buffer devices M1 and M2 are driven at full-rail
VDD
VDD VLO
VDD VLO / 2
VLO -
0 VDD
+
0
50pF 0
IC IC
NMOS Buffer external Dynamic Sense-Amp

bus
VLO
VDD in
M1
VDD out
0
VLO
M2 0
Fig. 2.12: Low-swing I/O bus.

voltage swings, V DD , providing sufficient overdrive for good high-speed performance.
Since they drive their large output load capacitance between only 0 V and V LO , power
dissipation may be substantially reduced for V LO « V DD . A receiving dynamic sense
amplifier compares the incoming low-swing signal against a DC reference, midway
between the low-voltage rails. In the ideal case, the power dissipation of the receivers
is negligibly small, so that the power dissipation of the inter-chip communication is
2
reduced by the factor ( V dd ⁄ V LO ) . In [Burd95], a 200 mV signal swing has been
proposed, and a test chip verified successful operation above 100 MHz [Burd98]. The
new bus transceiver system reduces this component of power dissipation to:
P = 1.6 mW at 100 MIPS (Eq 2-11)
P = 80 µW at 5 MIPS (Eq 2-12)
a factor of 272 and 27.5 lower than the figures reported in (Eq 2-9) and (Eq 2-10),
respectively − and nearly negligible compared to the power dissipation of the processor.
This low-swing bus architecture has two distinct advantages over existing
techniques. First, a high-efficiency DC-DC converter provides the ultra-low-voltage
supply to the drivers so that, unlike other low-swing I/O architectures that employ
linear regulators, the majority of the power saved by the transceiver circuitry is not
dissipated in the regulator. Second, this approach uses single-ended, rather than
differential, signals. This means that pin count and board-level routing complexity are
reduced, and an additional factor of two in power dissipation is saved compared to
differential architectures.
2.3.1 Discussion
The ultra-low-swing I/O transceivers require an ultra-low-voltage DC-DC
converter to create the supply voltage V LO . Here, high efficiency is especially

2.4 Voltage Regulation Enhances Battery Run-Time 28
challenging: 80 µW at 0.2 V is far lower in voltage and power than any previously
reported converter. However, since the power savings are so large as to make power
dissipation nearly negligible, the efficiency need not be as aggressively high as in most
converters. In fact, an efficiency above 70% is likely suitable at 0.2 V. Furthermore,
since V LO need not be tightly regulated − it must be some voltage which is much
smaller than V DD − some compromises can be made in the design of the converter.
A DC-DC converter has been successfully demonstrated for this application.
Its design and performance are summarized in Chapter 6.
2.4 Voltage Regulation Enhances Battery Run-Time
Voltage regulation as an interface between the battery source and load can
further enhance system run-time. A circuit may be designed such that its optimum
operating voltage is the end-of-life voltage of a specific cell, apparently minimizing its
power consumption without the use of a DC-DC converter. This not only makes the
circuit design challenging (the voltage of a typical AA-type lithium ion cell may vary
by as much as ± 20% of its nominal value throughout its discharge), but because the cell
discharge characteristic is not flat, the circuit will consume greater than its minimum
operating power from the cell throughout the majority of its discharge. If a DC-DC
converter is inserted between the cell and the load, and the converter’s output voltage is
maintained down to the end-of-life cell voltage, the circuit will consume its minimum
operating power independent of the cell voltage, substantially extending system run-
time (by as much as 50% for a digital CMOS circuit powered by a single lithium ion
cell).
Figure 2.13 shows typical low-rate battery discharge curves for three
commercially available AA-type secondary battery sources: Nickel Cadmium (NiCd),

4.5
Li Ion
Cell Voltage v(q) [V]

3.0
NiMH
1.5
NiCd
0
0 300 600 900
Charge Delivered q [mAh]
Fig. 2.13: Typical low-rate discharge characteristics for AA-type Nickel Cadmium (NiCd),
Nickel Metal Hydride (NiMH), and Lithium Ion (Li Ion) cells. Data is approximated from
[Caruthers94].
Nickel Metal Hydride (NiMH), and Lithium Ion (Li Ion). Consider a block of
throughput-constrained logic run directly from a NiMH cell and designed to operate
down to the end-of-life cell voltage. If the power consumption of the logic is dominated
by the dynamic component, and the circuitry is clocked at a frequency f 0.9 to meet
throughput constraints at the minimum cell voltage v ( q ) = 0.9 V , then the circuitry will
consume a minimum power at the end of the usable cell life:
2
P L(min) = f 0.9 ⋅ C eff ⋅ 0.9 (Eq 2-13)
Here, C eff is the effective switching capacitance (commonly expressed as the product of
a lumped physical capacitance and an activity factor [Rabaey96]). However, at other
points q in the cell discharge characteristic v(q), the power consumption of the circuitry
is given by:
2
2 v(q)
P L ( q ) = f 0.9 ⋅ C eff ⋅ v ( q ) = P L ( min ) ⋅ ------------- (Eq 2-14)
2
0.9
At initial cell voltage, this is a factor of 2.78 times P L(min), and at nominal cell voltage,
a factor of 1.78 times P L(min) . Thus, the load is seen to consume greater than minimum
power throughout the cell discharge without increased throughput.
If a DC-DC converter with efficiency:
P out
η ≡ ---------- (Eq 2-15)
P in
and zero dropout voltage is inserted between the battery and the load, and the output of
the converter is regulated to the end-of-life cell voltage, the logic consumes P L(min)
independent of the cell voltage, and the power drawn from the cell at any point q in its
discharge characteristic is constant and equal to:
P L ( min )
P ( q ) = ------------------- (Eq 2-16)
η
In this section, a mathematical model is developed to estimate the impact of
DC-DC conversion on system run-time. This analysis considers analog circuitry with
supply-independent biasing and throughput-constrained digital CMOS circuitry, and
compares system run-time when these loads are run directly from the battery source,
and from the battery source at a minimum voltage through a linear regulator or a
switching regulator.
2.4.1 A Piecewise Linear Model to a Low-Rate Battery Discharge Curve
A piecewise linear model which approximates a typical low-rate cell discharge
curve is constructed in Figure 2.14. The battery discharge characteristic is described by
its cell voltage v(q) after a charge, q, has been delivered to the load. At full capacity
( q = 0 ), the cell has an initial voltage v ( 0 ) = V 1 . The nominal cell voltage lies in the
range V 2 ≤ v ( q ) ≤ V 3 from a delivered charge Q 1 ≤ q ≤ Q 2 . At the end of its usable life

V1 Initial
Nominal
V2
V3
Cell Voltage (v(q))

V4
End of Life
0 Q1 Q2 QA
Charge Delivered (q)
Fig. 2.14: A piecewise linear model of a typical low-rate cell discharge characteristic.
( q = Q A ), the cell voltage drops to v ( Q A ) = V 4 . The energy available in the cell at
full capacity, E A , is the area under the entire discharge curve. The mean cell voltage
(averaged over the delivered charge, q) is v ( q ) = E A ⁄ Q A . The system run-time, t A , is
found by solving the following differential equation which governs the cell discharge at
any point q in the discharge characteristic:
·
q = i(q) (Eq 2-17)
with the initial condition:
q = 0, t = 0 (Eq 2-18)
yielding:
QA
∫ ---------
dq
tA = (Eq 2-19)
i(q)
0
2.4.2 Models for Battery Loading Conditions
Figure 2.15 shows the three loads considered in this analysis, (a) a constant
current load I, (b) a resistive load R, and (c) a constant power load P, each attached
across the terminals of a cell whose discharge characteristic v(q) is described by Figure
2.14.
In Figure 2.15a, the current drawn from the battery is constant and equal to I.
Thus, (Eq 2-19) yields:
QA
t A = -------- (Eq 2-20)
I
For the resistive load of Figure 2.15b:
v(q)
i ( q ) = ----------- (Eq 2-21)
R
i(q) = I i(q) = v(q) / R i(q) = P / v(q)
+ + + Constant
v(q) v(q) R v(q) Power
I Load, P
- - -
(a) (b) (c)
Fig. 2.15: Battery loading conditions: (a) a constant current load I, (b) a resistive load R, (c)
a constant power load P.
and although integration of (Eq 2-19) provides a closed-form expression for t A , it
proves ungainly and provides little insight. However, if the simplifying assumption that
the mean load current, averaged over the system run-time ( t ∈ [ 0, t A ] ) is equal to the
mean load current, averaged over the delivered charge ( q ∈ [ 0, Q A ] ):
v(q )
i ( t ) = i ( q ) = ----------- (Eq 2-22)
R
is made, the expression for t A is considerably more workable:
QA ⋅ R
t A = ---------------- (Eq 2-23)
v( q)
Since the cell voltage v(q) is relatively flat during the majority of the cell discharge, the
approximation of (Eq 2-22) is valid for any of the discharge characteristics of Figure
2.13, introducing an error of less than 0.5%.
In Figure 2.15c, the load draws a constant power P from the cell, such that:
P
i ( q ) = ----------- (Eq 2-24)
v(q)
and:
EA QA ⋅ v( q )
t A = ------- = ----------------------- (Eq 2-25)
P P
2.4.3 Case Study: An Analog Load with Supply-independent Biasing
Analog circuitry with ideal supply-independent biasing draws a quiescent
current I, independent of the voltage across its terminals.

2.4.3.1 Run directly from the cell
(Eq 2-19) gives the baseline system run-time t Ao:
QA
t Ao = -------- (Eq 2-26)
I
2.4.3.2 Run through a linear regulator
In the idealized case, the linear regulator has a dropout voltage of zero and a
quiescent operating current which is negligible with respect to I (see Section 3.6.1).
Thus, the supply may be regulated to the minimum voltage, V min ≤ v ( q ) , at which the
load can operate, minimizing its power consumption, and the quiescent current of the
regulator may be ignored. However, because the same current I drawn by the load flows
through the regulator, the power which is conserved by running the load at V min is
dissipated in the regulator. (The dissipation in the regulator is I ⋅ V min .) The battery
still sources the current I, and:
tA
-------
- = 1 (Eq 2-27)
t Ao
System run-time is neither enhanced nor diminished.
2.4.3.3 Run through a switching regulator
If the output is regulated to any V min through a switching regulator with
efficiency η, the load consumes a constant and minimum power. The power drawn from
the cell is constant and equal to:
P L ( min ) I ⋅ V min
P = ------------------- = ------------------- (Eq 2-28)
η η
Substituting (Eq 2-28) into (Eq 2-25), and normalizing with respect to t Ao gives:
tA η ⋅ EA η ⋅ v ( q -)
-------
- = ------------------------
- = ------------------ (Eq 2-29)
t Ao V min ⋅ Q A V min
2.4.4 Case Study: A Throughput-constrained Digital CMOS Load
A throughput-constrained digital CMOS circuit whose power consumption is
dominated by its dynamic component, that is clocked at a frequency f V(min) to meet
throughput constraints at the minimum voltage V min , and that has an effective switching
capacitance C eff , may be modeled by an equivalent resistance of value:
1
R eff = --------------------------------- (Eq 2-30)
f V ( min ) ⋅ C eff
2.4.4.1 Run directly from cell
Substitution of (Eq 2-30) into (Eq 2-23) gives the baseline system run-time:
Q A ⋅ R eff
t Ao = ---------------------- (Eq 2-31)
v(q)
2.4.4.2 Run through a linear regulator
If the load is run from the minimum voltage V min at which throughput
constraints are met, it consumes a constant current:
V min
I min = ------------ (Eq 2-32)
R eff
which is sourced through the regulator from the battery source. This current represents
the minimum operating current of the load. Substitution of I min in (Eq 2-32) for I in (Eq
2-20), and normalization of the result to t Ao yields:

tA
-------
EA
- = ------------------------ v ( q )-
- = ----------- (Eq 2-33)
t Ao V min ⋅ Q A V min
2.4.4.3 Run through a switching regulator
At the minimum voltage V min, the load consumes a constant power:
2
V min
P = P L ( min ) = ------------ (Eq 2-34)
R eff
which represents the minimum operating power of the load. The average power drawn
from the cell through the switching regulator is:
2
P L ( min ) V min
P = ------------------- = ------------------ (Eq 2-35)
η η ⋅ R eff
and:
2
tA η ⋅ EA η ⋅ v(q)
2
-------- = -------------------------------- = ---------------------- (Eq 2-36)
t Ao 2 2
( V min ⋅ Q A ) V min
2.4.5 Results
A factor that appears frequently in the above comparisons of system run-time
is the ratio of the mean cell voltage (averaged over the delivered charge, q) to the
minimum voltage required by the load. For convenience in summarizing the results, the
symbol β is used for this ratio:
v(q )
β ≡ ------------ (Eq 2-37)
V min
In terms of β, Table 2.1 gives the run-time enhancement factor, K, for a linear
(constant-current) or a constant throughput digital CMOS (resistive) load, where K is
the run-time relative to the baseline run-time when the load is run directly from the
battery source,
Table 2.1: System run-time enhancement.
Constant throughput digital

Regulator type Constant-current load
CMOS load
Linear K=1 K=β
Switching, efficiency η K=ηβ K = η β2
tA
K ≡ -------- (Eq 2-38)
t Ao
Figure 2.16 shows the system run-time enhancement for NiCd, NiMH, and Li
Ion cells loaded with analog and digital circuitry achieved by simply regulating the
battery source voltage with a linear regulator, and a 90% and 100% efficient DC-DC
converter. Here, the output voltage of each converter is maintained at the end-of-life
cell voltage.
The results shown in Table 2.1 can be used to predict the benefits of different
regulation schemes for a variety of loads. A linear regulator produces no advantage in
system run-time for a constant-current load (e.g. many analog circuits). It should only
be used if a stabilized voltage improves the performance of the load circuitry. With a
digital CMOS load, the linear regulator provides an improvement by the factor β.
Regardless of the load type, a switching regulator results in a value of K which is that
for a linear regulator, multiplied by an additional factor ηβ. As long as the efficiency of
the regulator is high enough that ηβ > 1, the switching regulator will give a longer run-
time than a linear regulator.

The benefits of a switching regulator are greatest where β is large; that is,
where the minimum required load voltage is small compared to the average battery
voltage. This makes intuitive sense, since an unnecessarily high voltage is wasteful of
energy. With a load that is designed to run down to the end-of-life cell voltage, the
factor β is only a function of the battery characteristic, and, for the discharge
characteristics of Figure 2.13, is 1.33 for NiMH or NiCd cells, and 1.26 for Li Ion.
Note, however, that for a load with a minimum operating voltage below the end-of-life
voltage of its battery source, β can be much higher. For example, consider the low-
power multimedia chipset introduced in [Chandrakasan94a]. If this chipset, which can
operate at a 1.1 V minimum supply voltage, were run from a Li Ion cell, β would be
3.27. In this system, even a very low efficiency switching regulator would be desirable
− even with 31% efficiency, it would out-perform an ideal linear regulator. Efficiency is
still important, however − in all cases, the run-time with a DC-DC converter is directly
2.0
β = 1.33 β = 1.33 β = 1.26 Analog Load
System Run-time Enhancement, K
Linear Reg
Analog Load
1.5 DC-DC (η=0.9)
Analog Load
DC-DC (η=1.0)
1.0
Digital Load
Linear Reg
Digital Load
0.5
DC-DC (η=0.9)
Digital Load
DC-DC (η=1.0)
0.0
NiCd NiMH Li Ion
Fig. 2.16: Battery run-time enhancement achieved by regulating the battery source voltage to
the end-of-life cell voltage.
proportional to the efficiency of the converter. In this example, with 90% efficiency, as
is readily achieved using the design techniques presented in Section 4.2, the system
run-time would be 9.64 times longer than if the chipset were run directly from the Li
Ion battery source.
2.4.6 Converter Size vs. Extra Battery Size
While DC-DC conversion can significantly improve system run-time, this
same enhancement of run-time may also be achieved by simply increasing the capacity
of the battery source. The battery is often the physically largest and most expensive
component in a portable electronic system. Nevertheless, regulators increase the cost,
volume, and complexity of the design. Thus, from a system design standpoint, it is
important to compare the volume required for the converter to the volume that would be
required for this additional battery capacity.
Suppose the run-time is enhanced by a factor K by the use of a DC-DC
converter. The volume of the converter needed to achieve this enhancement, ∆S DC-DC ,
may be estimated from the power it supplies, P L(min) , and its power density, D P(DC-DC) :
P L ( min )
∆S DC-DC = -------------------------- (Eq 2-39)
D P ( DC-DC )
To improve system run-time by the same factor K without using a converter,
the battery capacity would need to be increased by the factor K. The resulting increase
in battery volume is then:
∆S B = S B0 ( K – 1 ) (Eq 2-40)
where ∆S B is the volume of the additional battery capacity, and S B0 is the initial battery
volume. The initial battery volume may be calculated from the energy it stores at full
capacity, E A , and its volumetric energy density, D E(bat) :

EA
S B0 = ------------------ (Eq 2-41)
D E ( bat )
The volume of the DC-DC converter is related to the load power, as illustrated
by (Eq 2-39), whereas the volume of the additional battery capacity is related to the
integral of the load power − the total energy consumed by the load over the system run-
time. These two quantities can only be compared by specifying the enhanced run-time,
t A . In the case that a DC-DC converter is used, the load on the battery is a constant
power, P L(min) / η. Thus,
P L ( min ) ⋅ t A
E A = ----------------------------- (Eq 2-42)
η
Substituting this expression into (Eq 2-41), and the result into (Eq 2-40), gives
the additional battery volume in terms of t A and P L(min) :
t A ⋅ P L ( min ) ( K – 1 )
∆S B = ----------------------------- ⋅ ------------------ (Eq 2-43)
D E ( bat ) η
Comparing the additional volume needed in each case,
∆S B D P ( DC-DC ) ⋅ t A ( K – 1 )
---------------------- = ------------------------------------ ⋅ ------------------ (Eq 2-44)
∆S DC-DC D E ( bat ) η
Conceptually, (Eq 2-44) compares the energy density of the battery (D E(bat) ) to
the effective energy density of the converter − the factor D P ( DC-DC ) ⋅ t A gives the
energy handled by the converter per volume, and the factor ( K – 1 ) ⁄ η corrects this for
the amount of energy savings the converter effects, relative to the amount of energy it
handles. Although the position of η in (Eq 2-44) is at first counter-intuitive, recall that
K is directly proportional to η; we may write K = K 0 ⁄ η . In terms of K 0 then,

∆S B D P ( DC-DC )
---------------------- = -------------------------- ⋅ t A ⋅ ( K 0 – 1 ⁄ η ) (Eq 2-45)
∆S DC-DC D E ( bat )
Since K 0 is equal to β or β 2 (see Table 2.1), the ratio, (Eq 2-45), is seen to increase with
increasing efficiency, as expected.
Small Li Ion cells have an energy density up to 0.3 W-h/cm 3 [Caruthers94].
Primarily because of packaging volume, smaller converters have somewhat lower
power densities than large commercial converters of 50-200 W, but ultra-low-power
converters with power densities above 1 W/cm 3 can be achieved through the use of the
techniques discussed in Section 4.1. Using these power and energy densities in
conjunction with (Eq 2-44), it is possible to evaluate the relative converter or additional
battery volume required for an equal extension of system run-time.
For example, again consider the system introduced in Section 2.4.5. There, it
was shown that a 90% efficient DC-DC converter with a regulated 1.1 V output can be
used to enhance system run-time from a Li Ion source by a factor of K = 9.64 . For an
8 h target run-time, the volume required by 8.64 times more Li Ion capacity is roughly
256 times greater than that required by the converter. If a shorter run-time is targeted,
the additional battery volume needed to achieve the same percentage of enhancement is
smaller, but, because its power handling requirements are unchanged, the volume of the
DC-DC converter remains the same. Thus, for short run-times, adding battery capacity
requires less volume than adding a DC-DC converter. However, based on the same
factors of this example, for any run-time longer than two minutes, the additional battery
volume is still greater than the volume of the converter.
It may be concluded that, with the exception of systems designed for very short
run-times, enhancing system run-time by adding a DC-DC converter will typically
involve only a small increase in volume, much smaller than the increase in battery
volume that would be needed for the same increase in run-time.

3.1 Introduction to Switching Regulators 42
Chapter 3
DC-DC Converter
Fundamentals
This chapter introduces switching regulators and the requirements imposed on
these regulators by the portable environment. Design equations and closed-form
expressions for losses are presented for the three basic low-voltage CMOS switching
regulator topologies − buck, boost, and buck-boost − controlled via pulse-width or
pulse-frequency modulation. Also introduced are alternative, inductor-less regulator
topologies which have advantages in a specialized class of portable applications.
3.1 Introduction to Switching Regulators
The switching regulator shown in Figure 3.1 converts an unregulated battery
source voltage Vin to the desired regulated DC output voltage Vo . A single-throw,
double-pole switch chops Vin producing a rectangular wave having an average voltage
equal to the desired output voltage. A low-pass filter passes this DC voltage to the
output while attenuating the AC ripple to an acceptable value. The output is regulated
by comparing Vo to a reference voltage, Vref , and adjusting the fraction of the cycle for
which the switch is shorted to Vin . This pulse-width modulation (PWM) controls the
Unregulated dc Low-Pass Regulated dc

Output
+ Filter +
Vin RL Vo
- -
Frequency fs
Duty Cycle D
-
PWM + Vref
Error Amplifier
Fig. 3.1: Block diagram of a PWM switching DC-DC converter.
average value of the chopped waveform, and thus controls the output voltage. Unlike a
switched-capacitor converter (see Section 3.6.2) a switching regulator has an efficiency
which approaches 100% as the components are made more ideal. In practice,
efficiencies above 75% are typical, and efficiencies above 90% are attainable.
There are several simple alternative arrangements of the switching and filter
components that can be used to produce an output voltage larger or smaller than the
input voltage, with the same or opposite polarity. Some of these will be discussed
below. However, many of the design issues are similar, so first one topology, the step-
down (buck) converter, will be discussed in more detail.
3.1.1 Buck Converter
The power train of the low-output-voltage buck circuit, which can produce any
arbitrary output voltage 0 ≤ V o ≤ V in , is given in Figure 3.2. The basic PWM operation
is as follows: The power transistors (pass device M p and rectifier M n ) chop the battery
input voltage Vin to reduce the average voltage. This produces a square wave of variable
duty cycle D and constant period Ts = f s -1 at the inverter output node, v x . A typical
periodic steady-state v x (t) waveform is shown in Figure 3.3. The second-order low-pass
+
Mp iLf
Vin Cin
+ Lf +
Mn vx Cf Vo
- - -
Fig. 3.2: Low-output-voltage buck circuit
PMOS
Vin
on
NMOS vx(DC) = Vo
on
0
DTs (1-D)Ts
Fig. 3.3: Nominal periodic steady-state vx(t) buck circuit waveform
filter (L f and C f ) passes the desired DC component of this chopped signal, while
attenuating the AC to an acceptable ripple value. In the ideal case, the DC output
voltage is given by the product of the input voltage and the duty cycle:
V o = V in ⋅ D (Eq 3-1)
The switching pattern of M n and M p is pulse-width modulated, adjusting the
duty cycle of the rectangular wave at v x , and ultimately, the DC output voltage, to
compensate for input and load variations. The pulse-width modulation is controlled by
a negative feedback loop, shown in the block diagram of Figure 3.1, but omitted from
Figure 3.2 for simplicity. Some detail on ultra-low-power PWM design is included in
Chapter 4.
3.2 DC-DC Requirements in Portable Systems 45
3.2 DC-DC Requirements in Portable Systems
Figure 3.4 summarizes the primary requirements of DC-DC converters in
portable electronic systems. The following subsections elaborate on these requirements.
3.2.1 High Energy Efficiency
Since battery capacity is limited in any portable electronic device, power
minimization is crucial. DC-DC converters must dissipate minimal energy to extend
system run-time, a requirement which is particularly challenging in the low-voltage and
low-current applications common to a battery-operated device. In the portable
multimedia Infopad terminal, the six voltage converters are the dominant source of
power dissipation, consuming 42% of the total system power [Truman98].
A number of power management schemes are used in most low-power
hardware: Unused circuitry is powered-down and gated clocks are employed to reduce
power consumption during idle mode [Chandrakasan94b]. Such techniques may present
severe load variations (up to several orders of magnitude), and the system may idle for
a large fraction of the overall run-time. This implies the need for a high conversion
Low noise emissions
Small size and low cost
Support low voltage with high efficiency
Fig. 3.4: DC-DC converter requirements in portable electronic systems.

efficiency not only under full load, but over a large load variation. Furthermore, in the
ultra-low-power applications common to portable systems, the quiescent operating
power (control power) of the regulator must be kept to an even lower level to ensure
that it does not contribute significantly to the overall dissipation. For example, a
multimedia chipset has been demonstrated in [Chandrakasan94a] which supports speech
I/O, pen input and full motion video, and consumes less than 5 mW at 1.1 V. The
control circuit for a converter supplying this chipset must have substantially lower
quiescent power.
Section 3.3.2 and Section 3.4.2 summarize the fundamental mechanisms of
loss in the low-voltage CMOS buck converter. Chapter 4 introduces a number of
techniques at the power system and circuit levels to improve the energy efficiency of
these converters. At the power system level, resource sharing between converters is
used to minimize control system overhead. Low-voltage digital control which exploits
existing sub-system voltages is proposed to further reduce control power. A number of
power train circuit optimizations for high efficiency at ultra-low output voltages are
presented.
3.2.2 Low Cost
As portable electronic devices become increasingly sophisticated, and a
greater variety of technologies are integrated into a single system, their voltage
conversion needs grow. While successive generations of high performance digital ICs
demand progressively lower-voltage supplies, analog and data conversion chips
continue to require higher voltages for headroom and signal distortion considerations.
In addition, 3.3 V, 5 V, and 12 V standards remain in most systems for backward
compatibility to existing components.
Cost is often the primary consideration in consumer electronics. A high-
performance DC-DC converter, including the IC and all external components, can cost
as much as nine dollars 1 . Since as many as six DC-DC converter outputs may be
required in a portable electronic device [Truman98], the overall power system may
contribute substantially to the overall cost of the device.
High levels of functional integration, as proposed in Chapter 4, can be used to
reduce the cost of the power system. Current-day DC-DC converters require as many as
ten external components. The design methodology presented in Chapter 4 reduces this
number to three: One input bypass capacitor, and an output filter inductor and capacitor.
In addition, the methodology allows for the integration of several power supplies on a
single IC, further reducing cost. Finally, since vanilla digital CMOS integration is
proposed, small custom power supplies can be integrated together with their own digital
CMOS loads.
Nevertheless, regardless of the number of supplies integrated on a single chip,
each DC-DC converter output requires its own external filter elements. These
components, particularly the inductor, can be quite expensive. In Chapter 4, high
operating frequencies are proposed to reduce the values of these elements, thereby
reducing their cost. In addition, a “minimum inductor” design is presented to trade
decreased inductance for increased capacitance, resulting in an overall lower cost.
3.2.3 Small Size
The portability requirement places severe constraints on physical size and
mass. Since several DC-DC converters are required in almost any portable electronic
device, minimization of the physical size of each is a key design objective. The six
voltage converters in the Infopad terminal consume 12% of the printed circuit board
surface area [Truman98]. In addition, the large inductors in DC-DC converters often
determine the height of end-products such as cellular phones and pagers.
1. Cost of the MAX887 purchased through a distributor in volumes of 1000, including 10 external compo-
nents.
The techniques described in Section 3.2.2 for power system cost reduction are
equally effective in reducing overall power system size. Higher levels of functional
integration can be used to minimize external component count. Integration of multiple
power supplies on a single IC, and power supplies together with their loads reduces the
total number of IC packages.
Further optimizations can be made at the power system level. As indicated in
Chapter 4, converter topology and battery voltage choices can have a profound impact
on the size of the overall power system. In addition, since there is a fundamental trade-
off between the size of a DC-DC converter and its losses (see Section 4.1.1) the size
and efficiency of different converters in the system may be traded to yield the optimum
power system design.
In low-power applications, the external components usually dominate the
physical size of a DC-DC converter. Higher operating frequencies reduce the required
values of inductance and capacitance, and ideally, their form factor. “Minimum
inductor” designs yield the minimum form factor inductor for a given application.
3.2.4 Low Noise
DC-DC converters are traditionally among the noisiest components in any
electronic system. Their switching noise generates interference, which is of particular
concern in wireless communications applications. As a result, many cellular handset
manufacturers use linear, rather than switching regulators for all DC-DC down-
conversion, despite the negative impact on battery run-time.
Several approaches are used to combat switching noise in DC-DC converters.
The converters are used only in PWM mode, where the switching frequency (and
therefore, the frequencies of fundamental and harmonic switching noise) is known. The
switching frequency is chosen so that the higher-order harmonics are kept outside of the
3.3 PWM Operation 49
sensitive IF band, minimizing the effects of spurious transmissions on radio
performance. The magnitude of the noise is reduced with careful physical design. All
power traces in the PCB are kept short and wide, minimizing the area, and thus the stray
inductance, in all critical high current loops. A closed-core output filter inductor design
offers a closed magnetic path to contain flux. Finally, a more recent innovation called
soft-switching (see Chapter 4) is proposed to control the high frequency noise
emissions.
3.3 PWM Operation
Figure 3.5 shows the steady-state operating waveforms of the buck circuit in
PWM operation. The switching cycle is initiated when PMOS device, M p , turns on.
During the interval, D, of the switching period, Ts , the inverter output node, v x , is
shorted to Vin . A constant positive potential, Vin -Vo , is applied across the inductor, and
i Lf linearly increases from its minimum value to its maximum value. Some of the
energy removed from the battery is stored in the magnetic field of the inductor, and
some is delivered to the filter capacitor and the load.
Then, the PMOS device is turned off, and the NMOS rectifier device, M n , is
turned on to pick up the inductor current, shorting v x to ground. During this interval,
(1-D) of the cycle, a constant negative potential is applied across the inductor, and i Lf
linearly decreases from its maximum value to its minimum value. Excess energy in the
inductor is delivered to the output filter capacitor and load. The cycle then repeats by
turning off M n and turning on M p .
In periodic steady-state, regulation is maintained when the charge drawn from
the battery during a switching period is equal to the charge consumed by the load.
Vin Ts
vx (t) 0
Io
iLf (t) ∆I
0
Vin
vgp (t) 0
Vin
vgn (t) 0
d Ts (1-d) Ts
Fig. 3.5: Periodic steady-state PWM waveforms for the buck circuit.
3.3.1 Output Filter Design
In Figure 3.6, the rectangular wave of the inverter output node is applied to the
second order low-pass output filter of the buck circuit (L f and C f ) which passes the
desired DC component of v x while attenuating the AC component to an acceptable
ripple value. Load R L draws a DC current I o from the output of the filter. Figure 3.7
shows the nominal steady-state i Lf(t) and v o (t) waveforms for a rectangular input v x (t).
iLf
Io
vx (t) +
Lf +
Cf Vo RL
(D, fs)
-
-
Fig. 3.6: The output filter of the buck circuit (Lf and Cf) with load RL.
Vin DTs vx (t)
Ts
iLf (t)
∆I Io
vo (t)
∆V Vo
Fig. 3.7: Nominal steady-state waveforms of the buck circuit output filter.
In order to achieve the large attenuation needed in a practical power circuit,
–2
L f ⋅ C f » ω s , where ω s = 2πf s , and f s is the switching frequency of the converter. In
this case, the filter components may be sized independently, using time domain
analysis, rather than frequency domain analysis. Neglecting the effects of output
voltage ripple ( v o – AC « v x – AC ) , for a rectangular input with period Ts , the AC
inductor current waveform is triangular with period Ts and peak-to-peak ripple ∆I
symmetric about the average load current I o . The peak-to-peak current ripple may be
found by integrating the AC component of the v x (t) waveform over a fraction, D, of one
cycle, yielding:
V in ⋅ D ⋅ ( 1 – D ) Vo ⋅ ( 1 – D )
∆I = ---------------------------------------- = ----------------------------- (Eq 3-2)
Lf ⋅ fs Lf ⋅ fs
The output filter capacitor is selected to ensure that its impedance at the
switching frequency, including its equivalent series resistance (ESR), is small relative
to the load impedance. Thus, the AC component of the inductor current flows into the
filter capacitor, rather than the load. For many capacitor technologies at frequencies
above several hundred kilohertz, the resistive impedance dominates over the capacitive
impedance. In high-current-ripple designs, a primary design goal is to minimize ESR to
reduce both output voltage ripple and conduction loss (see below). For this reason, a
high-Q capacitor technology, such as multilayer ceramic, is typically used, and even at
high frequencies, ESR may be neglected in calculating output voltage ripple.
Considering only capacitive impedance, the peak-to-peak output voltage ripple may be
found through charge conservation. Assuming the AC inductor current flows only into
the filter capacitor:
∆I Vo ⋅ ( 1 – D )
∆V = ---------------------- = -------------------------------- (Eq 3-3)
8 ⋅ Cf ⋅ fs 8 ⋅ Lf ⋅ C f ⋅ f s
2
This output voltage ripple is symmetric about the desired DC output voltage
Vo , and, for the v x (t) waveform shown in Figure 3.7, is piecewise quadratic with period
Ts .
(Eq 3-2) and (Eq 3-3) illustrate the two principle means of miniaturizing a DC-
DC converter. First, it can be readily seen that the necessary values of filter inductance
–1
and capacitance decrease with f s . Thus, a higher operating frequency typically results
in a smaller converter. Second, because the requirement of interest is output voltage
ripple, it is the L f ⋅ C f product, rather than the values of the individual components, that
is important. Through choice of a higher current ripple, ∆I, a lower filter inductance
solution may be obtained, often resulting in a smaller supply.

3.3.2 Sources of Dissipation
The power train of the low-output-voltage buck circuit, including all series
resistance, parasitic capacitance C x , stray inductance L s , and drain-body diodes of the
power transistors, is shown in Figure 3.8. Listed below are the chief sources of
dissipation that cause the conversion efficiency of this circuit to be less than unity. In
Chapter 4, methods which reduce these losses are described.
3.3.2.1 Conduction Loss
Current flow through non-ideal power transistors, filter elements, and
interconnections results in dissipation in each component:
2
P q = i rms ⋅ R (Eq 3-4)
where i rms is the root mean squared current through the component, and R is the
resistance of the component.
In PWM mode, the rms current has a DC and an AC component:
2 2 2
i rms = i rms ( DC ) + i rms ( AC ) (Eq 3-5)
where:
Ls
+
Rbat RCin Mp iLf
Vgp Io
Rs
Vin Cin
Lf RCf +
Vgn
Mn Cx Cf Vo RL
- -
Fig. 3.8: Low-output-voltage buck circuit, including parasitics.

2 2
i rms ( DC ) = d ⋅ I o (Eq 3-6)
and
1 ∆I 2
i rms ( AC ) = d ⋅ --- ⋅  ------
2
(Eq 3-7)
3  2
Here, 0 ≤ d ≤ 1 is a weighting factor which indicates the duty cycle of current flow
through the component, I o is the DC load current, and ∆I is the peak-to-peak inductor
current ripple.
While DC conduction loss scales quadratically with decreasing load current,
AC conduction loss is a fixed quantity and may substantially degrade efficiency at light
load.
3.3.2.2 Gate-Drive Loss
Raising and lowering the gate of a power transistor each cycle dissipates an
average power:
Pg = Eg ⋅ fs (Eq 3-8)
where E g is directly proportional to the gate energy transferred per off-to-on-to-off gate
transition cycle (which can include some energy due to Miller effect), and includes
dissipation in the drive circuitry (see Section 4.2.5.4).
Gate-drive loss is independent of load current and will therefore degrade light-
load efficiency.
3.3.2.3 Timing Errors
Three mutually exclusive mechanisms of loss attributed to timing errors in the
switching of the power MOSFETs are described below. Each is independent of load.
No Dead-Time: Short Circuit Loss
A short-circuit path may exist temporarily between the input rails during
power FET switching transitions. To avoid potentially large short-circuit losses, it is
necessary to provide dead-times in the conduction of the MOSFETs to ensure that the
two devices never conduct simultaneously.
Dead-Times Too Long: Body-Diode Conduction
If the durations of the dead-times are too long, the body diode of the NMOS
power transistor may be forced to pick up the inductor current for a fraction of each
cycle. Since in low-voltage applications, the forward bias diode voltage ( V d ≈ 0.7 V )
can be comparable to the output voltage, its conduction loss may be significant:
P diode ≈ 2 ⋅ I o ⋅ V d ⋅ t err ⋅ f s (Eq 3-9)
where t err is the timing error between complementary power MOSFET conduction
intervals.
Furthermore, when the PMOS device is turned on, it must remove the excess
minority carrier charge from the body diode, dissipating an energy bounded by:
E rr = Q rr ⋅ V in (Eq 3-10)
where Q rr is the stored charge in the body diode.
Dead-Times Too Short: Capacitive Switching Loss
In a hard-switched converter, MOSFET M p charges parasitic capacitance C x to
Vin each cycle, dissipating an average power:
1 2
P Cx ( LH ) = --- ⋅ C x ⋅ V in ⋅ f s (Eq 3-11)
2
where C x includes reverse-biased drain-body junction diffusion capacitance C db and
some or all of the gate-drain overlap (Miller) capacitance C gd of the power transistors,
wiring capacitance from their interconnection, and stray capacitance associated with L f .
In ultra-low-power monolithic converters, C x may be dominated by parasitics
associated with the connection of an off-chip filter inductor, which include a bond pad,
bond wire, pin, and board interconnect capacitance.
When M p is turned off, the inductor begins to discharge C x from Vin to ground.
If M n is turned on exactly when v x reaches ground, this transition is lossless. If the
NMOS device is turned on too late, v x will be discharged below ground, until the body
diode is forced to conduct (see above). If the NMOS device is turned on too early, it
will discharge v x to ground through its channel, introducing losses:
1 2 1 2
P Cx ( HL ) = --- ⋅ C x ⋅ v x ⋅ f s ≤ --- ⋅ C x ⋅ V in ⋅ f s (Eq 3-12)
2 2
3.3.2.4 Stray Inductive Switching Loss
Energy storage by the stray inductance L s in the loop formed by the input
decoupling capacitor C in and the power transistors causes dissipation (Figure 3.9).
iLs φ
Imax
Ls i(t)
Mp Imin
φ i (t) iLs(t)
Mn
φ ELs = 0 ELs = 1/2 Ls Imax2
i (t)
ELs = 1/2 Ls Imin2 ELs = 0
Fig. 3.9: Energy dissipation due to stray inductance.

Here, M p and M n are modeled as ideal switches, and L f is modeled as a current source
of value i(t) = i Lf (t). When switch M p closes, it charges L s from i Ls = 0 to i Ls = I min .
When M p opens and M n closes, L s is discharged from i Ls = I max to i Ls = 0. The average
power dissipation is equal to:
1 2 2
P Ls = --- ⋅ L s ⋅ ( I min + I max ) (Eq 3-13)
2
This loss is somewhat dependent on load current, as:
∆I
I min = Io – ------ (Eq 3-14)
2
and
∆I
I max = I o + ------ (Eq 3-15)
2
The value of L s is dependent on PCB layout, packaging, bonding, and chip
layout, and is reduced by minimizing the area of this critical high current loop. In a
multilayer interconnection technology, the lowest stray inductance is achieved by using
a conductor that overlaps a return path in a different layer, with thin dielectric
separating the layers. In a careful design:
1 nH < Ls < 10 nH (Eq 3-16)
3.3.2.5 Quiescent Operating Power
The PWM and other control circuitry consume static power. In low-power
applications, this control power may contribute substantially to the total losses, even at
full-load.
3.4 PFM Operation 58
3.4 PFM Operation
While a PWM DC-DC converter can be made to be highly efficient at full load,
many of its losses are independent of load current, and it may, therefore, dissipate a
significant amount of power relative to the output power at light loads. Figure 3.10
plots total losses versus a 1000:1 load range for a typical PWM buck converter. As the
load scales downward, AC conduction loss, switching loss, and PWM control power
become increasingly significant, and total dissipation in the converter asymptotes to a
fixed minimum power dissipation. From this plot, it may be concluded that a PWM
converter which is 94% efficient at full load is roughly 3% efficient at one thousandth
full load. If the converter is used at full load for little of its operating time, energy loss
at light load will be the dominant limitation on battery run-time, and improving
efficiency at light load becomes essential.
PWM Converter Losses vs. Output Power

6
5.5
5
Pdiss [% of full load]
4.5
3.5
3
−3 −2 −1 0
10 10 10 10
Pout [normalized to full load]
Fig. 3.10: PWM converter losses vs. load.

ACTIVE
PFM control IDLE
Lf delivers charge Cf sources Io
V+
vo (t)
VREF
V-
Fig. 3.11: A conceptual illustration of PFM control.
One control scheme which achieves high efficiency over a wide load range is
pulse-frequency modulation (PFM). In this scheme, conceptually illustrated in Figure
3.11, the converter is operated only in short bursts at light load. Between bursts, both
power FETs are turned off, and the circuit idles with zero inductor current. During this
period, the output filter capacitor sources the load current. When the output is
discharged to a certain threshold below V REF, the converter is activated for another
burst, returning charge to C f . Thus, the load-independent losses in the circuit are
reduced. As the load current decreases, the idle time increases. Regulation is
maintained when the charge delivered through the inductor is equal to the charge
consumed by the load.
One major drawback of PFM control is that the switching period (the time
between charge bursts) is a function of load. Thus, the converter appears almost chaotic
and the switching noise is unpredictable. This is not well-suited to wireless
communications applications. However, PFM mode can be used judiciously during
periods of radio inactivity by tying the converter’s operating mode to the pulse timing
of the radio. For example, during the page/scan mode of a TDMA RF system, the
converter can be commanded into PWM mode, where the spectrum of the switching
noise is well-controlled, while the receiver is active. During the periods of receiver
inactivity, the converter can be commanded into PFM mode for high energy-efficiency.
3.4.1 Output Filter Design
Figure 3.12 shows the steady-state buck circuit waveforms under PFM control.
The PFM operation is described heuristically in Figure 3.11: When the output voltage
drops to a certain threshold below V REF (likely sensed by a hysteretic comparator), a
burst of charge is delivered, returning Vo to a threshold above V REF. (Unlike the
waveforms of Figure 3.11, here, only a single switching event of the DC-DC converter
is used to deliver each burst of charge.) This charge burst is delivered with high energy
efficiency through the inductor as follows: The PMOS device is turned on for a time
interval, T pmos . Some of the energy removed from the battery is delivered to the output;
the rest is stored in the inductor. During this interval, the inductor current slews at a
rate of:
di L ( V in – V o )
-------- = -------------------------
- (Eq 3-17)
dt Lf
and reaches its peak value of i Lf = I p at the conclusion of the PMOS conduction
interval. The PMOS device is then turned off, and after a short dead-time, the NMOS
vo (t)
VREF
T Vin
vx (t)
Vo
0
Tidle
Tnmos Tpmos
Ip
iLf (t) iLf(AVE) = Io

0
Fig. 3.12: Steady-state PFM waveforms.

device is turned on to pick up the inductor current. During NMOS conduction, v x is
shorted to ground, and the energy stored in the inductor is released to the output. The
inductor current slews from I p to 0 at a rate of:
di L –V
-------- = ---------o- (Eq 3-18)
dt Lf
The NMOS device is (ideally) turned off when i Lf decays to zero. At this time,
v x will ring up to Vo , and the circuit will idle with zero inductor current and the output
capacitor sourcing the load current.
The total charge delivered through the inductor by each PFM burst is found by
integrating the area under the i Lf (t) waveform for one switching cycle of the DC-DC
converter:
1
Q L = --- ⋅ I p ⋅ ( T pmos + T nmos ) (Eq 3-19)
2
Because a time delay is fairly straightforward to implement on-chip, a convenient PFM
controlling variable is the PMOS conduction interval, T pmos . The NMOS conduction
interval is uncontrolled, but can be found in relation to the controlling variable by
equating the products of the linear inductor current slopes and the conduction intervals
to the peak current, I p :
( V in – V o ) ⋅ T pmos V o ⋅ T nmos
I p = ---------------------------------------------- = -------------------------- (Eq 3-20)
Lf Lf
( V in – V o )
T nmos = -------------------------- ⋅ T pmos (Eq 3-21)
Vo
In terms of only the controlled variable,

2
1 T pmos ⋅ ( V in – V o ) ⋅ V in
Q L = --- ⋅ ----------------------------------------------------------- (Eq 3-22)
2 Vo ⋅ Lf
Regulation is maintained when this delivered charge is equal to the charge
consumed by the load:
QL = Io ⋅ T (Eq 3-23)
where
T = Tidle + Tpmos + Tnmos (Eq 3-24)
is the variable PFM repetition period.
Inductor Value
To support a maximum load current, I o(max) :
T pmos ⋅ ( V in – V o )
L f = ---------------------------------------------- (Eq 3-25)
2 ⋅ Io ( max )
As indicated by (Eq 3-22), a smaller value of inductance than that given in (Eq 3-25)
will support a larger load current, and will support I o(max) with a larger time between
pulses, Tidle .
Capacitor Value
The capacitor is selected to ensure that the peak-to-peak output voltage ripple,
∆V, is maintained to a certain percentage of Vo . The worst-case output voltage ripple is
calculated assuming that all of the charge delivered through the inductor is absorbed by
Cf:
QL
∆V = ------- (Eq 3-26)
Cf
3.4.2 Sources of Dissipation
The mechanisms of loss in PFM operation are identical to those presented in
Section 3.3.2 for PWM operation. However, PFM converters are shut down during the
idle time, Tidle , between pulses and, with the exception of some static dissipation in the
control circuits, dissipate energy only during pulses. Thus, the analysis below presents
losses in terms of the energy dissipated per PFM pulse.
Assuming a small AC voltage ripple ∆V « V o , the energy delivered to the load
in one PFM pulse is given by:
E pulse = Q L ⋅ V o (Eq 3-27)
The overall efficiency of the converter in PFM operation is then expressed as the ratio
given by:
E pulse
η = ---------------------------------- (Eq 3-28)
E pulse + E diss
3.4.2.1 Conduction Loss
Current flow through non-ideal power transistors, filter elements, and
interconnections results in energy dissipation in each component:
T pulse
∫
2
Eq = i ( t ) R dt (Eq 3-29)
0
where i(t) is the current through the component, T pulse = T pmos + T nmos , and R is the
resistance of the component.
3.4.2.2 Gate-Drive Loss
Raising and lowering the gate of a power transistor each cycle dissipates an
energy E g . This is directly proportional to the gate energy transferred per off-to-on-to-
off gate transition cycle (which can include some energy due to Miller effect), and
includes dissipation in the drive circuitry.
3.4.2.3 Switch Transitions and Timing Errors
PMOS Turn-On
The power PMOS device is always turned on with the converter idling − in
steady-state, v x = Vo and i Lf = 0. The energy stored on C x just prior to PMOS turn-on is:
1 2
E Cx ( initial ) = --- ⋅ C x ⋅ V o (Eq 3-30)
2
The PFM switching cycle is initiated when M p charges C x from v x = Vo to v x = Vin . The
energy stored on C x just after this transition is:
1 2
E Cx ( final ) = --- ⋅ C x ⋅ V in (Eq 3-31)
2
The energy drawn from the battery during this transition is equal to:
E in = V in ⋅ ∆Q Cx = V in ⋅ C x ⋅ ( V in – V o ) (Eq 3-32)
The energy dissipated in the turn-on transition is therefore given by:
1 2
E Cx ( IH ) = E in – ( E Cx ( final ) – E Cx ( initial ) ) = --- ⋅ C x ⋅ ( V in – V o ) (Eq 3-33)
2
where the IH subscript denotes the idle-to-high transition at v x .
PMOS Turn-Off, NMOS Turn-On
The PMOS off to NMOS on transition is nearly identical to that in PWM mode
(Section 3.3.2.3). With no dead-time provided, a short-circuit path may exist
temporarily during switch transitions, introducing significant loss. If the dead-time is
too short, M n discharges C x through its resistive channel, introducing a loss bounded
by:
1 2
E Cx ( HL ) ≤ --- ⋅ C x ⋅ V in (Eq 3-34)
2
(The subscript HL indicates the high-to-low transition at v x .)
If the dead-time is too long, the inductor discharges C x below ground, until the
NMOS body diode becomes forward-biased.
NMOS Turn-Off
Ideally, the NMOS device is gated off when i Lf decays to zero. In this case, the
i Lf (t) and v x (t) waveforms will ring from the initial condition, i Lf (t) = 0, v x (t) = 0, to the
final steady-state condition during idle mode, i Lf (t) = 0, v x (t) = Vo in the resonant
circuit of Figure 3.13. Since in any practical DC-DC converter, C f » C x , in this circuit
the output capacitor is modeled as an ideal voltage source. The ringing v x (t) and i Lf (t)
waveforms are shown in Figure 3.14.
The energy dissipated in this ring (in the equivalent series resistance in the L f -
C x -C f tank, R) is fundamentally equal to:
1 2
E Cx ( LI ) = --- ⋅ C x ⋅ V o (Eq 3-35)
2
iLf (t)
+ Lf +
R
vx (t) Cx Vo
- -
Fig. 3.13: Resonant tank during PFM idle time interval.
vx (t)
v x ( max ) = 2V o
τ LC = LfCx ( Cx « Cf )
Vo
t
iLf (t)
t
Vo
i Lf(min) = – --------------------
Lf ⁄ Cx
Fig. 3.14: LC ring after NMOS turn-off.
The LI subscript in (Eq 3-35) indicates the low-to-idle transition at v x . Note that if:
v x ( max ) = 2V o > V bat + V D (Eq 3-36)
where V D is the PMOS forward bias diode voltage (approximately equal to 0.7 V), the
PMOS body diode will conduct for a portion of the first sinusoidal cycle, dissipating
additional energy.
If the NMOS device turns off too early (i Lf = I ε > 0), additional energy stored
in the output inductor is dissipated. For:

iLf (t)
- Lf +
VD NMOS Vo
body diode
+ -
Fig. 3.15: Equivalent circuit during NMOS body diode conduction.
VD t
vx(t)
iLf(t)
slope = -(Vo + VD) / Lf
Id
Body diode Body diode

turn-on turn-off
Fig. 3.16: Waveforms during NMOS body diode conduction.
1 2 1 2
E L = --- ⋅ L ⋅ I ε < E C = --- ⋅ C x ⋅ V D (Eq 3-37)
2 2
where V D is the forward bias NMOS diode voltage (also approximately equal to 0.7 V),
the NMOS body diode will not forward bias, and all of E L will be dissipated in the
resistance in series with the LC tank. If the condition of (Eq 3-37) is not satisfied, the
NMOS body diode will conduct, dissipating some of E L and delivering the rest to the
output. Figure 3.15 and Figure 3.16 show the equivalent circuit and i Lf (t) and v x (t)
waveforms during NMOS body diode conduction. Since the voltage drop across the
diode is large compared to that across any resistance in series with the LC tank, R is
eliminated from this model, leaving the body diode as the only dissipater. In this case,
the ratio of energy dissipated to energy stored is equal to the ratio of voltage drop
across the diode to that across the inductor:
VD
E diode = E L ⋅ -------------------------------------- (Eq 3-38)
V bat + V D – V o
where
1 2
E L = --- ⋅ L ⋅ I d (Eq 3-39)
2
and
VD
I d = I ε – -------------------- (Eq 3-40)
L f ⁄ Cx
In addition,
1 2 2
E R = --- ⋅ C x ⋅ ( V o + V D ) (Eq 3-41)
2
is dissipated in the series R before and after body diode conduction, resulting in an
1 2
energy penalty of --- ⋅ C x ⋅ V D .
2
From the above results, the total energy penalty associated with an early
NMOS turn-off transition is:
1 2 VD
E penalty = --- ⋅ L ⋅ I ε I ε < -------------------- (Eq 3-42)
2 Lf ⁄ Cx
1 2 1 2 VD otherwise
E penalty = --- ⋅ C x ⋅ V D + --- ⋅ L ⋅ I d ⋅ ---------------------
2 2 Vo + V D
If the NMOS device turns off too late (i Lf = I ε < 0) some or all of the energy
stored in the inductor is dissipated in the series resistance and/or the PMOS body diode.
Since the analysis is similar to the derivation of (Eq 3-42), only the resulting losses are
given:
1 2 ( V D + V bat ) (Eq 3-43)

E penalty = --- ⋅ L ⋅ I ε for I ε < ------------------------------
2 Lf ⁄ Cx
1 2 1 2 VD otherwise
E penalty = --- ⋅ C x ⋅ ( V D + V bat ) + --- ⋅ L ⋅ I d ⋅ --------------------------------------
2 2 V bat + V D – V o
In (Eq 3-43),
( V D + V bat )
I d = I ε + ------------------------------ (Eq 3-44)
L f ⁄ Cx
and is less than zero.
3.4.2.4 Stray Inductive Switching Loss
Energy storage by the stray inductance L s in the loop formed by the input
decoupling capacitor C in and the power transistors causes dissipation (Figure 3.9). In
the PFM PMOS turn-on transition, i Lf = 0, and since no energy is stored in L s , there is
no associated loss. The PMOS turn-off / NMOS turn-on transition occurs when the peak
inductor current, I p , flowing into the power circuit is switched from the high-side to the
low-side input terminal, introducing a loss equal to:
1 2
E Ls = --- ⋅ L s ⋅ I p (Eq 3-45)
2
3.4.2.5 Quiescent Operating Power
The PFM control circuitry consumes static power, even when the converter is
idling. The energy dissipation per charge burst is given by:
E static = P static ⋅ T (Eq 3-46)

3.5 Other Topologies 70
where T is the variable PFM repetition period.
This proves to be the fundamental limitation to light-load efficiency under
PFM control. Since T increases with decreasing load, E static becomes the dominant
source of light-load loss. Effort must therefore be concentrated on minimizing this
static power dissipation.
3.5 Other Topologies
Two other basic configurations for PWM switching converters are the boost
converter (Figure 3.17) and the buck-boost converter (Figure 3.19). All three basic
topologies − buck, boost, and buck-boost − are similar in that they each have two
complementary switches and one inductor. Their conversion ratios may all be adjusted
by varying the duty cycle with frequency held constant. They can all be derived from
the same basic switching cell [Kassakian91].
The boost converter produces output voltages V o ≥ V in . A typical steady-state
v x (t) waveform is shown in Figure 3.18. In one portion of the cycle, (1-D), the NMOS
device is on, and the input voltage is applied across L f , building up current and thus
storing energy in the inductor. When the NMOS switch is turned off, the attempt to
interrupt the current in the inductor causes the voltage at node v x to rise rapidly. The
Lf
+ + +
Vin Cin vx Cf Vo
- - -
Fig. 3.17: Low-voltage CMOS boost circuit.

PMOS
Vo
on
NMOS Vx(DC) = Vin
0 on
DTs (1-D)Ts
Fig. 3.18: Nominal steady-state vx(t) boost circuit waveform.
PMOS device is turned on at this point, limiting the voltage produced by this inductive
kick to the voltage on the output capacitor. (If the PMOS device were not turned on, its
drain-body diode would short v x to one diode drop above Vo .) During the fraction of the
cycle, D, that the PMOS device conducts, some of the energy stored in the inductor is
transferred to the output, along with additional energy flowing from the input. The
cycle then repeats.
The boost converter may be considered a variation of the buck converter, but
with power flow from the lower voltage side to the higher voltage side. The voltage at
node v x is a rectangular wave whose DC component is equal to the input voltage. (It
must be equal, as the average voltage across the inductor must be zero for periodic
steady state.) Thus, the input and output voltages are related by:
V in = V o ⋅ D (Eq 3-47)
+ + -
Vin Cin vx Lf Cf Vo
- - +
Fig. 3.19: Low-voltage CMOS buck-boost circuit.

PMOS
Vin
on
NMOS Vx(DC) = 0
on
Vo
DTs (1-D)Ts
Fig. 3.20: Nominal steady-state vx(t) buck-boost circuit waveform.
the same relation as for the buck converter, but with the input and output terminals
reversed.
The operation of the buck-boost converter (Figure 3.19) is similar to that of the
buck converter, in that the cycle starts with the input voltage applied across the
inductor, in this case through the PMOS device for a duration, D ⋅ T s . However, when
the PMOS device is turned off, the voltage at v x heads downward, and the circuit
produces an output voltage polarity opposite to that of the input (Figure 3.20). The
energy transferred to C f during this portion, (1-D), of the cycle (while the NMOS
device conducts) is only the energy stored in the inductor, with none coming directly
from the input. Setting the average voltage across the inductor equal to zero allows the
conversion ratio to be found:
D
V o = V in ⋅ ------------- (Eq 3-48)
1–D
Note that this allows input voltages of smaller or larger magnitude than the input, hence
the name “buck-boost”.

3.6 Alternatives to Switching Regulators 73
3.6 Alternatives to Switching Regulators
For ultra-low-power applications, the complexity of a switching regulator may
prove prohibitive. In particular, the necessity of including a magnetic component may
preclude the use of a PWM DC-DC converter in many applications. Two alternatives
that do not require magnetic components are linear regulators and switched-capacitor
converters. Both types of circuits can be advantageous in ultra-low-power applications,
and in a limited range of other specialized applications.
3.6.1 Linear Regulators
Linear regulators, illustrated conceptually in Figure 3.21, are limited by two
principle constraints. The output voltage, Vo , must be less than the input voltage, Vin ,
and the efficiency, η, can never be greater than V o ⁄ V in . However, linear regulators
have the advantage of requiring few or no reactive components, and they can be very
small and simple. This makes them especially attractive for portable applications.
A linear regulator can be efficient only in applications that require an output
voltage just slightly below the input voltage. This requirement may be incompatible
with other system design constraints, but in some systems it is practical, and, in this
Pass Device
Unregulated dc Regulated dc
Vin
+
RL Vo
-
Vref
Error Amplifier
Fig. 3.21: Block diagram of a linear (series-pass) regulator.

case, a linear regulator may be highly efficient. The achievable efficiency then depends
on two parameters of the regulator: quiescent current and dropout voltage. The
quiescent current determines the regulator’s dissipation when the load is not drawing
current, and in ultra-low-power applications, it may also contribute significantly to
dissipation at full load.
If the input voltage of a linear regulator drops below a certain threshold,
regulation is lost, and the output voltage will sag below the nominal regulation point.
Dropout voltage is this minimum voltage difference between input and output required
to maintain regulation. If it is not very low, it can conflict directly with the design
requirement of having the output voltage only slightly less than the input voltage, and
will therefore preclude high efficiency. This becomes especially important in low-
voltage systems. With a 5 V output, a 1 V dropout voltage represents only a 20%
increase in the minimum input power over what would be required with zero dropout
voltage. However, with a 1 V output, a 1 V dropout voltage doubles the minimum input
power.
Linear regulator circuits with low quiescent power, and PNP or MOSFET pass
devices to allow low dropout voltage, are now commercially available. In the limited
class of circuits that require a regulated voltage just below the input voltage of the
regulator, these can provide a high-efficiency solution.
3.6.2 Switched-Capacitor Converters
Switched-capacitor converters (also known as charge pumps) are widely used
in ICs where a voltage higher than, or of opposite polarity to, the input voltage is
needed. Unlike a PWM converter, a switched-capacitor converter requires no magnetic
components. In addition, it is often possible to integrate the necessary capacitors, but
applications are usually limited to those in which poor efficiency and very low output
power are adequate.

φ1 φ2
+ +
φ2 Cs
Vin Vo
φ1
- -
Fig. 3.22: A switched-capacitor voltage doubler. Switches labeled φ1 and φ2 are closed alternately.
Figure 3.22 illustrates the basic principle of operation of a switched-capacitor
voltage doubler. The switches are closed in pairs, alternately. First the switches labeled
φ 1 are closed, charging capacitor C s to the input voltage, Vin . Then the φ 1 switches are
opened, and the φ 2 switches are closed. This places C s , which is now charged to Vin , in
series with the input voltage, producing a voltage of 2 ⋅ V in across the output. The cycle
then repeats. The output capacitor maintains the output voltage near 2 ⋅ V in during φ 1 .
The same converter topology can be used as a step-down converter, producing an output
voltage of half the input voltage, by exchanging the input and output terminals. By
using more complex configurations, it is possible to produce any rational conversion
ratio, for example by first stepping the voltage up by one integer ratio, and then
stepping down by another integer ratio. Some of the many possible topologies are
discussed in [Oota90] and [Harada92].
Like a PWM DC-DC converter, a switched-capacitor converter may be built
entirely of theoretically lossless elements − in this case, only switches and capacitors.
However, a switched-capacitor converter is not ideally lossless. As the parasitic
resistances in the capacitors and switches approach zero, the loss in the converter
approaches a non-zero limit. This is in contrast to a PWM converter, in which the losses
approach zero as parasitic effects are reduced.

The inherent losses in a switched-capacitor converter are due to unavoidable
dissipation which occurs when a pair of capacitors, charged to different voltages, are
shorted together through a switch. If two capacitors with values C1 and C 2 , initially
charged to voltages V 1(initial) and V 2(initial) , respectively, are shorted together through a
parasitic resistor R, the energy dissipated in the resistor will be:
1 C 1 C2 2
E diss = --- ⋅ ------------------- ⋅ ( V 1 ( initial ) – V 2 ( initial ) ) (Eq 3-49)
2 C 1 + C2
Note that this is independent of the value of R.
To better understand these losses, consider the efficiency of the voltage
doubler shown in Figure 3.22. During φ 2 , the equivalent circuit is as shown in Figure
3.23. The charge flowing to the output is supplied by both the input and C s . During φ 1 ,
this same quantity of charge must be supplied from the input and stored on C s for the
next cycle. Since all the charge that flows out of the output must be supplied twice by
the input, the average input current must equal twice the average output current, i.e.,
I in = 2 ⋅ I o . Thus, the efficiency is:
Vo ⋅ Io Vo
η = ------------------- = ---------------- (Eq 3-50)
V in ⋅ I in 2 ⋅ V in
+
Cs
+ Vo
Vin
- -
Fig. 3.23: Equivalent voltage doubler circuit during φ2.

The efficiency would be 100% if Vo were in fact twice Vin . However, in order
for a charge, Q, to flow into C s during φ 1 and subsequently flow out of C s during φ 2 , the
voltages applied across C s during the two phases must differ by an amount
∆V = Q ⁄ C s . Assuming that the RC time constant determined by the parasitic
resistance of the switches and C s is small compared to the switching period so that the
charge on C s reaches its steady-state value before the end of each phase, and that the
input and output capacitors are large enough to maintain constant Vin and Vo , the
voltage drop is ∆V = 2 ⋅ V in – V o . With a switching period of Ts , Q = I o ⋅ T s , and so:
Io ⋅ Ts
2 ⋅ V in – V o = -------------- (Eq 3-51)
Cs
The circuit may be modeled as shown in Figure 3.24, with an ideal doubler
(shown as an ideal transformer) followed by an effective resistance:
Reff = Ts / Cs (Eq 3-52)
that accounts for the voltage drop ∆V. The effective resistance also accounts for the
loss; calculating the dissipation in this resistor gives a result identical to that found
from (Eq 3-49).
In general, the model of a switched capacitor converter includes an ideal
transformer with a fixed rational turns ratio, N, and an effective resistance. The
conversion ratio, N, can be chosen to bring Vo near the desired output voltage; to
Reff = Ts / Cs
1:2
+ +
Vin Vo
- -
Fig. 3.24: Equivalent circuit for the switched-capacitor voltage doubler.

precisely regulate Vo , R eff is varied through changes in the switching frequency. Using
R eff for regulation is undesirable, since increasing it to lower the output voltage
produces additional power dissipation. However, N is fixed by the topology, and cannot
be used to regulate the output.
This is the main limitation of switched-capacitor converters: they can
efficiently convert voltages, but they cannot regulate these converted voltages any more
efficiently than a linear regulator. Thus, their efficient application is limited to
situations in which a voltage must be converted to another rationally related voltage,
but regulation is not necessary, or to situations in which the regulation range is limited,
and so the efficiency η = V o ⁄ ( N ⋅ V in ) is adequate.
In practice, there are several other considerations that limit efficiency in a
CMOS implementation of a switched-capacitor converter. In order for (Eq 3-52) to
hold, it is necessary for the time constant of the switched capacitor and the on-
resistance of the switch to be much less than the switching period, i.e. C s ⋅ R on « T s .
This requires the use of a large MOSFET to implement the switch, but the gate-drive for
that device then requires substantial power, especially if a high switching frequency is
used to minimize the required size of C s . Thus, gate-drive loss must be considered in
the design.
If an on-chip capacitor is used to implement C s , the stray capacitance from one
of its plates to ground will be a substantial fraction of its terminal capacitance. This
2
introduces C stray ⋅ V ⋅ f s loss, further hampering efficiency. Technologies for
fabricating capacitors with low stray capacitance to ground, or off-chip capacitors are
necessary to achieve high efficiency.

4.1 Converter Miniaturization 79
Chapter 4
DC-DC Design Techniques

for Portable Applications
The key requirements of DC-DC converters in portable electronic systems
were listed in Chapter 3. In this chapter, design techniques at the power system,
individual control system, and circuit levels are described which help meet the stringent
requirements imposed by battery operation. The focus is low-power portable
applications, where small size and high efficiency are the principal objectives.
Section 4.1 introduces circuit-level optimizations focused on reducing the size
and cost of a DC-DC converter in low-voltage and low-power portable applications. In
Section 4.2, circuit and control system techniques are described which eliminate,
minimize, or reduce the power dissipation due to each primary loss mechanism. Several
system-level considerations are presented in Section 4.3.
4.1 Converter Miniaturization
Since the portability requirement places severe constraints on physical size
and mass, the volume and mass of a converter can be a critical design consideration.
This section introduces several design techniques that may be used to reduce both the
size and cost of a PWM DC-DC converter.

4.1.1 High Frequency Operation
As indicated by (Eq 3-2) and (Eq 3-3), there are inherent size and cost
advantages associated with higher frequency operation. The reactive filter components
are likely to be the major contributors to the volume of a highly-integrated converter.
For the same impedance, jω s L or 1 ⁄ ( jω s C ) , a higher switching frequency,
f s = ω s ⁄ ( 2π ) , enables the use of reactive components with smaller value and smaller
–1
physical size. Ideally, the size of these components will decrease with f s . However, as
will be described in Section 4.2.4, if the operating frequency of the circuit is increased,
the sum of the losses in the power transistors and drive, if optimized, will increase
roughly with f s . Thus, the general theoretical relationship between the size of a DC-
DC converter and its losses is as illustrated in Figure 4.1. Here, operating frequency is
used as a parameter, and the sum of the losses in the power transistors and drive is
plotted against the volume of the converter.
If the cost and volume of the converter are decreased, additional space and
resources are left for a larger or better battery, compensating for lower conversion
3
Normalized Losses
Increasing fs
2
00 0.5 1.0 1.5 2.0

Normalized Volume
Fig. 4.1: General trends in power transistor losses versus the size of a DC-DC converter.
efficiency. The system requirements and battery characteristics will help to determine
which point on this curve is optimal for a specific application. For example, in systems
designed for shorter run-times, the volume of the converter can become comparable to
the volume of the battery, particularly if a battery with a relatively high volumetric
energy density is used. Then, it might be worthwhile to operate the converter at a higher
frequency, sacrificing efficiency while leaving space for additional battery capacity.
In Section 4.3, circuit-level optimizations are described which significantly
reduce the frequency-dependent losses in the power train, yielding a class of miniature
yet highly efficient converters that are well-suited for portable applications. In practice,
higher-frequency operation is limited not only by frequency-dependent losses in the
power train and controller, but also by diminishing returns in the miniaturization of the
filter components. Frequency limitations in inductive filter components are addressed
in [Kassakian91] and many other sources.
4.1.2 Minimum Inductor Selection
Since the L f C f product determines the output voltage ripple (Eq 3-3), the
relative size and cost of inductance versus capacitance should be considered in the
selection of these components. As the size, cost, and commercial availability of low-
voltage multilayer ceramic chip capacitors are often superior to those of inductors,
using large-value capacitors and small-value and small-size inductors is preferred. This
decision is restricted primarily by the increasing rms current in the inductor, which
circulates throughout the power train, increasing conduction loss in proportion to
2
i Lf ( rms ) .
The inductor current is approximated as a triangular AC waveform with peak-
to-peak ripple ∆I superimposed on the DC output current, I o , (see Figure 3.7). In Figure
4.2, ∆I is varied, and its effects on three key circuit parameters are shown. As
10
(Conduction Loss)
Normalized Circuit Parameters

I2Lf-rms = Io2 + 1/3 (∆I/2)2
1
(Physical Size)
E = 1/2 Lf (Io + ∆I/2)2
0.1
Lf ∝ ∆I-1
10-20.1 1 10
Current Ripple ∆I (Normalized to Load Io)
Fig. 4.2: The effect of increased current ripple on the value of Lf, the physical size of Lf, and
iLf(rms)2.
illustrated by (Eq 3-2), the value of filter inductance decreases with ∆I -1 . However, the
physical size of L f is roughly proportional to its peak energy storage, which in turn, is
given by:
∆I 2
E Lf = --- ⋅ L f ⋅  I o + ------
1
(Eq 4-1)
2  2
and is minimized for ∆I = 2I o . The rms current is:
∆I 2
I o + --- ⋅  ------
2 1
i Lf ( rms ) = (Eq 4-2)
3  2
and for ∆I = 2I o , the AC component of the current accounts for 25% of the overall full-
load conduction loss in the power train.
Although the preferred value of ∆I will depend slightly on the trade-off
between size and loss in a particular application, it can be concluded that a peak-to-
peak current ripple in the range I o < ∆I < 2Io is optimal for many applications. As ∆I is
decreased, the ripple-current contribution to total rms current (and so to conduction
loss) decreases. However, below ∆I = I o , further decreases in ∆I make little difference
in conduction loss at full load, and do not justify the larger inductor that would be
required. There is no obvious benefit for ∆I > 2I o , but this will be seen to be
advantageous for one mode of operation in Section 4.2.2.
4.1.3 High Integration
A completely monolithic supply (active and passive elements) would meet the
severe size and weight restrictions of a hand-held device. Because most portable
applications call for low-voltage power transistors, their integration in a standard logic
process is tractable. However, existing monolithic magnetics technology cannot provide
inductors of suitable value and quality for efficient power conversion [Barringer93].
Emerging magnetics technology may allow completely monolithic supplies (see
[Sullivan93]), but currently, magnetics, capacitors, and silicon circuitry are fabricated
separately and assembled at the board level or in a multi-chip module (MCM). The
extent of integration is the use of a monolithic silicon circuit, including all power
transistors with their drive, and all control circuitry.
Such a highly-integrated solution not only results in a more compact and cost-
effective design, it gives the designer more latitude in physical design and device
sizing, allowing application-specific optimizations which are likely to yield a more
efficient converter. Parasitics from both the active devices and interconnect may be
orders of magnitude lower on an IC than on a printed circuit board. Many of the
frequency dependent losses in a power circuit increase in direct proportion to the
energy storage of these parasitics; thus, integration enables higher efficiency at high
operating frequencies than that obtained by a discrete solution.

4.2 Circuit Techniques for High Efficiency 84
In Section 4.3.3, still higher levels of CMOS integration are proposed. By
integrating multiple supplies on a single die, and integrating small custom DC-DC
converters with their individual loads, the overall size and cost of the entire power
delivery system are further reduced.
4.2 Circuit Techniques for High Efficiency
The chief mechanisms of dissipation in a CMOS low-output-voltage buck
converter have been summarized in Section 3.3.2 and Section 3.4.2. In this section,
circuit techniques to eliminate, minimize, or reduce the dissipation due to these
mechanisms are described. While the following discussion is sometimes specific to the
buck circuit, all of the techniques presented here can be applied to maximize the
efficiency of boost and buck-boost type converters, each of which is typically required
in the power delivery scheme of a battery-operated system.
4.2.1 Synchronous Rectification
The focus of this chapter is the CMOS low-voltage buck converter, in which
the switching elements, modeled by the single-throw double-pole switch in the block
diagram of Figure 3.1, are implemented by complementary MOSFETs. The more
conventional implementation consists of one controlled switch and one uncontrolled
switch (a diode). The pure CMOS implementation allows an important advantage.

Consider the conventional buck circuit of Figure 4.3. Even if all other losses in
the circuit are made negligible, the maximum efficiency is limited by the forward bias
diode voltage, V diode . Since the diode conducts for a fraction (1-D) of the switching
period, the maximum efficiency this circuit can obtain is given by:
Vo
η max = ---------------------------------------------------- (Eq 4-3)
V o + ( 1 – D ) ⋅ V diode
For example, consider a conventional buck circuit used to generate an output voltage of
1.5 V from a single lithium ion cell. Even using a low-voltage Shottky diode with a
forward drop of 0.3 V, at the nominal cell voltage of V in = 3.6 V , η max is lower than
90%. With a silicon bipolar diode, V diode = 0.7 V , and η max = 0.79 .
If the diode in Figure 4.3 is replaced by an NMOS device which is gated when
the diode would have conducted (M n in Figure 3.2), the forward drop can be made
arbitrarily small by making the device sufficiently large. In this way, the NMOS device,
used as a synchronous rectifier, can perform the same function as the diode more
efficiently. Assuming all other losses, including the gate-drive for the synchronous
rectifier, are still negligible, the maximum efficiency of the low-voltage buck converter
approaches unity.
4.2.1.1 Synchronous Rectifier Control
Although the synchronous rectifier may reduce conduction loss at low output
voltage levels, it comes at the expense of an additional gate-drive signal and its
+ S1 Lf +
Vin Cin D1 Cf Vo
- -
Fig. 4.3: Conventional buck circuit with pass device, S1, and diode.
associated loss. In addition, as mentioned in Section 3.3.2 and Section 3.4.2, without
proper control of the rectifier, a short-circuit path may exist temporarily between the
input rails during transients. In the rectifier control scheme described in Section 4.2.3,
the dead-times, which ensure that M p and M n never conduct simultaneously, are
adjusted in a negative feedback loop to achieve nearly ideal zero-voltage switched turn-
on transitions of both power MOSFETs.
4.2.2 Zero-Voltage Switching
When the low-voltage buck circuit of Figure 3.2 is hard-switched, it dissipates
2
power in proportion to C x ⋅ V in ⋅ f s as a result of the step charging of parasitic
capacitance C x through a resistive path, M p . In addition, it is likely to exhibit either
substantial short-circuit loss (if no dead-time is provided), or reverse recovery loss (if a
dead-time is provided). In a soft-switched circuit, the filter inductor is used as a current
source to charge and discharge this capacitance in an ideally lossless manner, allowing
additional capacitance to be shunted across C x , slowing the inverter output node
transitions. In this way, appropriate dead-times may be set such that the power
transistors are switched with v ds = 0 , essentially eliminating all associated switching
loss.
+
Mp iLf
vx
Vin Cin
Lf +
Mn Cx Cf Vo
- -
Fig. 4.4: Low-voltage CMOS buck circuit with capacitance Cx.
Ts
vx
DTs Vin
τxLH τxHL t
iLf
∆I/2
Io
∆I/2
t
Mp ON
|Vgsp|
Vgsn
t
Mn ON
Fig. 4.5: Nominal steady-state ZVS waveforms.
Figure 4.4 and Figure 4.5 show the low-voltage buck circuit and associated
periodic steady-state waveforms for ideal zero-voltage switching operation. The soft-
switching behavior is similar to that described in [Maksimovic93] and by other authors.
Assume that at a given time (the origin in Figure 4.5), the rectifier M n is on, shorting
the inverter output node to ground. Since by design, the output is DC and greater than
zero, a constant negative potential is applied across L f , and i Lf is linearly decreasing. If
the value of filter inductance is small enough, the zero-to-peak current ripple exceeds
the full load ∆I > 2I o , and i Lf ripples below zero. As illustrated in Section 4.1.2, for ∆I
slightly larger than 2I o , the physical size of the inductor is close to minimum.
If the rectifier is turned off after the current reverses (and the PMOS device,
M p , remains off), L f acts approximately as a current source, charging the inverter output
node. To achieve a lossless low-to-high transition at the inverter output node, the
PMOS device is turned on when v x = V in . In this scheme, a pass device gate transition
occurs exactly when v dsp = 0 .
With the PMOS device on, the inverter output node is shorted to Vin . Thus, a
constant positive voltage is applied across L f , and i Lf linearly increases, until the high-
to-low transition at v x is initiated by turning M p off. As indicated by Figure 4.5, at this
time, the sign of current i Lf is positive. Again, L f acts as a current source, this time
discharging C x . If the NMOS device is turned on with v x = 0 , a lossless high-to-low
transition of the inverter output node is achieved, and M n is switched at v dsn = 0 .
In this scheme, a form of soft-switching, the filter inductor is used to charge
and discharge all capacitance at the inverter output node (and supply all Miller charge)
in a lossless manner, allowing the addition of a shunt capacitor at v x to slow these
transitions. Since the power transistors are switched at zero drain-source potential, this
technique is known as zero-voltage switching (ZVS), and essentially eliminates
capacitive switching loss. Furthermore, because the inductor current in a ZVS circuit
reverses, if the body diode conducts for a portion of the cycle, it turns off through a
short circuit (rather than through a potential change of Vin ), nearly eliminating the
dissipation associated with reverse recovery, a factor which might otherwise dominate
switching loss, particularly in low-voltage converters.

4.2.3 Adaptive Dead-Time Control
To ensure ideal ZVS of the power transistors, the periods when neither
conducts (the dead-times), τ D , must exactly equal the inverter output node transition
times:
τDLH = τxLH (Eq 4-4)
τDHL = τxHL (Eq 4-5)
In practice, it is difficult to maintain these relationships. As indicated by Figure 4.5, the
inductor current ripple is symmetric about the average load current. As the average load
varies, the DC component of the i Lf waveform is shifted, and the current available for
commutating the inverter output node is modified. Thus, the inverter output node
transition times are load dependent.
In one approach to soft-switching, a value of average load may be assumed,
yielding estimates of the inverter output node transition times. Fixed dead-times are
based on these estimates. In this way, losses are reduced, yet perhaps not to negligible
levels.
In portable applications where battery capacity is at a premium, this approach
to soft-switching may not be adequate. To illustrate the potential hazards of fixed dead-
time operation, Figure 4.6 shows the impact of non-ideal ZVS on conversion efficiency
through reference to a high-to-low transition at the inverter output node. In Figure 4.6a,
the dead-time is too short, causing the NMOS device to turn on with v dsn > 0 , partially
discharging C x through a resistive path and introducing losses. Since shunt capacitance
with a value much larger than the intrinsic parasitics may be added to slow the soft-
switched transitions in a ZVS circuit, this loss may be substantial. In Figure 4.6b, the
dead-time is too long, and the inverter output node continues to fall below zero until the
vx τxHL vx τxHL
Body diode
conduction
Mn discharges Cx
vgn τDHL vgn τDHL
(a) (b)
Fig. 4.6: Non-ideal ZVS and its impact on conversion efficiency.
drain-body junction of M n becomes forward biased. In low-voltage applications, the
forward-bias body diode voltage is a significant fraction of the output voltage; thus,
body diode conduction must be avoided for efficient operation. When the rectifier (M n )
turns on, it removes the excess minority carrier charge from the body diode and charges
the inverter output node back to ground, dissipating additional energy.
To provide effective ZVS over a wide range of loads, an adaptive dead-time
control scheme for a 1 MHz ZVS buck circuit has been outlined in [Stratakos94]. Figure
4.7 shows a block diagram of the approach. A phase detector updates an error signal
based on the relative timing of v x and the gate-drive signals of the power transistors. A
delay generator adjusts the dead-times based on these error signals. Using this
technique, effective ZVS is ensured over a wide range of operating conditions and
process variations. A similar proposal for adaptive control of a synchronous rectifier
was made in [Acker95], and a successful IC implementation of a ZVS buck circuit was
reported in [Lau97].
Figure 4.8 shows a circuit implementation of a τ DHL adaptation scheme
[Stratakos94], which is similar in principle to a delay-locked loop. The phase detector
consists of two SR flip-flops, and controls the complementary switches of a charge
pump. An error voltage proportional to the difference between the high-to-low soft-
switched inverter output node transition time and its corresponding dead-time is
vgn
vx phase delay
detectors generators
error vgp
signals
vgn
vgp
τDLH τDHL
Fig. 4.7: A conceptual illustration of adaptive dead-time control.
generated on integrating capacitor, C I . This error voltage is sampled and held at the
switching frequency of the converter, such that:
v ε ( nT s + T s ) ≈ v ε ( nT s ) + I ⋅ [ τ xHL ( nT s ) – τ DHL ( nT s ) ] (Eq 4-6)
The delay generator, which is implemented by a V/I converter and a
monostable multi-vibrator, updates the dead-time on a cycle-by-cycle basis. For
sufficiently high op-amp gain:
Vin
PHASE DETECTOR Vin

vx R
cross Vin / 2
2I V / I CONVERTER
R
Vgp CHARGE PUMP
S Q -
turn-off icontrol
vε
S/H +
iCI
S Q POWER NMOS
fs DELAY GENERATOR vx
R CI
PWM Vgn
Vgn I Mn
CLK
turn-on C GATE DRIVE
Fig. 4.8: Rectifier turn-on delay adjustment loop.

V in ( nT s ) – v ε ( nT s )
i control ( nT s ) ≈ ------------------------------------------------ (Eq 4-7)
R
and, assuming the dead-time is large compared to a gate delay,
C ⋅ V M+
τ DHL ( nT s ) ≈ ------------------------------------------ (Eq 4-8)
i control ( nT s – T s )
where V M+ is the low-to-high switching threshold of the schmitt trigger.
In periodic steady-state, the error voltage, and thus the gate timing errors, are
forced to zero, nulling propagation delays in the control and drive circuitry. Figure 4.9
shows the periodic steady-state waveforms associated with an ideal ZVS rectifier turn-
on.
vgp
vx Vin / 2
vgn
2I
iCI
0
-I
τxHL / 2
τDHL
Fig. 4.9: Ideal steady-state waveforms for the τDHL adjustment loop.
A similar loop is used to adjust the dead-time between the turn-off of M n and
the turn-on of M p , τ DLH .
4.2.4 Dynamic Power Transistor Sizing
Through use of ZVS with adaptive dead-time control, switching loss is
essentially eliminated. If the filter components in the buck circuit of Figure 4.4 are
ideal, and series resistance and stray inductance in the power train are made negligible,
the fundamental mechanisms of power dissipation will include on-state conduction loss
and gate-drive loss in the power transistors. When sizing a MOSFET for a particular
power application, the principal objective is to minimize the sum of the dissipation due
to these mechanisms. This minimization is performed at the operating point where high
efficiency is most critical: Usually at full load, at high temperature, and in portable
applications, at the nominal battery source voltage.
During their conduction intervals, the power transistors operate exclusively in
–1
the triode region, where r ds = R 0 ⋅ W (the channel resistance is inversely
proportional to gate-width with constant of proportionality R 0 ). Thus, at a given
operating point, the on-state conduction loss in a FET is given by:
2
i ds ( rms ) ⋅ R 0
P q = ----------------------------- (Eq 4-9)
W
Since the device parasitics generally increase linearly with increasing gate-
width, the gate-drive loss can be expressed as a linear function of gate-width W:
P g = E g0 ⋅ f s ⋅ W (Eq 4-10)
where E g0 is the total gate-drive energy consumed in a single off-to-on-to-off gate
transition cycle (see Section 4.2.5 for more detail) and f s is the switching frequency of
the converter. In a ZVS circuit, the filter inductor supplies all of the Miller charge, so
E g0 contains no dissipation due to Miller effect.
Using an algebraic minimization at the most critical operating point, the
optimal gate-width of the power transistor,
2
i ds ( rms ) ⋅ R 0
W opt = ----------------------------- (Eq 4-11)
E g0 ⋅ f s
is found to balance on-state conduction and gate-drive losses, where
2
P q ( opt ) = P g ( opt ) = i ds ( rms ) ⋅ R 0 ⋅ E g0 ⋅ f s (Eq 4-12)
and P total = P q + P g is at its minimum value, P t(min) . Figure 4.10 illustrates normalized
power transistor losses as a function of gate-width.

FET Losses (Normalized to Pt-min)
Pt = Pg + Pq
Pq = i2ds-rmsRo/W
Pg = EgofsW
0
0 1 2
Gate-Width (Normalized to Wopt)
Fig. 4.10: Power transistor losses versus gate-width.

x1 x1 x1
CLK
CLK
CLK
CLK xN
φ0 φ1 φN
DYNAMIC FET SIZING DECODER
enable0 enable1 enableM
A/D CONVERTER
LOAD Vin
Fig. 4.11: Conceptual illustration of dynamic power transistor sizing.
Note that dynamic power transistor sizing may be used to repeat this
optimization at various battery voltages, as terms i ds(rms), R 0 , Q g0, and Vin , are each a
function of battery voltage. Since the battery voltage is slowly varying with time, a
slow, low-precision A/D might be used to quantize the battery voltage every few
milliseconds. (It is also useful to include a digitally-encoded estimate of the load
current.) Figure 4.11 shows a heuristic schematic representation of dynamic transistor
sizing. One implementation of this scheme is described in Chapter 6.
4.2.5 Reduced Swing Gate-Drive
To ensure that the duration of the low-to-high soft-switched transition is kept
reasonably short in a ZVS buck circuit, the inductor current ripple must be made
substantial. This gives rise to large circulating currents in the power train, and
therefore, when the power transistors are sized according to (Eq 4-11), increased gate-
drive losses. Since gate-drive losses increase in direct proportion with f s , this proves to
be the limiting factor to higher-frequency operation of soft-switched converters. To
reduce gate-drive losses, a number of resonant gate-drives have been proposed
[Maksimovic90], [Theron92], [Weinberg92]. While several such techniques have

demonstrated the ability to recover a significant fraction of the gate energy at lower
frequencies, due to the resistance of the polysilicon gate of a power transistor, none are
likely to be as successful in the 1 MHz frequency range. Furthermore, each requires
additional reactive components and may therefore be impractical for portable
applications.
Rather than attempting to recover gate energy in a resonant circuit, another
approach to reducing gate-drive dissipation is to reduce the gate energy consumed per
cycle. By decreasing the gate-source voltage swing between off-state ( V GS = 0 ) and
on-state conduction ( V GS = V g ) , for V g » V t , where V t is the device threshold voltage,
gate energy may be quadratically reduced. This is an attractive alternative in portable
systems where a number of low-voltage supplies are typically available for the gate-
drive. However, because the channel resistance of the device increases with
–1
( V g – Vt ) , gate-swing cannot be arbitrarily reduced, implying the existence of an
optimum V g .
4.2.5.1 Zero-Order Analysis
If the gate capacitance of the power MOSFET is modeled as a linear capacitor
of value C g over the voltage range 0 ≤ V GS ≤ V g , the gate energy dissipation in a single
off-to-on-to-off gate transition cycle is given by:
2
Eg = Cg ⋅ V g (Eq 4-13)
Since the power transistors conduct almost exclusively in the triode region, where:
∂I D W
g ds = -------------- ≈ µC ox ----- ( V g – V t ) (Eq 4-14)
∂V DS L
for V DS « V g – V t , and the device channel resistance is given by:

1
R DS = ------- (Eq 4-15)
g ds
in the triode region, R 0 is inversely proportional to ( V g – V t ) .
In the previous subsection, it was shown that if a power transistor is sized
according to (Eq 4-11), its total dissipation is minimized, and that this minimum
dissipation is related to the square root of the product of the gate energy and the device
channel resistance:
Vg
P t ( min ) ∝ R 0 ⋅ E g0 ∝ ----------------------- (Eq 4-16)
Vg – V t
Minimizing with respect to V g , the optimum gate-swing which minimizes total
dissipation in a power transistor is:
V g = 2V t (Eq 4-17)
Figure 4.12 shows the merits and limitations of a reduced-swing gate-drive.
While the total dissipation of a power transistor may be reduced by lowering V g (for
V g > 2V t ) and appropriately scaling its gate-width, the optimum gate-width which
minimizes dissipation increases rapidly with decreasing Vg .
4.2.5.2 First-Order Analysis
If the inherent non-linearity of the gate capacitance of a MOSFET (shown in
Figure 4.13) is considered in the analysis, the optimum gate-swing is process
technology dependent. For V g < V t , the channel of the device is not enhanced, and the
incremental gate capacitance may, to the first order [Rabaey96], be approximated by the
gate-source and gate-drain overlap capacitances:

Normalized Losses, Gate-Width

Pt-min
Wopt
01 3 5 7
Gate-Swing Vg (Normalized to Vt)
Fig. 4.12: The optimal gate-width and minimum total dissipation for a power MOSFET versus
gate-swing in a ZVS topology.
Gate Capacitance, Cg
triode: WLCox
cut-off:
2WLDCox
0
Vt
On-State Gate-Source Voltage Vg
Fig. 4.13: A first-order gate capacitance model to a power MOSFET in a ZVS application.
dQ g
C g = ---------- ≈ 2WL D C ox, ( Vg < Vt ) (Eq 4-18)
dv gs
where L D is the lateral diffusion in the drain and source areas, and C ox = ε ox ⁄ t ox is the
gate oxide capacitance per unit area. For V g > 2V t , the channel is enhanced, and
because in any practical power circuit, V DS ( on ) « ( V GS – V t ) , the power MOSFET
operates in the triode region, the channel is assumed uniform, and:
dQ g
C g = ---------- ≈ WLC ox, ( Vg ≥ Vt ) (Eq 4-19)
dv gs
Here, L is the drawn channel length, and is equal to the sum of the effective channel
length and the lateral diffusion in both the source and drain diffusion areas (see Figure
4.14):
L = Leff + 2 LD (Eq 4-20)
Note that in a ZVS circuit, the Miller charge is supplied by the filter inductor through
the drain, not through the gate-drive. Thus, the effective gate capacitance does not
include any Miller effect.
Polysilicon Gate
Source Drain
Leff W
n + LD LD n+
Gate-Bulk
L Overlap
(a)
Gate Oxide
tox
n+ Leff n+
(b)
Fig. 4.14: An illustration of the effect of lateral diffusion, LD, on the effective channel length, Leff,
of a power MOSFET: (a) Top view. (b) Cross-section.
The gate-drive dissipation for a single off-to-on-to-off gate transition cycle,
E g , is:
E g = V g ⋅ ∆Q g (Eq 4-21)
where V g is the potential of the gate-drive supply voltage, and ∆Q g is the change in
charge stored on the gate, given by:
t t Vg
C g dv g’
∆Q g = ∫ ig dt’ = ∫ ---------------
dt’
- dt’ = ∫ Cg dv g’
0 0 0
Vt Vg
= ∫ 2WLD Cox dvg’ + ∫ WLCox dvg’

0 Vt
(Eq 4-22)
= 2WL D C ox V t + WLC ox ( V g – V t )
Thus, neglecting dissipation due to the inverter chain, the total gate energy dissipation
per cycle is:
2
E g = WLC ox V g – WL eff C ox V g V t (Eq 4-23)
Substituting (Eq 4-23) into the expression for P t(min) in (Eq 4-12), and
minimizing this total dissipation with respect to V g , the optimum gate-drive voltage is:
2L
V g ( opt ) = V t ⋅  1 + ---------D- (Eq 4-24)
 L 
which is process technology dependent and less than 2V t . For a standard 1.2 µm digital
CMOS process in which L D ≈ 0.15 µm , (Eq 4-24) yields V g ( opt ) = 1.5V t , or about 1.2 V
for an n-channel power MOSFET.

In practice, however, ∆Q g contains a voltage-dependent component due to the
CMOS gate-drive buffering. In the following subsections, it will be shown that as V g is
decreased below 2Vt , this component begins to dominate the overall gate-drive
dissipation, such that
V g ( opt ) ≈ 2V t (Eq 4-25)
While (Eq 4-25) is useful for first-order design centering, iteration with a circuit
simulator is necessary to find a true “optimum” V g .
4.2.5.3 Scaling Vt
To further reduce the total dissipation of a power MOSFET with a given gate
voltage swing, the off-state voltage can be made greater than zero (Figure 4.15a) to
increase the gate overdrive, reducing the device channel resistance. This scheme is
equivalent to that shown in Figure 4.15b, where V GS = 0 in the off-state, and the
device threshold voltage, V t' < V t , is scaled, while all other parameters are held
constant, if:
V t' = V t – V GS ( off ) (Eq 4-26)
(ON)
Overdrive = VGS(off) + ∆Vg - Vt (ON)

∆Vg
Vt Overdrive = ∆Vg - Vt’
VGS(off) > 0 ∆Vg
(OFF)
Vt’
0
(OFF)
(a) (b)
Fig. 4.15: Two equivalent schemes to further reduce total power transistor losses: (a) The gate-
source voltage is not brought to zero. (b) Lower Vt.
Threshold voltage scaling is limited primarily by subthreshold current
conduction in the power MOSFETs, which increases exponentially with decreasing V t ,
and with increasing temperature. For a combination of sufficiently low V t and/or
sufficiently high temperature, subthreshold leakage can result in significant static
power dissipation in the power train of the converter. Figure 4.16 shows the inherent
compromise associated with V t scaling. Here, using the simple zero-order model for
gate energy consumption and the model for subthreshold current conduction presented
in [Liu93], the optimal gate-width and minimum total dissipation of an NMOS power
transistor in a 1.2 µm CMOS technology is plotted versus its threshold voltage, V t , at
room temperature and with all other application- and technology-related parameters
held constant. The gate-swing has been optimized for minimum dissipation ( V g = 2V t ) ,
and subthreshold conduction has been considered in the selection of optimum gate-
width. For V t > 0.4 V , leakage power dissipation (at V in = 6 V ) is negligible compared
to the gate-drive power (at f s = 1 MHz ), and as Wopt increases with 1 ⁄ V t , P t(min)
decreases with V t . As the threshold voltage is dropped below 0.4 V, leakage power
becomes substantial, causing an exponential decrease in Wopt and increase in P t(min)
with decreasing V t . At T = 100 o C, the “optimal” V t is close to 0.5 V.
4.2.5.4 CMOS Gate-Drive Design
In CMOS circuits, a power transistor is conventionally driven by a chain of N
inverters which are scaled with a constant tapering factor, u, such that
N Cg
u = ------ (Eq 4-27)
Ci
1.8
1.2 µm CMOS

T = 25° C
1.2 Pt-min
0.8
Wopt
Increasing leakage power

0.20.2 0.4 0.6 0.8 1.0
Vt
Fig. 4.16: The optimal gate-width and total minimum dissipation, including static power
dissipation due to subthreshold conduction, for a power n-channel MOSFET versus Vt in a 1 MHz
ZVS buck circuit.
Here, C g is the gate capacitance of the power transistor and C i is the input capacitance
of the first buffering stage. This scheme, depicted in Figure 4.17, is designed such that
the ratio of average dynamic current to load capacitance is equal for each inverter in the
chain. Thus, the delay of each stage and the rise/fall time at each node are identical. It
is a well known result that under some simplifying assumptions, the tapering factor u
that produces the minimum propagation delay is the constant e [Mead80]. However, in
power circuits, the chief concern lies not in the propagation delay of the gate-drive
buffers, but in the energy dissipated during a gate transition.
Vg Vg Vg 0 ↔ Vg
τ0 τgs τgs τgs τgs

1 u uN-1
Ci
Cg = u N Ci
Fig. 4.17: CMOS gate-drive.

In a ZVS power circuit, the following timing constraint is desired:
τ x » τ gs ≈ uτ 0 (Eq 4-28)
where τ x is the soft-switched inverter output node transition time, τ gs is the maximum
gate transition time which ensures effective ZVS of the power transistor, τ 0 is the
output transition time (rise/fall time) of a minimal inverter driving an identical gate,
and u is the tapering factor between successive inverters in the chain. In general, it is
desirable to make τ gs as large as possible (yet still a factor of five to ten less than τ x ),
minimizing gate-drive dissipation. Given τ gs and τ 0 , if there exists some u > e such that
the criterion given by (Eq 4-28) is met, the buffering scheme of Figure 4.17 will
provide a more energy efficient CMOS gate-drive than that obtained through
minimization of delay.
Determination of the Inverter Chain
In this analysis, a minimal CMOS inverter has an NMOS device with minimum
dimensions ( W 0 ⁄ L ) and a PMOS device whose gate width is µ n ⁄ µ p ≈ 3 times that of
the NMOS device. It has lumped capacitances C i at its input and C o at its output. Given
that the pull-down device operates exclusively in the triode region during the interval
of interest, and assuming it is a long-channel device, it can be shown [Elmasry91] that
the output fall time of a minimal inverter driving an identical gate from
V out = V g – V tp to V out = V tn is:
Co + C i
τ 0 = ------------------ ⋅ κ (Eq 4-29)
W0
which is linearly proportional to the capacitive load, inversely proportional to the gate-
width of the n-channel device, and directly related to the application and technology
dependent constant:
2L ( 2V g – 3V tn ) ( V g – V tp )
κ ≡ ------------------------------------------ ⋅ log --------------------------------- ⋅ ----------------------------------------------- (Eq 4-30)
µ n C ox ( V g – V tn ) V tn ( V g – 2V tn + V tp )
In [Chandrakasan94b], a similar expression can be found for the output fall time
assuming a heavily velocity-saturated pull-down device.
The factor u which results in an output signal transition time τ gs is found by
solving:
κ ( C o + uC i )
τ gs = ------------------------------ ≈ uτ 0 (Eq 4-31)
W0
yielding a corresponding tapering factor of
τ gs W 0 – κC o
u = -------------------------------- (Eq 4-32)
κC i
between successive buffers. Given u, the number of inverters in the chain is:
log ( C g ⁄ C i )
N = ----------------------------- (Eq 4-33)
log ( u )
The inverter chain guarantees a gate transition time of τ gs with minimum
dissipation, and a propagation delay of
t p ≈ Nut p0 (Eq 4-34)
where t p0 is the propagation delay of a minimal inverter loaded by an identical gate.
Loss Analysis
There are two components of power dissipation in the inverter chain:

2
P dyn = C T ⋅ V g ⋅ f s (Eq 4-35)
P sc = ∑ Isc, i ⋅ Vg (Eq 4-36)

i=1
where I sc, i is the mean short-circuit current in the i th inverter in the chain, and the total
switching capacitance, including the loading gate capacitance of the power MOSFET, is
N
) ⋅ ( C o + C i ) + C g =  --------------- ⋅ ( C o + C i ) + C g
2 N–1 u –1
CT = ( 1 + u + u + … + u (Eq 4-37)
 u–1
Since u N is the constant given by (Eq 4-27), C T and thus, the dynamic dissipation, is
minimized for large u.
Though the dynamic component is readily calculated from (Eq 4-35) and (Eq
4-37), the short-circuit dissipation is more difficult to quantify. From Figure 4.18, it can
be seen that short-circuit current exists in a CMOS inverter while the n- and p-channel
devices conduct simultaneously ( V tn < V in < V g – V tp ) , and that the total energy
consumed during an input transient is proportional to both the input transition time and
Vg - |Vtp|
Inverter input
Vtn
Ipeak
Short-circuit current
τr τf
Fig. 4.18: Short-circuit current in a CMOS inverter.

the peak short-circuit current (which in turn, is related to the output transition time
[Veendrick84]). Figure 4.19 plots simulation results of the ratio of short-circuit to
dynamic dissipation per cycle versus the ratio of 10%-90% input to output transition
times for a minimal inverter operated at V g = 5 V and V g = 3 V , and a ten times
minimal inverter operated at V g = 3 V . These results illustrate three key points
regarding short-circuit dissipation in a CMOS inverter:
• The normalized E sc is seen to increase dramatically with normalized input signal
transition time, but is negligible for equal input and output signal transition
times, and for faster input signal transitions.
• While the magnitude of short-circuit current is dependent on device dimensions
(I peak increases linearly with device size), the ratio of E sc to E dyn appears to be
independent of size.
10
1.2 µm CMOS
1
0.1
Esc / Edyn
Vg = 5V, W/L = min

10-2
Vg = 3V, W/L = min
Vg = 3V, W/L = 10x
10-3
10-4
1 3 5
τin / τout
Fig. 4.19: Simulation results showing normalized short-circuit energy versus normalized 10%-
90% input edge rate for CMOS inverters in a 1.2 µm CMOS technology.
• For V g → V tn + V tp , the normalized E sc decreases with decreasing supply voltage.
While the 10%-90% input edge rate is relatively independent of supply voltage
for short-channel devices, the duration of short-circuit current flow approaches
zero.
Therefore, because the tapering factor u is constant throughout the inverter
chain, providing equal transition times τ gs at each node, the short-circuit dissipation is
made negligible, particularly at low supply voltages. Furthermore, for u > e , less silicon
area will be devoted to the buffering; thus parasitics, and ultimately, dynamic energy
loss, are reduced as compared to the conventional CMOS gate-drive.
To make a first-order estimate of the total energy consumed in a single off-to-
on-to-off gate transition cycle of a minimal power MOSFET, (Eq 4-35) and (Eq 4-37)
are used in conjunction with the values of u and N derived in (Eq 4-32) and (Eq 4-33),
giving:
2 κ ( Co + C i )
E g0 ≈ C g0 ⋅ V g ⋅ ------------------------------------------------- + 1 (Eq 4-38)
τ gs W 0 – κ ( C o + C i )
where C g0 is the gate capacitance of a power transistor with minimum gate-width W 0 ,
linearized over 0 ≤ V GS ≤ V g . To obtain (Eq 4-38), it is assumed that the short-circuit
dissipation in the inverter chain is negligible compared to the dynamic dissipation, that
N
all capacitances scale linearly with gate-width, and that u » 1 . Under these
simplifications, gate-drive losses are expressed as a linear function of gate-width,
identical in form to (Eq 4-10).
Scaling Vg
The practical limit to gate-drive supply voltage scaling is set by increasing
delays in the drive circuitry, which produce reversing returns in the reduction of gate
energy consumption as V g → V tn + V tp and below. Using a linearized first-order model
to a CMOS inverter delay [Rabaey96], it can be shown that for V g » V t , τ 0 increases
with V g -1 for long-channel devices, and is roughly independent of V g for heavily
velocity-saturated short-channel devices. However, as V g → V tn + V tp , these delays
increase rapidly [Chandrakasan92].
This phenomenon is illustrated in Figure 4.20, where the output signal rise and
fall times of a CMOS inverter with W p ⁄ W n ≈ µ n ⁄ µ p in a 1.2 µm technology are plotted
versus the supply voltage, V g . For V g > 3 V , delays are indeed relatively independent of
supply voltage, and the rise and fall times are nearly equal. However, as the supply is
dropped below 2 V, it becomes comparable to V tn + V tp , and inverter output signal
transition times increase rapidly. Furthermore, because V tp > V tn in this technology,
the output rise time increases more quickly than the output fall time. To achieve
balanced rise and fall times at the output of a CMOS inverter with a supply voltage
5
10%-90% Transition Time [ns]
Rise Time
4
3 1.2 µm CMOS
Wn = 2.4 µm
Wp = 7.2 µm
2 Ln = Lp = 0.9 µm
Fall Time
0
1 2 3 4 5
Vg [V]
Fig. 4.20: Simulated output rise and fall times for a minimal CMOS inverter driving an identical
gate as a function of supply voltage, Vg.
comparable to V t , the difference in threshold voltages of n-channel and p-channel
MOSFETs must be considered in the ratioing of the devices.
Figure 4.21 plots the total gate energy consumed per cycle as a function of the
gate-drive supply voltage. Here, power transistor size and τ rise = τ fall = τ gs = 5 ns (a
typical gate transition time for a 1 MHz ZVS power circuit) are held constant. For
V g » V t , there is an approximately quadratic reduction in E g with decreasing supply
voltage. However, because of the increase in inverter output signal transition times, and
the increase in buffer input and output capacitances associated with larger p-channel
device ratioing, as V g → V tn + V tp and below, the tapering factor, u, between
successive inverters in the chain becomes small, and the dynamic energy consumed by
the gate-drive buffering increases dramatically and begins to dominate over that
required by the gate capacitance of the power transistor. Thus, when the dissipation in
the inverter chain is considered in gate-drive supply voltage scaling, at ultra-low
voltages, E g increases as V g decreases.
15
1.2 µm CMOS
Vtn = 0.7 V
|Vtp| = 0.9 V
10
Normalized Eg
increasing u
increasing drive dissipation

2
Vg
5 ∝
Eg
0
1 2 3 4 5
Vg [V]
Fig. 4.21: Gate energy per cycle (including the CMOS drive) versus gate-drive supply voltage
for fixed power transistor size and τgs = 5 ns.
4.2.5.5 Optimum Vg
In most portable systems, it is common to have at least one low-voltage supply
available for the gate-drive. While this low sub-system operating voltage may not be
optimal, it is likely to be useful to reduce the minimum achievable FET losses in the
power train of each DC-DC converter. Thus, it is important to compare the minimum
achievable FET losses and the gate-width required to achieve this minimum loss for
V g = V in and V g equal to this low-voltage sub-system supply.
In Figure 4.22, Wopt and P t(min) are plotted versus V g . Simulation results on a
large area n-channel MOSFET in a 1.2 µm CMOS technology have been interpolated to
find device parameters R 0 and E g0 at each data point. Dissipation in the drive circuitry
is included in E g0 . From this plot, it can be seen that the greatest power savings with
scaling V g are achieved for V g » V t : Since E g0 decreases quadratically, while R 0
increases linearly, if the gate-width of the power device is appropriately scaled
–3 ⁄ 2
( W opt ∝ R 0 ⁄ E g0 ∝ V g ) , as indicated by (Eq 4-16), P t(min) decreases as Vg .
However, since both R 0 and E g0 increase as V g is brought below the sum of the
threshold voltages in the gate-drive buffers, P t(min) increases with any further decrease
in V g . It may be concluded that:
V g ( opt ) ≈ V tn + V tp (Eq 4-39)
Consider a converter in a portable system operating from a lithium ion battery
source. From Figure 4.22, the total losses in each power FET at V g = 1.5 V (the
operating voltage for the baseband circuitry in the current InfoPad terminal) are 20%
lower than at V g = 3.6 V (the nominal battery source voltage). However, the gate-
1.5
Pt-min

1
1.2 µm CMOS
Vtn = 0.7 V
|Vtp| = 0.9 V
0.5
Wopt
Vg ≈ Vtn + |Vtp|
0
1 2 3 4 5
Gate-Swing Vg [V]
Fig. 4.22: The optimal gate-width and minimum total dissipation for a power NMOS versus
gate-swing in a 1.2 µm CMOS technology.
width of each device must be increased by a factor greater than 4.7 to achieve this
reduced dissipation.
4.2.5.6 Reduced Gate-Swing Circuit Implementation
Figure 4.23 and Figure 4.24 show a circuit implementation of a reduced-swing
gate-drive and its associated waveforms in a low-output-voltage ZVS CMOS buck
circuit. The gate of M n is actively driven from 0 to V g by its CMOS gate-drive. The
gate of the p-channel power MOSFET is driven from Vin to approximately V in – V g
with an AC-coupled gate-drive. PMOS device M off , whose gate swings from rail-to-rail,
provides a low-impedance path from the gate of M p to Vin , ensuring that M p remains
fully off during its off-state. In ultra-low-power applications, the AC-coupling
capacitor C c » C gp might be implemented on-chip.

Vin
φoff
Moff Vin
Vg Vg
φp
Mp
Vgp
Cc iLf
Io
Vx
Vg Vg Lf
φn Vgn
Mn Cx Cf RL
Fig. 4.23: A reduced gate-swing CMOS buck circuit implementation with gate supply Vg.
Vg
φP
0
Vin
φoff Mp conducts
0
Vin
 C
c 
Vgp V ⋅  -----------------------
g C + C 
c gp
Vg
φN
0
Vg
Vgn 0 Mn conducts
Dead-times Dead-times
Fig. 4.24: Waveforms for the reduced-swing gate-drive.

2N - 1 reference
ramp
reference
N-bit ramp control
counter N
^ 0
To
converter
N bits To
2N fs oscillator
≥
converter
control N
+
N-bit
+/- (D, fs)
N
counter
Digital
increment /
Filtering
decrement
Vref Vo
From
converter
Fig. 4.25: A micro-power PWM controller.
4.2.6 Ultra-Low-Power PWM Control
Figure 4.25 shows the block diagram of a digital PWM controller
[Stratakos95]. The analog output voltage, Vo , is sampled at the switching frequency, f s ,
and converted to a one-bit digital signal through a slicer with switching threshold Vref .
The output of the slicer is integrated by an N-bit increment/decrement counter. The N-
bit duty cycle control signal consists of this integral term, and a proportional term
which is digitally filtered to provide the compensation necessary to achieve loop
stability.
The N-bit output of a counter, clocked at 2 N times the converter switching
frequency, is used as a reference ramp signal. A glitch-free N-bit digital comparator,

also clocked at 2 N f s , compares the reference ramp and the control signal, generating a
pulse-width modulated clock with variable duty cycle:
control
D = ----------------- (Eq 4-40)
N
2 –1
and constant frequency f s .
The power consumption of the controller is kept low by aggressively scaling
the operating voltage (typically, the lowest voltage available to the system may be
used), and minimizing physical capacitance. While power consumption may be
substantially reduced by decreasing the bit-width, N, the granularity of the control of
the duty cycle:
–N
∆D = 2 ⋅ Ts (Eq 4-41)
is also reduced. This may result in a larger low-frequency output voltage ripple due to
limit cycling behavior.
A similar controller was successfully implemented in [Dancy97a].
4.2.7 PWM-PFM Control for Improved Energy Efficiency
Nearly any load in a portable electronic system can vary by several orders of
magnitude during system run-time. Since these loads spend a majority of time idling in
a low-power state, it is the overall energy efficiency, rather than the peak power
efficiency of the converters supplying these loads, which ultimately determines the
battery run-time.
Figure 4.26 shows the losses versus load of a high-efficiency low-voltage DC-
DC converter under three modes of control: PWM operation (see Section 3.3); PFM
operation (see Section 3.4); and a hybrid PWM-PFM control scheme. In the hybrid
4.3 System-Level Considerations 116
PWM, PFM, and Hybrid PWM−PFM Converter Losses vs. Output Power
0.09
0.08
0.07 PWM
PFM
PWM−PFM
0.06
Pdiss [% of full load]

0.05
0.04
0.03
0.02
0.01
0
−3 −2 −1 0
10 10 10 10
Pout [normalized to full load]
Fig. 4.26: Hybrid PWM-PFM control provides the highest energy-efficiency.
scheme, the converter automatically selects its control mode for peak efficiency as a
function of its output power.
Automatic mode switching can be accomplished by monitoring the peak or
average inductor current, which decrease with decreasing load [MAX887]. In
[Wang97], an adaptive hybrid control scheme is proposed which does not require
current sensing. Perhaps the most straightforward implementation ties the converter’s
operation mode directly to the pulse timing of the load. A feedforward command from
the load signals a transition from idle to full operation and vice-versa.
4.3 System-Level Considerations
By considering the battery source and all DC-DC converters as a unified power
delivery system, a hierarchical design strategy may be employed. In the preceding
subsections, circuit-level optimizations were presented which improve the efficiency

and reduce the physical size and cost of each individual DC-DC converter. This section
introduces several higher-level trade-offs and optimizations that are applicable in
systems where greater than one converter is to be designed.
In the design of a complete power delivery system, the size and efficiency of
different converters within the system may be traded, and the relative merits of
different topologies may be considered in the selection of the battery source voltage.
Furthermore, resources such as oscillators and reference voltages may be shared among
components on the same die, and various sub-system voltages may be utilized in the
design of each individual converter. When such system-level optimizations are
incorporated in the overall design, the resulting power system is likely to be far
superior to one consisting of a number of DC-DC converters designed independently.
4.3.1 Converter Topology Selection
To minimize physical size and complexity, each converter topology may be
chosen to minimize component count. The three basic topologies described in Chapter
3, buck, boost, and buck-boost, each require two switches, two capacitors, and one
inductor − the minimum component count for a PWM DC-DC converter. However, they
are a small subset of the many DC-DC converter topologies that have been proposed
and that are used in practice. Other important classes of converter topologies include
transformer-coupled circuits and soft-switching topologies, such as resonant
converters. Although many of these topologies have important advantages in some
applications, transformer coupling is usually unnecessary in portable systems (see
below), and soft-switching can be achieved without the use of resonant techniques
(Section 4.2.2). Thus the basic topologies are appropriate, perhaps optimal, for most
portable applications. The reader is referred to [Kassakian91], and the references
contained therein, for more discussion of other topologies.

In buck and boost converters, a fraction of the output energy is supplied
directly from the input to the output, reducing the energy storage requirement of the
inductor, and thus, its physical size. In a buck-boost converter, because none of the
energy is transferred directly − it is transferred from the input into the inductor, and
then in a separate portion of the cycle, from the inductor to the output − a larger
inductor is typically needed in this circuit. Thus, the buck and boost topologies are
generally preferred. Because of its more severe inductor requirements, a buck-boost
topology should only be used for voltage polarity inversion, or in applications which
require both up-conversion and down-conversion over the discharge of the battery
source.
Linear regulators and switched-capacitor converters, which have the advantage
that they require no external magnetic components, were introduced in Section 3.6.
There it was shown that their efficiency is fundamentally limited by the conversion
ratio. They should therefore be used judiciously in applications where physical size and
cost are of far greater concern than energy dissipation, or where the conversion ratio
(over the entire battery discharge) is within a range that allows an acceptable energy
efficiency.
4.3.1.1 Transformer-Coupled Topologies
In discrete power conversion circuits, a transformer-coupled topology is often
desirable to accomplish conversion over a wide voltage ratio, because the turns ratio in
the transformer can produce most of the voltage ratio. This allows switching patterns
similar to those in a 1:1 converter (see below), minimizing inductor requirements (and
relaxing the requirements for other components in a discrete implementation).
However, in a highly-integrated converter, the size of the transformer would probably
outweigh any size reductions that would result from decreased inductor requirements.
Thus, transformer-coupled circuits are likely to be useful in portable systems only for
special applications, and will not be discussed further. Special applications that could
indicate the use of a transformer-coupled circuit could include high voltage
requirements (e.g., for a display or backlight) and isolation. The reader is referred to
[Kassakian91], and the references contained therein, for more details on these circuits.
4.3.2 Effects of Conversion Ratio
The effect of conversion ratio on efficiency and component sizing can be an
important factor in selecting the battery source voltage. While predetermined
constraints may dictate the selection of battery voltage and converter output voltage
and thus determine the required conversion ratio, in the design of a complete power
delivery system, there is often a choice of battery source voltage.
In general, a conversion ratio as close to 1:1 as possible minimizes the
inductor size. For example, in (Eq 3-2), it is shown that for a PWM buck converter with
a given output voltage, the required inductor value is proportional to the complement of
the duty cycle, (1-D). Thus, as the conversion ratio approaches 1:1, D approaches one,
and the value and physical size of the inductor approach zero. Similarly, the inductor
requirement in a boost converter approaches zero as the conversion ratio approaches
1:1. In a buck-boost converter, a 1:1 ratio still minimizes the inductor requirement, but
the requirement does not approach zero as the conversion ratio approaches 1:1.
Thus to minimize inductor size, the preferred battery voltage is as close as
possible to the desired output voltage, consistent with the constraint that, with a buck
converter, the end-of-life battery voltage must be above the required output voltage.
(For a boost converter, the constraint would be that the maximum battery voltage must
be below the required output voltage.)
Another important consideration for a CMOS converter implementation which
includes complementary switches is that P-channel devices are inherently inferior to N-
channel devices. On the basis of FET losses alone, it is desirable to choose a conversion
ratio which ensures that current is carried by the NMOS device for a large fraction of
the cycle. For example, consider the CMOS buck topology drawn in Figure 3.2. For a
given output voltage and current, the losses in the power transistors are minimized if
the NMOS device carries the inductor current for the majority of the cycle. This calls
for a large conversion ratio, as far from 1:1 as possible. With a 5:1 conversion ratio, for
example, the PMOS device will conduct for only 20% of the cycle, and its losses can be
made small.
Thus, for conversion ratios near 1:1, it may be desirable to reconfigure the
buck topology as shown in Figure 4.27. In this circuit, the NMOS device functions as
the pass device, and, for conversion ratios near 1:1, it will have the longer conduction
interval. Similar reconfigurations of the boost and buck-boost topologies are possible to
minimize losses at extreme duty cycles. Figure 4.28 plots filter inductance and FET
losses versus conversion ratio for a buck circuit with fixed output voltage.
In a system requiring many unique voltages for different sub-systems, the
battery voltage should be selected as close as possible to the voltage at which the most
power is required, minimizing the size and maximizing the efficiency of the converter
supplying that voltage. The remaining converter topologies would then be chosen to
accommodate that battery voltage.
+ + +
Mp vx iLf Cf Vo
- -
Vin Cin
Lf Output
Mn Filter
-
Chopped Signal
Fig. 4.27: Alternative buck circuit topology for D > 0.5.

Buck Circuit: Fixed Vo, D = Vo / Vin
Normalized Losses, Size

NMOS conducts NMOS conducts
1 for (1-D) for D
L ∝ (1-D)
0
0 0.2 0.4 0.6 0.8 1
Conversion Ratio D
Fig. 4.28: Value of L and FET losses vs. conversion ratio for fixed Vo.
4.3.3 Highest Integration
Linear regulators have the advantage that they are physically small and simple
three-terminal components that can be integrated in a vanilla CMOS process. As a
result, one or more linear regulators are often integrated together (sometimes with their
individual loads) on a single IC [Shin94]. In fact, an entire power distribution system
for a cellular phone, which consists of five separate linear regulator outputs, is
commercially available in a single IC package [TDA3601Q]. The incremental size and
cost of adding additional regulators to an existing IC is small compared to the
introduction of a new IC to the system.
In recent years, PWM DC-DC converters integrated in standard foundry-
available digital CMOS processes have been demonstrated [Stratakos94], [Lau97],
[Dancy97a], [Wang97]. Integration of several of these converters on a single IC is
possible, and would provide size and cost advantages similar to those enjoyed by
multiple-output linear regulator ICs.

4.3.4 Exploiting Subsystem Voltages
Existing sub-system voltages can be used in the design of each individual
converter. In Section 4.2.5, it was shown that as the power transistor gate-drive supply
voltage, V g , is reduced for V g « V t , total power transistor losses, if optimized, decrease
roughly as V g . There, it was also shown that a gate-drive voltage near 1.5 V is nearly
optimal in terms of total power transistor losses. (This is an encouraging result as many
modern-day digital ICs are trending toward such a voltage supply.) Thus, a low sub-
system voltage may be utilized as the gate-drive supply for each DC-DC converter in
the power system to reduce losses in each power train.
A similar strategy may be used to minimize the power consumption of the
control circuitry. Although analog components − such as a bandgap reference,
amplifiers, and comparators − are often required to implement the PWM and/or PFM
control functions, power dissipation due to digital logic and control is becoming
increasingly important to the overall control power budget. It is these circuits which
can benefit most from supply voltage scaling (see Chapter 2).
In Chapter 6, the design of a power delivery subsystem for an energy-efficient
microprocessor is reviewed. Here, separate sub-system voltages are used within each
converter. The lithium ion battery powers the analog blocks directly; a low-voltage
digital supply is used to reduce the dissipation of the digital control circuits; and a sub-
volt supply provides power for a high-speed low-swing I/O bus on the converter.
4.3.5 Shared Resources
In general, as the size of a DC-DC converter is decreased through frequency
scaling (see Section 4.1.1), its losses increase. In a complete power delivery system
consisting of a number of DC-DC converters, frequency scaling may be used such that
the size and efficiency of different converters are traded, yielding the desired
combination of overall size and losses. For example, the power supply with the highest-
power requirement may be optimized for high efficiency and reasonable size (with an
operating frequency in the hundreds of kHz), and all supplies with lower-power
requirements may be optimized for small size and reasonable efficiency (with operating
frequencies of 1 MHz and above). The lowest-power converters might be implemented
with linear regulators or switched-capacitor converters.
Furthermore, resources may be shared among different converters, particularly
among converters which are integrated on the same die. Oscillators, reference voltages,
and master bias generators are needed in the control loop of any PWM or PFM DC-DC
converter. These components are likely to substantially degrade light-load efficiency,
particularly for a lower-power converter. If these components are shared among several
converters, the overall quiescent operating power and component count of the power
system will be reduced. In the design example of Chapter 6, successful resource sharing
is demonstrated between converters integrated on separate ICs.

5.1 Dynamic Converter Definitions 124
Chapter 5
Design Considerations for

Dynamic DC-DC
Converters
The concept of dynamic voltage scaling was introduced in Chapter 2 as a
means of trading processor performance for energy dissipation at run-time. In this
chapter, design considerations for the key DVS enabler, called the dynamic DC-DC
converter, are discussed.
Section 5.1 introduces the principle of operation and key performance metrics
for a dynamic DC-DC converter. An example DVS system is shown in Section 5.2 and
followed throughout the chapter. In Section 5.3, the performance metrics are detailed.
Section 5.4 and Section 5.5 illustrate their impact on dynamic DC-DC converter and
overall DVS system design. Section 5.6 summarizes previous work on dynamic DC-DC
converters and compares them on the basis of these performance metrics.
5.1 Dynamic Converter Definitions
Figure 5.1 shows a conventional “static” low-voltage DC-DC converter as a
low-power enabler. The desired operating point on the load’s energy-versus-
performance curve is selected at design time by choosing a fixed converter output

L fixed Vo
+ DC-DC +
Vbat feedback C Load Vo
Normalized load energy dissipation - -
1.0
3.3V
Choose one operating point at

design time with fixed Vo
0.5
1.05V
0
0 0.5 1.0
Normalized load performance
Fig. 5.1: Voltage scaling for low-power.
voltage, Vo . Particularly in fixed throughput applications, the lowest power converter-
load combination is achieved using the voltage scaling approaches of Chapter 2
together with the high-efficiency low-voltage DC-DC converter design techniques of
Chapter 4. The load and static DC-DC converter do not communicate. The converter
maintains regulation of Vo by comparing it to a known voltage reference and controlling
the output via a pulse-width or pulse-frequency modulation scheme.
A dynamic voltage scaling (DVS) system is shown in Figure 5.2. Here, the
performance and energy dissipation of the load are traded dynamically by varying the
Request
L variable Vo
Dynamic
+ DC-DC +
Vbat C Load Vo
- -
Normalized load energy dissipation
1.0
3.3V
Dynamically choose operating point at

run time with variable Vo
0.5
gV
o
in
as
cre
de
1.05V
0
0 0.5 1.0
Normalized load performance
Fig. 5.2: Dynamic voltage scaling for energy-efficient variable throughput processing.
converter output voltage at run-time. The dynamic DC-DC converter and its load must
communicate to set proper voltage levels as a function of time.
The dynamic DC-DC converter has several requirements which differ from
those of the static DC-DC converter. While both converters must maintain a
substantially DC output voltage with high efficiency during regulation, the dynamic
DC-DC converter must do so over a much wider range of voltages and currents. In
addition, the dynamic converter must slew its output voltage during transitions at rates
approaching volts per microsecond, and must transfer large quantities of energy from
input to output and vice-versa with high energy efficiency.

instant and lossless

transitions
Vo or performance
regulates to ideal
DC output voltage
with 100% efficiency
majority of time in
lowest energy state
time
Fig. 5.3: Ideal DVS transient waveform.
Figure 5.3 illustrates an ideal DVS transient waveform. In this figure,
converter output voltage or load performance is plotted versus time. The DVS system
spends the majority of its time at the lowest voltage where it enjoys its largest energy
savings. Each voltage adaptation requested by the load is instant and lossless, providing
performance on demand without penalty. Between voltage adaptations, the converter
maintains a precisely regulated DC output voltage, independent of variations in
environmental conditions, load current, and battery discharge, and does so with 100%
power efficiency.
Figure 5.4 shows a practical DVS transient waveform. Voltage adaptations are
no longer instant; instead, there is a non-zero tracking time. Tracking energy is
dissipated by the converter during transitions. Between transitions, absolute DC output
voltages are no longer maintained. The output voltage ripple causes extra load energy
dissipation. The converter itself dissipates regulation energy, and is likely to be least
efficient at the lowest output voltage and power levels − where efficiency matters most.
5.2 DVS System Example 128
non-zero
Tracking Time and Tracking Energy
Vo or performance
non-zero Voltage Ripple
causes load dissipation
non-zero Regulation Energy

(worst efficiency at lowest voltage)
time
Fig. 5.4: Non-ideal DVS transient waveform.
5.2 DVS System Example
Figure 5.5 shows a voltage and frequency tracking loop for use in a dynamic
voltage scaling system. The desired processor throughput is commanded by the process
scheduler, which requests an integer multiple, 5 ≤ M ≤ 127 , of the 1 MHz reference
frequency, f REF. The dynamic voltage converter consists of a frequency detector, a loop
filter, and the buck DC-DC converter described throughout this thesis and shown in
Figure 3.2. The frequency detector generates a digital error signal in proportion to the
frequency error, M ⋅ f REF – f VCO . This error is translated into an update signal for the
DC-DC converter through the loop filter. The DC-DC converter provides the voltage
supply, V dd , to the processor, regulating against changes in battery voltage and load
current, I dd . The voltage-controlled oscillator (VCO) is integrated together with the
processor, and designed to match its critical path. The loop forces the output frequency
of the VCO, f VCO , to equal the commanded frequency M ⋅ f REF , at an input voltage V dd .
5.2 DVS System Example 129
Battery
DVS converter
Frequency
Detector L Vo fVCO
+ Loop Buck
Σ Filter Converter
VCO
1.05 V to > 3.3 V
− C
M*fREF = 5 MHz to 127 MHz

Idd
Vdd
Requested fVCO from process scheduler
µP <
Fig. 5.5: A voltage and frequency tracking loop.
The processor is therefore run at the minimum voltage supply, V dd , at which the
throughput request can be met, resulting in the lowest achievable energy per operation
while sustaining f VCO .
The DVS system of Figure 5.5 has been prototyped and is further described in
Chapter 6. Some key system parameters, summarized in Table 5.1, are used for
illustration throughout this chapter.
Table 5.1: Example DVS system parameters.

DC-DC output inductor L = 3.5 µH
DC-DC output capacitor C = 5 µF
processor throughputa 100 MIPS at 3.3 V
5 MIPS at 1.05 V
processor energy per instructiona 4.5 nJ/inst at 3.3 V (450 mW)
0.4 nJ/inst at 1.05 V (2 mW)
a. Processor design detailed in [Burd98]. Energy and delay per operation

scale as in Figure 2.1.
5.3 Dynamic DC-DC Converter Performance Objectives 130
5.3 Dynamic DC-DC Converter Performance Objectives
There are two primary objectives of the dynamic DC-DC converter whose
relative importance are determined solely by the DVS application:
• Minimize energy consumption of the entire DVS system for a given set of
processor throughput commands
• Slew the output voltage upwards as rapidly as possible to allow performance on
demand
Translated to the quantifiable performance metrics of Section 5.1, a high-
performance dynamic DC-DC converter must minimize low-voltage regulation energy
and the energy penalty associated with output voltage ripple, minimize tracking energy,
and minimize tracking time. In the following subsections each of these performance
metrics are detailed, and their impact on the buck converter design and the DVS system
as a whole are discussed. It is shown that optimization of the converter is heavily
application dependent. Detail on the prototype implementation of a dynamic DC-DC
converter and its measured performance are given in Chapter 6.
5.3.1 Tracking Energy
To effect the large and rapid DVS transitions of its output voltage, the dynamic
DC-DC converter must efficiently transfer large quantities of energy from input to
output and vice-versa (Figure 5.6). The energy dissipated during these tracking
transitions is called the tracking energy of the DVS system.
If the DVS voltage excursions are made through a resistive element alone,
tracking energy dissipation is large. Consider a linear regulator tracking an output

E bat = ∆E C + Etrack
v o2
Vbat Dynamic Vo
v o1
Converter
C Load
bypass
1 2 2
∆EC = --- ⋅ C ⋅ ( v o2 – v o1 )
2
Fig. 5.6: Input to output energy flow in a DVS tracking transition.
excursion from v o1 to v o2 from a battery at potential V bat (Figure 5.7). The change in
energy on bypass capacitor, C, is:
1 2 2
∆E C = --- ⋅ C ⋅ ( v o2 – v o1 ) (Eq 5-1)
2
The charge transferred to C through the linear regulator is given by:
∆Q C = C ⋅ ( v o2 – v o1 ) (Eq 5-2)
All of the charge delivered to the bypass capacitor is supplied by the battery. The
energy drawn from the battery is equal to the product of the delivered charge and the
potential from which it is delivered:
Linear regulator
Vbat Vo
C Load 1.05 V to 3.3 V

bypass
Fig. 5.7: A linear regulator based voltage tracking system.

∆E bat = V bat ⋅ ∆Q C = C ⋅ V bat ⋅ ( v o2 – v o1 ) (Eq 5-3)
The difference in energy consumed versus energy transferred is dissipated in the
resistive element of the linear regulator:
1
E track = ∆E bat – ∆E C = --- ⋅ C ⋅ ( v o2 ⋅ ( 2V bat – v o2 ) – v o1 ⋅ ( 2V bat – v o1 ) ) (Eq 5-4)
2
With V bat = 3.6 V, v o1 = 1.05 V, and v o2 = 3.3 V, E track = 3.21 µJ per 1 µF of bypass
capacitance. For the DVS system parameters of Table 5.1, this is equal to the energy
dissipation of 8025 instructions at 5 MIPS, or 1.6 ms of operation.
If the voltage excursions are instead made through an ideal DC-DC converter,
they are ideally lossless. This is because the large input to output voltage ratio is
applied across a series inductor, rather than a resistor. Figure 5.8 shows equivalent
circuits and several cycles of i L (t) and v o (t) waveforms for a tracking voltage transition
made in discontinuous conduction mode. The output inductor is periodically biased to
(V bat -Vo ) and -Vo , storing and releasing energy from the battery to the output capacitor.
In practice, the loss mechanisms described in Chapter 3 limit the efficiency of
the tracking transition. In the integrated DC-DC converters described in Chapter 4, gate
and switching losses, resistive losses, and control power can usually be kept to below
10% of the energy handled by the converter. Using this conservatively high relative
dissipation together with (Eq 5-1), a simple first-order estimate to the tracking energy
of a DC-DC converter may be found. For example, with v o1 = 1.05 V and v o2 = 3.3 V,
E track = 0.49 µJ per 1 µF of bypass capacitance − only 15% of the energy required by
the linear regulator. This is equivalent to the energy consumed by 1225 instructions at 5
MIPS, or 245 µs of run-time.

iL iL
+ L + L +
Vbat C vo C vo
− − −
iL increasing: L stores energy from Vbat iL decreasing: L releases energy to C
iL(t)
vo(t)
Fig. 5.8: A DVS tracking transition through a discontinuous mode DC-DC converter.
The preceding result is useful to determine when it is energy efficient to
transition into a low-power mode. For every 1 µF of output bypass, 0.49 µJ is dissipated
during the high-voltage to low-voltage transition, and another 0.49 µJ is dissipated
during the low-voltage to high-voltage transition. This high-to-low-to-high transition is
only worthwhile if the energy saved by computing at low-voltage is greater than the
energy dissipated during the transition. For every 1 µF of output bypass:
0.98 µJ
---------------------------------------------------------- = 239 instructions at 5 MIPS (Eq 5-5)
4.5 nJ/inst. – 0.4 nJ/inst.
is the break-even point. For fewer than 239 low-voltage instructions, it is more energy-
efficient to compute at the higher voltage. This is equal to 48 µs of run-time at 5 MIPS.
Since tracking energy dissipation increases with increased energy handling,
according to (Eq 5-1) the value of output bypass capacitor, C, should be minimized.
5.3.2 Tracking Time
The tracking time of the dynamic DC-DC converter determines the latency
between operation in a lower-energy computation mode and operation in the peak
throughput mode. A fast transition from the most energy-efficient mode (the lowest
output voltage) to the highest throughput mode (the highest output voltage) is critical to
the successful implementation of a DVS system for general purpose processing
applications.
Tracking time is limited by the LC output filter of the DC-DC converter.
Figure 5.9 shows the fastest possible transition of the converter output voltage. A large-
signal step-response of state variables i L and v o to a full 3.6 V step at the inverter
output node, v x , is plotted for L = 3.5 µH, C = 5 µF, and R = 0.12 Ω. The time constant
of the LC ring is:
Series LCR step respsone. L = 3.5 uH, C = 5 uF, R = 0.12 Ohms, Vin = 3.6 V
3
1
iL [A]
−1
−2
−3
0 0.2 0.4 0.6 0.8 1 1.2
−4
x 10
4
vo [V]
1
0 0.2 0.4 0.6 0.8 1 1.2
time [sec] −4
x 10
Fig. 5.9: Series LCR step response.

τ LC = L⋅C (Eq 5-6)
Thus, to minimize tracking time, small-valued output filter elements are desired.
Large peak inductor currents are characteristic of rapid open-loop voltage
tracking transitions. For an adaptation in v o from v o1 to v o2 , a zero-to-peak inductor
current of:
v o2 – v o1
ˆi = ----------------------
Lf (Eq 5-7)
L⁄C
is required. Current-limited pulse-width or pulse-frequency modulation control of the
dynamic DC-DC converter is usually necessary to avoid damage to the converter IC and
filter elements during tracking transitions. When the inductor current is limited to some
I max , the maximum slew rate during output voltage transitions is:
dV I max
---------o- = ----------
- (Eq 5-8)
dt C
Even in current-limited transitions, a small output filter capacitor is desired to rapidly
adapt the DVS supply voltage.
5.3.3 Regulation Energy
Between tracking transitions, the dynamic DC-DC converter must maintain a
well-regulated DC output, independent of variations in load, battery voltage, and
environmental conditions. During this regulation mode, the dynamic converter behaves
similarly to the more conventional static DC-DC converter, and can operate with
conventional pulse-width or pulse-frequency modulation control.
Figure 5.10 shows the general trend of decreasing DC-DC converter efficiency
at lower output voltage and power levels − exactly where the converter must be
Decreasing Efficiency at Lower Vout and Pout, Pout∝ Vout3

25
pwm
pfm
20
Normalized losses relative to Pout

15
10
0
1 1.5 2 2.5 3 3.5
Vo [Volts]
Fig. 5.10: Decreasing DVS converter efficiency at lower voltage.
efficient to most effectively conserve energy in a DVS system. Here, P out scales with
Vo 3 , similarly to a DVS system, V bat = 3.6 V, output inductor and capacitor values (L =
3.5 µH, C = 5 µF) are chosen from the example DVS system of Section 5.2, and power
transistor sizes are optimized for the 3.3 V, 450 mW operating point. Quiescent control
currents of 500 µA in PWM mode and 100 µA in PFM mode are assumed. Total power
FET dissipation, conduction loss in the external filter elements, and static control
power are considered for a continuous conduction mode PWM converter and a constant
peak current controlled PFM converter. From this plot, it is clear that some type of PFM
or hybrid PWM-PFM control scheme is necessary to maintain higher efficiencies at the
lower-voltage, lower-current operating points. (This was also the conclusion of Section
4.2.7.)
Figure 5.11 and Figure 5.12 show the contribution of three key mechanisms of
loss relative to P out in PFM and PWM operation. Three important sets of observations
can be made from these plots:

Mechanisms of Loss, PFM Mode (Vbat = 3.6 V)

2.5
Quiescent control
Power FET
Inductor Conduction
2
Normalized losses as percentage of Pout

Data set 1: Vo = 1.05 V
1.5
0.5
0
1 2
Fig. 5.11: Mechanisms of loss, PFM mode.
Mechanisms of Loss, PWM Mode (Vbat = 3.6 V)

12
Quiescent control
Power FET
Inductor Conduction
10
Normalized losses as percentage of Pout

8
0
1 2
Fig. 5.12: Mechanisms of loss, PWM mode.

• In both PWM and PFM modes, total power FET dissipation increases substantially
relative to load power with decreasing output voltage. Dynamic transistor sizing
as a function of Vout (described in Section 4.2.4) will help to mitigate this effect.
• In both PWM and PFM modes, the relative contribution of static dissipation from
control circuits becomes increasingly significant at lower output voltage. This
trend is more noticeable under PWM operation since the control circuits are
generally more complex and power hungry than their PFM counterparts. A PFM
controller, whose power dissipation scales with the load, will generally
contribute the smallest dissipation with decreasing Vout . In [Wei96], a digital
controller, bootstrapped from the converter output, is successfully demonstrated
to scale the power dissipation of the controller together with the load.
• In PWM mode, conduction loss through the series resistance of the output filter
inductor also increases with decreasing output voltage, as expected. In PFM
mode, conduction and switching losses usually scale relative to the output power
3
because the PFM repetition period scales with load. However, since P out ∝ V o ,
and Vo changes over a three-to-one range, simple PFM-only operation is
insufficient to guarantee somewhat constant efficiency over the dynamic range
of the converter. Instead, some form of hybrid PWM-PFM scheme is necessary.
5.3.4 Output Voltage Ripple
In Chapter 3, it was shown that the output of any DC-DC converter includes a
symmetric AC ripple voltage superimposed on the desired DC. The magnitude of this
ripple was given in (Eq 3-3) for PWM operation and in (Eq 3-26) for PFM operation
with constant on-time control. These expressions are rewritten below:
V o ⋅ ( 1 – V o ⁄ V bat )
∆V PWM = ----------------------------------------------- (Eq 5-9)
P→P 2
8 ⋅ L ⋅ C ⋅ fs
2
1 T pmos ⋅ ( V bat – V o ) ⋅ V bat
∆V PFM = --- ⋅ ---------------------------------------------------------------- (Eq 5-10)
P→P 2 Vo ⋅ L ⋅ C
Regardless of the output voltage or operating mode of the DC-DC converter,
ripple scales inversely with the square of the LC time constant. (Eq 5-9) and (Eq 5-10)
also indicate that normalized output voltage ripple, ∆V / Vo , increases for decreasing
Vo . Figure 5.13 shows the trend. Here, inductor and capacitor values are fixed, V bat =
3.6 V, and normalized output voltage ripple is plotted versus DC output voltage, Vo .
Output voltage ripple causes increased energy dissipation in the loading
general purpose processor of the DVS system, particularly at low voltage. A simple
first-order model is used here to estimate the impact. In Figure 5.14, the peak-to-peak
output voltage ripple, ∆V, is symmetric about the desired DC output voltage, V nom . The
required processor throughput, f nom , is maintained by dithering between high and low
frequency values such that:
Output Voltage Ripple Versus Vo, Vin = 3.6 V

8
pfm
pwm
7
6
Normalized output voltage ripple
0
1 1.5 2 2.5 3 3.5
Vo [Volts]
Fig. 5.13: ∆V / Vo (in percent) versus Vo.

duty cycle, d
fhi
Throughput fnom
dithers such that fave = fnom
flo
Output Voltage ∆V/2 Vnom

∆V/2
Fig. 5.14: First-order frequency and voltage model used to compute voltage ripple energy.
d ⋅ f hi + ( 1 – d ) ⋅ f lo = f nom (Eq 5-11)
This frequency waveform is generated by a dithering output voltage from
V nom +∆V/2 to V nom -∆V/2. The resulting average system throughput is f nom . The
resulting average energy per operation is:
E ave = d ⋅ E V ⁄2+ ( 1 – d ) ⋅ EV ⁄2 (Eq 5-12)

nom +∆V nom -∆V
Figure 5.15 plots the normalized load energy dissipation, E ave ⁄ E V , for
nom
various normalized output voltage ripple, ∆V ⁄ ( 2V nom ) . This data assumes that energy
and delay scale with voltage as shown in Figure 2.1. From this plot, a zero-to-peak
output voltage ripple as high as 5% might be considered tolerable, even at low nominal
voltages. Higher normalized output voltage ripple may be acceptable above 1.5 V. For
greatest efficiency, however, ripple should be minimized, particularly at lowest voltage.
According to (Eq 5-9) and (Eq 5-10), this indicates the use of large values of L and C,
optimized for operation at the lowest output voltage.

5.4 Impact of Performance Metrics on Power Circuit Design 141
1.45
1.40
1.35
Normalized energy
1.30
1.25
1.20 20% zero-peak Vo ripple
1.15
1.10
10% zero-peak Vo ripple
1.05 5% zero-peak Vo ripple
1.00
1.0 1.5 2.0 2.5 3.0 3.5 4.0
Vo(nom) [V]
Fig. 5.15: The impact of output voltage ripple on load energy dissipation.
5.4 Impact of Performance Metrics on Power Circuit Design
There are two sets of performance metrics that trade-off in a dynamic DC-DC
converter through the values of output filter inductor and capacitor. With larger values
of L and C, the converter is a better regulator, with improved conversion efficiency and
reduced output voltage ripple. With smaller values of L and C, the converter is a better
tracking system, with decreased tracking energy and tracking time.
The relative importance of these metrics is determined solely by the
application. As the application demands performance adaptations with greater
frequency, tracking metrics become increasingly important. If the application requires
true performance on demand, optimization of tracking time might be the principal
objective. If most operations are performed at a low throughput and low energy corner,
tracking transitions are rarely made, and latency can be tolerated, large values of L and
5.5 Impact of Performance Metrics on System Performance 142
C should be selected to minimize output voltage ripple and low-voltage, light-load
converter losses.
The need for high conversion efficiency over a wide range of output voltage
3
and power levels, with P out ∝ V o , presents a difficult design challenge. A hybrid PWM-
PFM control scheme is most likely to maintain low-voltage efficiency by ensuring that
the converter switches only when necessary. Dynamic transistor sizing is necessary to
minimize power FET losses over the output range of the converter. The voltage scaling
approaches of Chapter 2, together with other well-known low-power circuit design
techniques (see Chapter 6), must be judiciously used to scale the quiescent control
losses together with the load power.
5.5 Impact of Performance Metrics on System Performance
The preceding subsections have summarized the nonidealities of a dynamic
DC-DC converter. Here, the impact of these nonidealities on DVS energy savings is
quantified.
Assuming a 95% DC-DC converter efficiency at 3.3 V and 450 mW, the
converter-load combination of Figure 5.5 dissipates 4.7 nJ per instruction at the 100
MIPS at 3.3 V operating point 1 . With 5 µF of output bypass capacitance and 10%
tracking energy dissipation, the dynamic converter dissipates a total of 4.9 µJ for one
complete 3.3 V to 1.05 V to 3.3 V tracking cycle. At the low energy operating point − 5
MIPS at 1.05 V − the processor dissipates 0.4 nJ per instruction. For a DC-DC
converter with a 5% zero-to-peak output voltage ripple at 1.05 V, Figure 5.15 indicates
a 4% energy dissipation penalty in the load. With an 85% conversion efficiency at 1.05
V and 2 mW, the total dissipation of the converter-load combination is:
1. Extra load energy dissipation due to output voltage ripple is negligible at 3.3 V.
5.5 Impact of Performance Metrics on System Performance 143
0.4 nJ ⋅ ( 1 + 0.04 )
E diss = ------------------------------------------- = 0.5 nJ/instr (Eq 5-13)
0.85
at the lowest energy operating point.
Figure 5.16 plots the normalized energy dissipation (E DVS /E 3.3V ) as a function
of the number of instructions computed at 1.05 V. The “break-even” point, N 1.05V,
where a DVS transition is energy efficient is:
4.9 µJ
N 1.05V = ----------------------------------------------------------- = 1167 instructions (Eq 5-14)
4.7 nJ/instr – 0.5 nJ/instr
A nearly 70% energy savings is observed for 5000 low-voltage instructions, or 1 ms of
run-time at 5 MIPS.
DVS Energy Savings

1.3
1.2
1.1
0.9
EDVS / E3.3V
0.8
0.7
0.6
0.5
0.4
0.3
1000 1500 2000 2500 3000 3500 4000 4500 5000
Number of instructions
Fig. 5.16: DVS energy savings, including converter nonidealities.

5.6 Summary of Previous Work 144
5.6 Summary of Previous Work
Dynamic voltage scaling has been proposed to minimize the energy
consumption of variable workload processors in a number of recent publications
[Nielsen94], [Wei96], [Chandrakasan96], [Gutnik96a], [Namgoong97], [Kuroda98].
Each of the approaches is similar to the block diagram of Figure 5.5, in that the critical
path of the processing element is replicated by a delay element or ring oscillator, and
the processor performance is regulated similarly to a delay- or phase-locked loop.
[Wei96], [Namgoong97], and [Kuroda98] all propose DC-DC converter
designs for use in dynamic voltage scaling systems. Each identifies conversion
efficiency over a wide range of output voltage and power levels to be of primary
concern. As a result, digital CMOS controllers, bootstrapped from the converter’s
output, are implemented in an effort to scale the quiescent dissipation of the converter
with decreasing output voltage. Table 5.2 benchmarks the three designs.
Table 5.2: Summary of previous dynamic DC-DC converters.
[Wei96] [Namgoong97] [Kuroda98]
L 50 µHa 7 µH 8 µH
C 50 µFa 33 µF 32 µF
Vout range 2.0 V to 4.5 V 1.5 V to 3.5 V 0.8 V to 2.9 V
Pout range 375 mW to 850 mW 10 mW to 200 mW 10 mW to 300 mW
Efficiency 82% to 92% 83% to 93% 40% to 81%
Max ∆Vout < 1% < 2% < 2%
0-90% tracking time ~3 msb ~1 msb ~90 µsb
Tracking energyc 25 µJc,d 17 µJc,d 32 µJc,d
a. Estimated from published bode plot.

b. Estimated from published measured waveforms.
c. For benchmarking, estimated for a 1.05 V to 3.3 V to 1.05 V tracking transition, even if
the published dynamic range of the converter is exceeded.
d. Estimated from published efficiencies.
[Kuroda98] uses a continuous conduction mode PWM control scheme for the
DC-DC converter. As a result of the constant frequency continuous mode operation,
conversion efficiency drops to 40% at the lowest voltage and power levels (10 mW at
0.8 V). L = 8 µH and C = 32 µF appear to be chosen for low output voltage ripple,
quoted at less than 0.1% at a constant load current. A first-order tracking response is
observed with a time constant on the order of 40 µs, which is set by an integral term in
the controller. Tracking energy is not documented, but can be estimated to exceed 32 µJ
for a 1.05 V to 3.3 V to 1.05 V output excursion 2 .
[Wei96] uses a hybrid PWM-PFM control scheme and is able to maintain
efficiencies between 82% and 92% over a 2.0 V to 4.5 V output voltage range when
driving a constant resistive load of 25 Ω. Inductor and capacitor values are not
provided, but a published bode plot shows an LC corner frequency below 3 kHz. For
benchmarking purposes, values of L = 50 µH and C = 50 µF are assumed. With such
large values of output filter elements, low output voltage ripple is guaranteed. Tracking
energy is estimated to exceed 25 µJ for a 1.05 V to 3.3 V to 1.05 V output excursion 3 .
Measured results show an underdamped third-order tracking response, whose settling
time is dominated by a pair of pole-zero doublets from the LC output filter and PID
controller. The 0-90% settling time appears to be on the order of 3 ms.
The most successful implementation is described by [Namgoong97]. This
converter is always operated in discontinuous conduction mode, allowing for a smaller
value of inductance (L = 7 µH). The converter output is regulated using a constant on-
time PFM control scheme, and therefore requires a fairly large output capacitor (C = 33
µF) to guarantee low ripple at the lowest output voltages. High conversion efficiency is
maintained over a wide range of output voltage and power levels: The maximum
efficiency is 93% at the 3.5 V, 200 mW operating point; the minimum efficiency is 83%
2. Assumes 20% energy loss in the converter; loosely estimated from published efficiencies.
at the 1.5 V, 10 mW operating point. Tracking energy is estimated at 17 µJ for a 1.05 V
to 3.3 V to 1.05 V output excursion 4 . Tracking time is listed at better than 6 ms/V, but
published waveforms indicate 0 to 90% settling in 1 ms, and a slightly underdamped
second-order response.
The prototype dynamic DC-DC converter presented in Chapter 6 is
differentiated from previous work on the basis of its increased dynamic range (1.05 V
to greater than 3.3 V output voltage and less than 1 mW to 500 mW output power),
consideration of both tracking and regulation figures of merit, and fivefold
improvement in tracking metrics. This gives the converter broader application in
dynamic voltage scaling systems, particularly as their performance requests vary with
greater frequency.
147
Chapter 6
Prototype DC-DC
Converters
This chapter demonstrates the design techniques introduced in Chapter 4 and
Chapter 5 on three separate prototype DC-DC converter designs. A complete power
delivery system for an energy-efficient microprocessor is shown to demonstrate design
at both the system and circuit levels. Power system design decisions are documented in
Section 6.1. All high-speed communication from the processor to its peripherals is
made via the low-swing I/O circuits described in Chapter 2, yielding as much as a 275x
reduction in power. A small DC-DC converter provides a regulated voltage supply (with
an adjustable output from 0.1 V to 0.5 V) to power the I/O transmitters. Section 6.2
details the design of this ultra-low-voltage DC-DC converter. The processor core and
surrounding peripherals are operated from a dynamically scaled voltage supply,
achieving throughputs ranging from 100 MIPS at 3.3 V, to 5 MIPS at 1.05 V. At the 5
MIPS operating point, a nearly 10x improvement in energy per operation is achieved.
The dynamic DC-DC converter which enables this DVS scheme is described in Section
6.3.
A third prototype converter is described in Section 6.4. This 1 MHz PWM
converter is designed to provide a 1.5 V output at a 500 mA full load current. It was
6.1 Processor Power Delivery System 148
fabricated in 1994 to demonstrate the viability of the concepts presented in Chapter 4,
particularly zero-voltage switching with adaptive dead-time control.
6.1 Processor Power Delivery System
Figure 6.1 shows a power delivery system for an energy-efficient
microprocessor. Two voltage scaling strategies, enabled by DC-DC conversion, are
aggressively used to minimize overall energy consumption. First, inter-chip
communication from the processor to its memory and peripherals is accomplished via
the ultra-low-swing I/O transceivers introduced in Chapter 2. This provides as much as
a 275x power savings. An ultra-low-voltage DC-DC converter, whose design and
measured results are documented in Section 6.2, enables the transceivers, delivering a
regulated supply (adjustable from 0.1 V to 0.5 V) with an efficiency as high as 85%.
Second, dynamic voltage scaling is used to dynamically trade microprocessor
throughput and energy consumption, allowing performance on demand with minimum
energy consumption. The design and measured results of the dynamic DC-DC converter
which enables this DVS loop are presented in Section 6.3.
The remainder of this section contains a discussion of the power system design
issues and optimizations, first introduced in Chapter 4.
6.1.1 Supply Voltage Selection
The DC-DC converters leverage the three available power supply voltages for
improved energy efficiency. While all analog circuits must operate from the battery
voltage for headroom considerations, critical digital hardware is operated from the
dynamically scaled voltage supply. This scales the energy per operation of the
converters’ digital control circuits together with those of the microprocessor and
6.1 Processor Power Delivery System 149
L1
0.2 V
DC-DC
Lithium Ion C1
Cell
+
3.6 V
nominal
L2 1.05 V to > 3.3 V
-
DVS
C2
Battery:
Vbat(max) = 4.2 V
Vbat(nom) = 3.6 V
Vbat(min) = 3.0 V
Processor system:
Request
100 MIPS, 4.5 nJ/inst. at 3.3 V
5 MIPS, 0.4 nJ/inst. at 1.05 V Memory
Full-speed 32-bit bus (50 pF per bit) Processor and
32 bits Peripherals
DC-DC Converter:
Adjustable 0.1 V to 0.5 V output
> 80% efficiency Low-swing bus drivers
L1 = 10 µH, C1 = 20 µF
DVS Converter:
Dynamic 1.05 V to > 3.3 V output
20 µs tracking time
> 85% energy efficiency
L2 = 3.5 µH, C2 = 4.7 µF
Fig. 6.1: Power delivery for an energy-efficient microprocessor subsystem.
peripherals, helping to maintain conversion efficiencies. In addition, the 0.2 V supply is
utilized by the dynamic voltage converter to enable low-swing communication from the
processor to the dynamic DC-DC converter IC.

6.2 An Ultra-Low-Voltage DC-DC Converter 150
6.1.2 Shared Resources
The converters have been designed to share a 10 µA master bias, conserving
static power. Since the power of one master bias can be amortized over two converters,
the light-load efficiencies of each are improved. In addition, the 4 MHz DVS system
clock is utilized by both converters. This clock is required by the microprocessor
subsystem itself; thus, its power consumption does not count against either converter.
6.1.3 Highest Integration
The initial plans for implementation of this power system included the highest
levels of integration. However, integration of the converters together with the processor
load is deemed infeasible due to the large voltage transients on the power FET ground
lines. Since an epi process has been chosen for fabrication of the processor, sufficient
isolation of the power FET ground noise from the processor circuits cannot be
guaranteed.
Integration of both power delivery ICs on a single substrate is considered
technically feasible since all of the high-current power FET switching transitions are
synchronized to the same system clock. However, for testability, the two chips were
fabricated separately and assembled in their own packages. An improved second-
generation system might integrate both power ICs on a single substrate.
6.2 An Ultra-Low-Voltage DC-DC Converter
The processor subsystem of Figure 6.1 includes a full-speed 32-bit bus. If this
bus were switched at the full DVS output voltage, it would approximately double the
system energy per instruction. Assuming a 25% activity factor and 50 pF per bit, E bus =
4.4 nJ/inst at 100 MIPS and 3.3 V, and 0.4 nJ/instr at 5 MIPS and 1.05 V.
The analysis presented in Section 2.4 shows the energy savings effected by
powering the bus transmitters from the battery through an ultra-low-voltage DC-DC
converter. The converter-load system E bus is reduced by the ratio:
ηβ2 (Eq 6-1)
where η is the efficiency of the DC-DC converter, β is the ratio:
V dd
β = ----------- (Eq 6-2)
V LO
and V LO is the output of the ultra-low-voltage DC-DC converter. As indicated by (Eq 6-
1), even for very low efficiencies, the converter-load system results in a more energy-
efficient bus transmitter. For η = 0.7 and V LO = 0.2 V, E bus is reduced to 20 pJ/instr −
an addition of only 5% to the processor energy per instruction at 5 MIPS and 1.05 V. At
100 MIPS and 3.3 V, E bus adds less than one half of one percent to the processor energy
per instruction.
The primary challenges to the DC-DC converter design are the ultra-low
output voltage and current levels that must be supported with reasonable efficiency.
Therefore, all control system, architecture, and circuit-level decisions are made with
low-power as the principle design objective.
6.2.1 Control System Design
The output of the ultra-low-voltage DC-DC converter is regulated using a
constant on-time, synchronous PFM control scheme. By exploiting the existing 4 MHz
DVS system clock, this simple controller offers ultra-low static power dissipation. A
block diagram of the controller is shown in Figure 6.2. The system timing diagram is
shown in Figure 6.3.

Vref - VLO
comparator Vbat
−
driver
Vref + S
Q iL
250 ns R
VLO = 0.2 V
sampler L
driver
S
edge detector Q C LOAD
R
− +
NMOS current
comparator
Fig. 6.2: Ultra-low-voltage DC-DC converter block diagram.
The system is synchronized to the existing 4 MHz DVS reference clock. At the
0 ns edge, the Vref −V LO comparator bias is enabled. 125 ns later, the comparator
sampling and pre-amplification switches are sequenced to initiate the comparison of the
converter output, V LO , to a low-power external reference, Vref . At the 250 ns edge, the
comparator output is sampled. If Vref < V LO , the power PMOS device is left off, the
system idles for 4 µs, then the cycle repeats.
If Vref > V LO , the PMOS device is turned on (always on the 250 ns edge) and
conducts for T pmos = 250 ns. During this interval, inductor current i L ramps linearly
from zero to its peak value, I p . When the PMOS turns off (always on the 500 ns edge),
feedback timing control turns the NMOS device on to pick up the inductor current.
During NMOS conduction, i L ramps linearly from I p to 0. The expected NMOS
conduction time interval may be found relative to the PMOS conduction interval. This
was derived for a PFM converter in Chapter 3, and is repeated here:
( V bat – V LO )
T nmos = T pmos ⋅ --------------------------------- (Eq 6-3)
V LO
0 ns 250 ns 500 ns 1.5 ns 1.75 ns 0 ns 250 ns 4 us = 0 ns 250 ns

125 ns 125 ns 125 ns
clk4
Vo-cmp bias
Vo-cmp output valid
vgp
vgn
iNMOS-cmp 4 clocks
bias
iNMOS-cmp
output enable
Noff Tnmos
iL 0
Vref
VLO
Vo < Vref
deliver charge Vo > Vref Vo > Vref
idle for 4 us idle for 4 us
Fig. 6.3: Synchronous PFM system timing diagram.
The minimum interval, T nmos = 1.25 µs, is found at the 3.0 V minimum battery voltage
and the 0.5 V maximum output voltage. To conserve energy, the NMOS current
comparator bias is not enabled until 1 µs after the NMOS device is gated − the 1.5 µs
edge. The maximum interval, T nmos = 10.25 µs, is found at maximum battery (4.2 V)
and minimum output (0.1 V), and sets the upper limit to NMOS current comparator
energy dissipation. The comparator bias is given 250 ns to settle; its output is not
monitored until the 1.75 µs clock edge. The NMOS is turned off asynchronously by the
NMOS current comparator when i L has decayed to zero. The cycle then repeats, re-
synchronized at “0 ns” on the next rising edge of the 4 MHz clock.

The control system has been verified using matlab simulation. Figure 6.4 and
Figure 6.5 show the start-up transient and steady-state operating waveforms for L = 10
µH and C = 20 µF (see Section 6.2.3 for detail on component selection).
vx [V]
2
0
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
100
50
iL [mA]
−50
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
300
vo [mV]
200
100
0
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
time [ms]
Fig. 6.4: Start-up transient waveforms.
4
vx [V]
0
0.6 0.65 0.7 0.75 0.8
100
50
iL [mA]
−50
0.6 0.65 0.7 0.75 0.8
210
vo [mV]
205
200
195
0.6 0.65 0.7 0.75 0.8
time [ms]
Fig. 6.5: Steady-state waveforms.

6.2.2 Circuit Implementation
For lowest static power dissipation, the DC-DC converter exploits the existing
4 MHz clock and 10 µA master bias of the DVS system. While for headroom
considerations, analog components must run from the full lithium ion battery source
voltage, V bat , all critical digital hardware is supplied by the dynamically scaled voltage,
V dd . This allows minimization of periodic switching power, particularly at the 5 MIPS,
1.05 V processor operating point.
6.2.2.1 Master Control
The digital master control synchronizes the system to the 4 MHz clock, and
negotiates power-on reset sequencing. From Figure 6.3, it provides clocks for the Vref −
V LO comparator, triggers the i NMOS comparator sequence, and commands the power
transistors. At the core of the master control are 16 low-voltage TSPC registers and
various combinational logic which provide clock division and generation functions.
Figure 6.6 shows the positive edge triggered TSPC register with level-sensitive reset
input. Device sizes have been modified from the UC Berkeley low-power library to
allow operation down to 1.0 V at the 3σ fast NMOS / slow PMOS process corner.
CLK RST
6/2
4/2 19/2 p: 15/2
n: 5/2
Q
6/2
D CLK CLK
4/2 4/2
4/2
p: 3/3
n: 3/11
CLK
4/2 4/2 3/2 4/2
Fig. 6.6: TSPC register with operation to 1.0 V. Device sizes in λ = 0.3 µm.
Figure 6.7 shows the level converter circuit from the DVS output voltage, V dd ,
to the battery voltage, V bat , required by the comparator clocks and the power
transistors. Device sizes have been chosen to allow operation down to 1.0 V at the 3σ
slow NMOS / fast PMOS process corner.
During idle cycles (Vref > V LO ) the 4 MHz system clock is divided into a 16-
phase period at V dd . Once per idle cycle, the Vref −V LO comparator clocks are sequenced
by the master control at V bat . The effective switched capacitance during an idle cycle
is:
• C Vdd = 8.8 pF at V dd
• C Vbat = 0.5 pF at V bat
For V dd = 1.05 V and V bat = 3.6 V, this contributes 4.0 µW of static power dissipation.
During active cycles (Vref < V LO ) the 4 MHz system clock is divided into a 7-
phase period at V dd . The master control provides the Vref −V LO comparator clocks, the
power transistor control signals, and triggers the i NMOS comparator. The effective
switched capacitance during an active cycle is:
• C Vdd = 3.1 pF at V dd
• C Vbat = 1.4 pF at V bat
For V dd = 1.05 V and V bat = 3.6 V, this contributes 21.5 pJ of energy dissipation.
Vbat
Vdd
3/2 3/2 in 0
outb out
Vbat
in 38/2 38/2 inb
out 0
Fig. 6.7: Level converter circuit. Device sizes in λ = 0.3 µm.

6.2.2.2 Vref−VLO Comparator
Figure 6.8 shows a circuit schematic of the Vref −V LO comparator. The
comparator is similar to those described in [Yin92] and [Lynn95] and is known to have
a good combination of speed and accuracy with relatively low power dissipation.
The comparator switch sequence is shown in Figure 6.9. At rest, ΦBIAS is low,
ΦEQ is high, and ΦEVAL is low. The bias current is disconnected from the
aVdd swVdd
(from Masterbias) ΦEVAL

46/2 46/2
30 uA
23/2 23/2
1x
ΦBIAS R S
96/2
15/2 15/2
VLO 300/5 300/5 Vref
ΦEQ
S Q 5x U_Vref
Y X
4/5
15/2 15/2 R
Qb
aGND aGND
Fig. 6.8: Vref−VLO comparator schematic. Device sizes given in λ = 0.3 µm.
clk4
ΦBIAS
ΦEQ
ΦEVAL
tcmp
U_Vref
0 ns 125 ns 250 ns
Fig. 6.9: Vref−VLO comparator timing sequence.

preamplifier, nodes X and Y are shorted through a switch, and the cross-coupled PMOS
load is disabled. The comparator sequence is initiated by the master control at the “0
ns” edge when ΦBIAS is asserted, enabling the preamp. The equivalent preamplifier
circuit is shown in Figure 6.10. Here, the shorting switch is sized to ensure that the M3-
M4-R O positive feedback loop gain is less than one over process, temperature, and
battery discharge. The overall preamplifier gain of:
V XY gm 1 R O
A V = ---------------------------- = --------------------------- (Eq 6-4)
V ref – V LO 2 – gm 3 R O
varies as a function of process, temperature, and battery, from as large as 9 V/V to as
low as 0.8 V/V.
At the 125 ns edge, the master control lowers ΦEQ, and after a short non-
overlap interval, asserts ΦEVAL. The shorting switch is released, and V XY is amplified
and latched by the cross-coupled PMOS and NMOS loads to full digital levels. The
nand-based SR flip-flop generates a digital signal, “U_Vref”, which is high when the
Vdd
30 µA
VLO Vref
M1 M2
RO
Y X
M3 M4
positive feedback
(loop gain < 1)
Fig. 6.10: Preamplifier equivalent circuit.

converter output voltage falls below Vref . This output is sampled by the master control
approximately 125 ns after the assertion of ΦEVAL.
Circuit simulation results are shown in Figure 6.11. Static current consumption
is 30 µA during the 125 ns preamplification interval, but climbs to 270 µA during
evaluation. Here, an unanticipated short circuit path increases the static current
LVcmp.tr0
LVcmp.tr0
phibias
phieval
I(vbat)
u_vref
vref
phieq
vo
5.00u
5.00u
4.00u
4.00u
TIME (S)
TIME (S)
3.00u
3.00u
2.00u
2.00u
XP 1997.202, (c) 1997 Avant! Corporation
1.00u
1.00u
printed at 21:06:04 Oct 10, 1998 by anthonys

*** lvcmp test : 98/06/28 22:15:25
*** lvcmp test : 98/06/28 22:15:25

0.
0.
-16.15m
-2.15m
1.71m
0.22
0.21
0.21
0.20
0.20
0.19
3.60
3.60
3.60
3.60
0.
0.
0.
Fig. 6.11: Vref−VLO comparator circuit simulation waveforms.

3.6 V 3.6 V
3.6 V
30 uA
0.20 V 3.48 V
1.78 V
0.19 V 0.20 V
1.95 V 0.20 V
Fig. 6.12: Vref−VLO comparator short circuit path during evaluation.
consumption by a factor of nine. The short circuit path is present only during
evaluation. It follows the direction of decreasing bias voltages as shown in Figure 6.12.
Unfortunately, this problem was not discovered until after tape-out, and caused a
noticeable degradation in measured converter efficiency.
Since the worst-case comparison time is kept below 2 ns with a 1 mV
differential input signal, the comparator is highly overdesigned. The total energy
consumed per cycle is equal to:
E cmp = ( ( 125 ns ) ⋅ ( 30 µA ) + ( 125 ns ) ⋅ ( 270 µA ) ) ⋅ V bat
For V bat = 3.6 V, E cmp = 135 pJ.
6.2.2.3 iNMOS Comparator
The i NMOS comparator commands the turn-off transition of the synchronous
rectifier when i NMOS = 0 from above (Figure 6.3). Chapter 3 discusses the energy
Energy Penalty for Early and Late PFM NMOS Turn−Off

0.04
Early NMOS turn off (Ierror > 0)

Late NMOS turn off (Ierror < 0)
0.035
Normalized energy dissipation penalty [Ediss / Eload]

0.03
0.025
0.02
0.015
0.01
0.005
0
0 2 4 6 8 10 12 14 16 18 20
abs(Ierror) [mA]
Fig. 6.13: Energy dissipation penalty from iNMOS comparator error.
dissipation penalty associated with early and late NMOS turn-off (see (Eq 3-42) and
(Eq 3-43)). Figure 6.13 illustrates the results: Energy dissipation penalty normalized to
the energy delivered to the load in a single PFM burst is plotted as a function of the
i NMOS turn-off error, I ε .
Figure 6.13 helps determine the accuracy requirements of the i NMOS
comparator and gives some design guidance. For 1 mA of error in either direction, the
2
energy penalty is 5.0 pJ. This scales as ( I ε ⁄ 1 mA ) until I ε is large enough to induce
body diode conduction. Since the nominal energy delivered to the load during a single
PFM pulse is 38.2 nJ, this extra dissipation starts becoming important for I ε on the
order of 10 mA and above. Note from the plot that for such values of I ε , body diode
conduction is indeed induced. Here it is desirable to gate the NMOS device a little late,
rather than early. This is due to the fact that at such a low output to battery voltage
ratio, the PMOS body diode dissipates less energy than the NMOS body diode for equal
conduction intervals.
i NMOS is inferred through the voltage drop across the NMOS channel:
v dsNMOS = i NMOS ⋅ R N (Eq 6-5)
Since R N is as small as 75 mΩ, low offset voltage is a primary design consideration for
the comparator. For Vos = 1 mV, the equivalent i NMOS error is:
1 mV
I ε = ----------------- = 13.3 mA (Eq 6-6)
75 mΩ
Comparator delay is not as critical in this application. The inductor current
slope during NMOS conduction is small:
di NMOS – V LO – 0.2 V
- = ---------------- = – 20 µA ⁄ ns
-------------------- = ------------- (Eq 6-7)
dt L 10 µH
For every 1 ns of comparator delay, only a 20 µA I ε is introduced.
Low energy dissipation is also a primary design objective. The i NMOS
comparator is designed to consume energy only during PFM pulses. A strobed bias
network and gated clocks are employed to eliminate static dissipation.
The comparator topology, shown in Figure 6.14, has been inspired by
[Acker95]. Two input-offset cancelled differential amplifier stages form the main
preamplifier. A high gain differential to single-ended amplifier and a nand gate convert
the output to full-swing digital levels. In reset mode, the bias to the amplifiers is
disabled, switches phased Φ1, Φ2, and Φ3 are closed, and switches phased Φ4 are open.
To conserve static power, the master control does not enable the comparator bias until
exactly 1 µs after the power NMOS device is gated. In the succeeding 250 ns, the
Φ1 Φ2
Φ3 diffal to se
Φ4 C1 C3
+ + - + - +
Vin Φ4 Noff
- - + - + -
C2 C4
Φ3 Φout
Φ1 Φ2
digital output enable
1st gain stage 2nd gain stage
Fig. 6.14: iNMOS comparator topology.
preamplifier offset is stored on the interstage coupling capacitors. (The input capacitors
also serve to level-shift the inputs, extending the input common-mode range below
ground.)
Compare mode is entered in the sequence shown in Figure 6.15. The release of
reset mode is initiated by the master control after 250 ns of offset storage by opening
switches phased Φ1. Any charge injection mismatch into C1-C2 due to the opening of
switches phased Φ1 is amplified by the first stage and stored differentially on C3-C4.
Switches phased Φ2 and Φ3 are then released, and Φ4 is closed, connecting the power
NMOS drain and source terminals to the comparator input. Differential voltage stored
on the capacitors now subtracts from the input voltage, cancelling the offset voltages of
the preamp stages and any charge injection mismatch. The effective input-referred
offset voltage in compare mode is:
∆Q
V os,eff =  V OS2 + ---------- ⋅  --------------------------------
1
(Eq 6-8)
 C 3,4  A 1 ⋅ ( 1 + A 2 )
When v dsNMOS crosses zero, the i NMOS comparator gates the power device and disables
its own bias.
A transistor-level schematic of the differential gain stage is shown in Figure
6.16. Device sizes have been chosen to maximize gain-bandwidth product. Tail current
iLF 0
vgn
Noff_bias_S
Noff_Φ1_R
ΦBIAS
Φ1
Φ2
Φ3
Φ4
Φout
Noff
Fig. 6.15: iNMOS comparator switch sequence.
I B is chosen for bandwidth ( BW ≈ 30 MHz ) and power considerations. Current sources
I 1 < I B ⁄ 2 boost the single stage gain to greater than 10 V/V.
Coupling capacitors C1-C2 and C3-C4 are implemented as a metal3-metal2-
metal1 stack with an approximately 50% bottom-plate parasitic. 1 pF input capacitors
C1-C2 ensure that kT/C noise has a negligible impact on comparator accuracy. 200 pF
interstage coupling capacitors C3-C4 are chosen as a reasonable trade-off of charge
injection mismatch error and capacitive loading on the first differential gain stage.
aVdd
gmn ( gmp + gon )
gain = ----------- BW = --------------------------------
Mp Mp gmp CL
I1 I1
+
vo
−
Mn Mn
+ CL CL
vi AMP1 AMP2
−
Mn 24/0.6 21/0.6
IB Mp 1.2/0.9 1.5/1.2
IB 50 µΑ 30 µΑ
I1 10 µΑ 10 µΑ
aGND
Fig. 6.16: Differential gain stage in iNMOS comparator (device sizes in microns).
The differential to single-ended converter is implemented as a simple NMOS
differential pair with a PMOS mirrored load. The stage has high gain ( g m ⋅ r o ) and is
biased at 50 µA for bandwidth considerations.
The overall comparator has a linear gain of greater than 80 dB from input to
nand gate input. The simulated delay is less than 40 ns over process and battery
discharge, introducing an error of less than 0.8 mA into the system. With offset
cancellation, the 3σ input-referred offset voltage is estimated to be less than 0.5 mV,
introducing a worst-case error of 6.7 mA. The worst-case energy dissipation penalty
from this error is less than 80 pJ.
The total static current consumption is 140 µA (including 10 µA of bias
mirroring). The digital clock sequencers and switches yield an effective switched
capacitance of 3.5 pF per PFM pulse. The overall energy dissipation of the i NMOS
comparator per PFM pulse is given by:
2
Ei = 80 pJ + ( 3.5 pF ) ⋅ V bat + V bat ⋅ ( 140 µA ) ⋅ ( T nmos – 1 µs ) (Eq 6-9)
NMOS
(Eq 6-9) includes the energy dissipation penalty introduced by a worst-case early or late
NMOS turn-off. For V bat = 3.6 V, T nmos = 4.25 µs, and E i = 1.76 nJ − 4.6% of the
NMOS
38.2 nJ energy delivered to the output in a single PFM pulse.
6.2.2.4 Master Bias
The converter exploits the 10 µA DVS system master bias for low-power. A
circuit schematic is shown in Figure 6.17. A digital signal strobes the 10 µA current
mirror. When “disable” is high, all current sources are cut off, eliminating static
dissipation. When “disable” is low, triode PMOS degeneration devices improve current
source output resistance. Simple cascode current sources are avoided for headroom
considerations. High-swing cascode current sources require extra mirrors and are
therefore also avoided.
In idle cycles, the master mirror is enabled for 250 ns of the 4 µs period,
consuming an average current of 625 nA. During PFM pulses, the mirror is active
throughout the entire cycle, so that:
E bias = ( 250 ns + T pmos + T nmos ) ⋅ ( 10 µA ) ⋅ ( V bat ) (Eq 6-10)
For V bat = 3.6 V and V LO = 0.2 V, T nmos = 4.25 µs and E bias = 171 pJ per PFM pulse.
Vbat
disable
10/20
40/10
biasIN
PAD
10uA bias10uA bias30uA
Fig. 6.17: Strobed master bias schematic.

Vbat Vbat
C1 R1
Vref Vref
C2 R2
V bat V bat
V ref = ---------------- V ref = ----------------
C2 R1
1 + ------- 1 + -------
C1 R2
2
C1 ⋅ C2 2 V bat
P static = --------------------- ⋅ V bat ⋅ f P static = ---------------------
C1 + C2 R1 + R2
For Vbat = 3.6 V, Vref = 0.2 V: For Vbat = 3.6 V, Vref = 0.2 V:
C1 = 1 pF R1 = 1.7 MΩ
C2 = 17 pF R2 = 100 kΩ
P = 3.1 µW (for f = 250 kHz) P = 7.2 µW
Fig. 6.18: Simple reference voltage generation.
6.2.2.5 Voltage Reference
Since a precise V LO is not a system requirement, a simple resistor or capacitor
divider may be used to generate the voltage reference, Vref , from the battery source
voltage, V bat . Figure 6.18 summarizes the two approaches.
Due to the lack of a monolithic capacitor with low bottom-plate parasitic, a
resistor divider based reference is implemented at the board level in the prototype
converter. This approach provides the additional advantage that the reference can be set
to a continuous range of values by using potentiometers for R1 and/or R2. For the
values given in Figure 6.18, the voltage reference consumes 7.2 µW of static power
from a 3.6 V battery.

+ Wp = 12.3 mm
Lp = 0.6 µm
L = 10 µH
Vbat = 3.6 V RL = 0.23 Ω +
Wn = 25.1 mm RC = 0.09 Ω
Ln = 0.6 µm Vo = 0.2 V
C = 20 µF
- -
Fig. 6.19: Power train of the ultra-low-voltage DC-DC converter.
6.2.3 Power Train Design
The power train of the ultra-low-voltage DC-DC converter, including
component values, approximate parasitics, and device sizes, is shown in Figure 6.19.
Filter element values are selected according to the design equations of Chapter 3. L =
10 µH is chosen to sustain the maximum load at 0.2 V:
Iout(max) = ( 1.0 ) ⋅ ( 32 bits ) ⋅ ( 50 pF ) ⋅ ( 0.2 V ) ⋅ ( 100 MHz ) = 32 mA (Eq 6-11)
With V bat = 3.6 V, V LO = 0.2V, and T pmos = 250 ns, (Eq 3-22) gives:
2
1 ( 250 ns ) ⋅ ( 3.6 V – 0.2 V ) ⋅ ( 3.6 V )
Q L = --- ⋅ ---------------------------------------------------------------------------------------- = 191 nC (Eq 6-12)
2 ( 0.2 V ) ⋅ ( 10 µH )
C = 20 µF maintains V LO for up to 4 µs of load consumption at I out(max) with only 6.4
mV of voltage sag.
Power transistors are sized according to (Eq 4-11) to minimize total energy
dissipation in the nominal 3.6 V to 0.2 V case. Tapering factors of 10-12 are used in the
gate-drive buffers, adding only a small gate energy dissipation overhead.

Table 6.1 summarizes the significant mechanisms of power train energy
dissipation per PFM pulse in a 3.6 V to 0.2 V application. The output inductor is the
dominant contributor to overall loss, as expected. With approximately 38 nJ of energy
delivered from battery to output per pulse, an overall power train efficiency of 86% is
achieved.
Table 6.1: Power train dissipation.
Loss mechanisms Energy dissipation
PMOS channel 0.33 nJ
PMOS gate and switching 0.34 nJ

NMOS channel 0.77 nJ
NMOS gate and switching 0.81 nJ
Output inductor 2.54 nJ
Output capacitor 0.91 nJ
Other series Ra 0.50 nJ (estimated)
Total 6.2 nJ
a. Includes metallization, bonding, and PCB interconnections.
6.2.4 Simulation Results
Full-chip circuit simulations on extracted layout were performed using
Avanti’s Starsim simulator. Figure 6.20 shows the key circuit waveforms. Table 6.2
summarizes the simulated efficiencies.
With V bat = 3.6 V, V LO = 0.2 V, and the processor operating at 100 MIPS and
V dd = 3.3 V, the average load at the regulator output is 8 mA. Here, the DC-DC
converter delivers power at a respectable 80% efficiency, with the power train
dominating the loss. The converter and low-swing I/O load combination consumes 2.0
mW from the 3.6 V battery. From (Eq 6-1) and (Eq 6-2), the converter enables a bus
energy dissipation reduction to only 0.4% of its original value at the high throughput
operating point.
6.2 An Ultra-Low-Voltage DC-DC Converter
XP 1997.202, (c) 1997 Avant! Corporation
*** test entire low-voltage regulation system : 98/06/29 00:21:12
1.50
LVreg.tr0
0. clk4
Fig. 6.20: Low-voltage regulator circuit simulation waveforms.
3.61
-69.97m noff
3.62
-15.59m noff_bias_s
3.62
-16.72m noff_phi1_r
3.68
-37.92m phieval
3.61
-19.42m u_vref
3.60
-15.32m vgn
3.60
-0.80m vgp
3.75
-48.13m vo_bias
0.21
1.68n vout
86.21m
-2.38m i1(lf)
2.00u 4.00u 6.00u 8.00u
1.00u 3.00u 5.00u 7.00u 9.00u
TIME (S)
170
printed at 18:40:04 Dec 3, 1998 by anthonys
At the low throughput corner − 5 MIPS at V dd = 1.05 V − the DC-DC converter
delivers 80 µW at 56% efficiency. At this operating point, the converter enables overall
I/O dissipation reduction to 6.5% of its original value. Here, the power dissipation is
dominated by the Vref −V LO comparator. Had this comparator been designed for lower
power and more suitable delay, and if its short circuit path were eliminated, conversion
efficiency could be brought above 70% at the 5 MIPS and 1.05 V operating point.
The standby power of the converter is only 47.3 µW, and is also dominated by
the Vref −V LO comparator. This could be brought below 20 µW with a properly designed
comparator.
Table 6.2: Simulated efficiency of the ultra-low-voltage regulator.

Component 3.6 V to 0.2 V 3.6 V to 0.2 V 3.6 V to 0.2 V
at 8 mAa at 0.4 mAb at 0 mAc
master control 22.9 µW 4.1 µW 4.0 µW
Vref−VLO cmp 33.0 µW 33.7 µW 33.8 µW
iNMOS cmp 73.8 µW 3.7 µW 0
master bias 8.0 µW 2.5 µW 2.3 µW
voltage reference 7.2 µW 7.2 µW 7.2 µW
power train 256.3 µW 12.8 µW 0
Total 401.2 µW 64.0 µW 47.3 µW

η = 80% η = 56%
a. Processor throughput = 100 MIPS at Vdd = 3.3 V.

b. Processor throughput = 5 MIPS at Vdd = 1.05 V.
c. Processor shut down. Vdd = 1.05 V.
6.2.5 Measured Results
The ultra-low-voltage regulator was fabricated in a 0.6 µm single poly, triple
metal process in May, 1997. Figure 6.21 shows a chip plot, with 0.9 mm by 1.8 mm die
dimensions. The upper portion of the IC contains the PMOS and NMOS power
transistors, drivers, and 400 pF of tuned bypass capacitance. The bottom portion of the
chip includes the digital control and analog circuits. Separate supplies with local on-
chip bypassing are maintained for the power, digital, and analog components on the IC.
The chip is housed in a 16-pin DIP, with 2 pins each dedicated to VX, power
FET supply, and power FET ground. Double bonds are used to reduce the resistance of
these critical high current traces.
Full functionality of the regulator was achieved over the full battery voltage
(3.0 V to 4.2 V), dynamically scaled digital supply voltage (1.05 V to 3.3 V), and
output voltage (0.1 V to 0.5 V) ranges. Due to the long lead-time on 10 µH inductors, L
= 15 µH is chosen as an alternative, reducing full-load current capability to 67% of the
• 0.5 µm 1P3M CMOS
• Die size: 0.9 mm x 1.8 mm

NMOS
PMOS
• Single cell lithium ion input
400 pF Bypass • 0.1 V to 0.5 V programmable output
Digital control • Supports 25 Ω maximum load
• > 80% efficiency
iNMOS comparator
Master bias Vref-VLO comparator
Fig. 6.21: Ultra-low-voltage regulator chip plot.

design objective. This also results in an increase in PFM pulse frequency, and a
corresponding increase in switching, gate-drive, and control losses relative to the load
consumption.
Figure 6.22 and Figure 6.23 show medium load and light load steady-state
operating waveforms for V bat = 3.0 V, V dd = 1.5 V, and Vout = 0.2 V. Peak-to-peak
output voltage ripple is kept below 4.5 mV in either case, which is consistent with the
simulated waveforms of Figure 6.5.
Successful operation of the i NMOS comparator is shown in Figure 6.24. Here,
v x and i L detail is shown at the NMOS zero-current turn-off transition. The NMOS
power FET turns off with i L = -7.6 mA, introducing 433 pJ of loss, or 2.1% (with L = 15
µH). This error is acceptable, and near the value predicted in Section 6.2.2.3.
Conversion efficiency has been characterized as a function of load for V bat =
3.0 V, V dd = 1.5 V, with Vout = 0.2 V and Vout = 0.5 V (Figure 6.25). In general, these
iL
20 mA/div
vo (AC)
10 mV/div
vx
2 V/div
Fig. 6.22: Medium load steady-state operating waveforms. Vbat = 3.0 V, Vdd = 1.5 V, Vout = 0.2 V,
Iload = 3.0 mA.
iL
20 mA/div
vo (AC)
10 mV/div
vx
2 V/div
Fig. 6.23: Light load steady-state operating waveforms. Vbat = 3.0 V, Vdd = 1.5 V, Vout = 0.2 V,
Iload = 1.2 mA.
iL
20 mA/div
vx
1 V/div
Fig. 6.24: Detail of the zero-current NMOS turn-off transition (Vout = 0.2 V).
efficiencies are acceptable, but are somewhat lower than expected for three primary
reasons. First, the larger than expected inductor value adversely affects the efficiency
of the power train, and increases the average dissipation of the i NMOS comparator
simply because they switch 50% more often. This degrades overall conversion
efficiency nearly equally across the full load range. Second, the extra dissipation
caused by the short-circuit path in the Vref -Vo comparator is not budgeted. According to
circuit simulations, this short-circuit dissipation, present only during evaluation mode,
increases the average power of the comparator by a factor of five at V bat = 3.0 V and
nominal process. Since this comparator dominates the overall quiescent dissipation of
the regulator, light load efficiency is poor. Third, the power-down scheme of the master
bias is disabled on the IC. The bias is attached off-chip, introducing several picofarads
of parasitic capacitance, and increasing the required settling time. This increases
quiescent current by 10 µA, further hampering light load efficiency.
Figure 6.26 shows the mechanisms of loss measured on the regulator at V bat =
3.0 V, Vout = 0.2 V, and P load = 161 µW and 921 µW. The power train losses include the
power transistors with their gate drive, all losses associated with the package, the input
and output capacitors, and the output inductor. Also included in the power train losses
are the power consumption of all digital circuits which run from V bat . The analog power
includes the master bias, voltage reference, Vref -Vo comparator, and i NMOS comparator.
The digital circuits operated from V dd = 1.5 V include only the master control.
It may be concluded that this prototype low-voltage regulator is a success.
Even with a 60% light-load and low-voltage efficiency, it is the key enabler of the low-
swing I/O transceivers.

LVreg conversion efficiency

85
80
Vout = 0.2 V
Vout = 0.5 V
75
Efficiency [%]
70
65
60
0 1 2 3 4 5 6
Pload [W] x 10
−3
Fig. 6.25: Measured efficiency with Vbat = 3.0 V.
Mechansims of Loss at Vout = 0.2 V

300
Power Train
Analog
Digital at Vdd = 1.5 V
250
200 Data set 1: Pload = 161 uW

Power Dissipation [uW]
Data set 2: Pload = 921 uW
150
100
50
0
1 2
Fig. 6.26: Mechanisms of loss for Vbat = 3.0 V, Vout = 0.2V, light and heavy load.
6.3 Prototype Dynamic Voltage Scaling DC-DC Converter 177
6.3 Prototype Dynamic Voltage Scaling DC-DC Converter
In the energy-efficient microprocessor subsystem of Figure 6.1, the processor
core and surrounding peripherals are run from a dynamically scaled voltage supply,
enabling up to a 10x improvement in average energy per operation. This section
describes the implementation of a prototype dynamic DC-DC converter for application
in this DVS scheme. Measured results are reported.
6.3.1 System and Algorithm Description
Figure 6.27 shows a block diagram of the dynamic DC-DC converter prototype
IC in its DVS application. The desired frequency is commanded by the process
scheduler through the 7-bit digital word, M:
f des = M ⋅ ( 1 MHz ) (Eq 6-13)
The DVS loop forces the processor clock frequency, f VCO , to equal the commanded
frequency at a minimum voltage, V dd , thereby minimizing system power dissipation.
The dynamic DC-DC converter is designed to operate only in discontinuous
mode. Its output is regulated via a synchronous PWM-PFM control scheme. By
exploiting the 4 MHz DVS system clock and using low-power digital control
bootstrapped from the converter output, the controller achieves low static power
dissipation which scales together with the load. Pulse-width modulation commands the
quantity of charge delivered during each PFM pulse through the controlled power FET
conduction interval. A pulse skipping algorithm modulates the pulse frequency,
maintaining acceptable conversion efficiency over the dynamic range of the converter.
4 MHz
system clock
Vbat Vdd Vbat Vbat

TRACK
Vdd
vgp iL
p_on FET cntrl Vdd = 1.05 V to 3.3 V
Loop vx
p_off and
− Filter n_on L Idd
M Drivers vgn
7 +
Σ 8
n_off
C uP
fVCO
Frequency 4 4 Vbat
Detector
Current Comparators:
PMOS limit, NMOS limit
PMOS zero, NMOS zero
Vbat
p_on −
p_off Start-up
Logic +
pwrGD
Soft-start circuits
Fig. 6.27: Dynamic DC-DC converter block diagram.
A system timing diagram is shown in Figure 6.28. The frequency detector
generates an 8-bit digital representation of the frequency error, f err, every 1 µs. The
loop filter samples f err on the following falling edge of clk4. In the first cycle of Figure
6.28, f err = -1, and the converter idles until the next sampling instant. During this
interval, the processor discharges V dd, causing a corresponding decrease in f VCO . When
the sampled f err > 0, the loop filter translates f err into an update command for the DC-
DC converter. A PFM pulse is initiated by the PMOS power FET, and the power NMOS
functions as a synchronous rectifier, turned off by the NMOS zero current comparator
when i dsN decays to zero. The cycle then repeats.

clk4
clk1
ferr<7:0> -1 +1
update<3:0> 2 1 0
iL
Vdd
vgp
vgn
skip pulse deliver charge skip pulse
Fig. 6.28: DVS system timing diagram.
6.3.1.1 PWM Control
The pulse-width modulation algorithm contains proportional and feedforward
terms (Figure 6.29). A power FET conduction interval, Ton, is the controlled variable.
For a quantized frequency error:
f des – f VCO
f err = floor  ---------------------------- (Eq 6-14)
 1 MHz 
the controlled conduction interval is:
T on = ( 250 ns ) ⋅ ( feedforward + gain ⋅ f err ) (Eq 6-15)

RAM M
gain
+ feedforward
fdes + ferr +
Σ Σ Ton
−
fVCO
Fig. 6.29: PWM block diagram.
In (Eq 6-15), the Ton LSB is 250 ns, equal to one cycle of the 4 MHz DVS system clock.
The feedforward term is chosen as a function of M to sustain full load current or to
consume a 2% peak-to-peak output voltage ripple budget.
The transfer function is two-sided (Figure 6.30). For f err < 0, Ton < 0 and the
converter removes excess charge from its output capacitor. The PFM pulse is initiated
by the NMOS power FET, T nmos = T on , and the power PMOS is operated as a
synchronous rectifier. For f err > 0, the converter delivers charge to the output via a PFM
pulse initiated by the PMOS power FET.
Ton < 0: Remove charge Ton > 0: Deliver charge

0
Ton
iL < 0 iL > 0
|Ton|
0
Vdd
∆V < 0 ∆V > 0
Vdd
Fig. 6.30: Charge removal and delivery.

Current limiting is included to protect the power FETs and external filter
elements during large signal tracking transitions. The magnitude of peak positive and
negative inductor currents are limited to 1 A.
6.3.1.2 PFM Control
Pulse frequency modulation ensures that the converter switches only when
necessary, conserving power at low output voltage and light load. The pulse-skipping
algorithm is simple: For – 3 ≤ f err < 0 , the converter idles, allowing the processor to
discharge V dd , decreasing f VCO . For f err ≥ 0 or f err < – 3 , charge is delivered to or
removed from the output according to the PWM algorithm of (Eq 6-15).
Figure 6.31 summarizes the transfer function of the hybrid PWM-PFM
controller. PWM parameters gain LH , gain HL , feedforward LH and feedforward HL are
chosen as a function of the desired frequency, M. In Figure 6.31, f des = 24 MHz (M =
Transfer function from ferr to Ton

800
600
400
ferr ≥ 0: Tpmos = feedforwardLH + gainLH ferr
200
Ton [ns]
−3 ≤ ferr < 0: idle

0
−200 f < −3: Tnmos = feedforwardHL + gainHL |ferr|

err
−400
−600
−10 −8 −6 −4 −2 0 2 4 6 8 10
ferr (1 LSB per MHz)
Fig. 6.31: PWM-PFM transfer function from ferr to Ton.

24), gain LH = gain HL = 1/4 LSB per MHz, feedforward LH = 1 LSB, and feedforward HL
= 0.
6.3.1.3 Start-Up
A reliable start-up mechanism is required to enable bootstrapped operation of
the digital controller. Figure 6.32 shows a block diagram of the approach.
At power-on, V dd = 0, and the soft-start controller commands the DC-DC
converter. A simple synchronous PFM scheme, with a constant 500 ns on-time, is used
to ramp the output voltage. Once the output voltage exceeds a weak PMOS V GS ≈ 1.2 V ,
the pwrGD flag is raised, and the DVS controller assumes command of the converter,
initialized with M = 24. When 21 MHz < f VCO < 27 MHz , the TRACK signal falls,
indicating successful frequency regulation.
Vbat Vdd Vbat
pwrGD TRACK
power-on soft-start DVS

Vdd = 0 control control
Vdd ~ 1.2 V
M = 24
Fig. 6.32: Start-up algorithm.

Dynamic DC−DC Converter Simulation

100
MHz
50
1 us average VCO
Desired
0
0 0.5 1 1.5 2 2.5
−4
x 10
4
vo [V] 3
1
0 0.5 1 1.5 2 2.5
−4
x 10
2
1
iL [A]
−1
−2
0 0.5 1 1.5 2 2.5
time [sec] −4
x 10
Fig. 6.33: Simulated tracking performance.
6.3.1.4 System Simulation Results
The control system has been verified using matlab simulation. Figure 6.33
shows the simulated tracking performance with V bat = 3.6 V, L = 3.5 µH, and C = 4.7
µF. The large-signal 12 MHz to 90 MHz tracking transition settles within 20 µs.
Figure 6.34 shows regulation at commanded throughputs of 26 MHz and 95
MHz. The DC-DC converter pulse width and pulse frequency are reduced at the lower
output frequency. Output voltage ripple is kept below 2% at 26 MHz.

DVS simulated in regulation mode

27.5
27
MHz
26.5
26
25.5
1 1.5 2 2.5 3 3.5
−5
x 10
1.6
vo [V]
1.55
1 1.5 2 2.5 3 3.5

−5
x 10
0.3
0.2
iL [A]
0.1
−0.1
1 1.5 2 2.5 3 3.5
−5
x 10
DVS simulated in regulation mode

96
95
MHz
94
93
1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5
−4
x 10
3.2
3.15
vo [V]
3.1
3.05
1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5
−4
x 10
0.3
0.2
iL [A]
0.1
−0.1
1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5
−4
x 10
Fig. 6.34: Simulated regulation waveforms at 26 MHz (top) and 95 MHz (bottom).
6.3.2 Load Specifications
The processor is being designed to achieve a 100 MIPS throughput at 3.3 V
[Burd98]. Figure 6.35 shows the simulated and modeled performance of the integrated
ring oscillator which is designed to match the processor’s critical path.
The processor is expected to achieve an energy per operation of 4.5 nJ at the
3.3 V, 100 MIPS operating point, yielding an average full-load current of 135 mA. The
energy per operation scales with voltage as shown in Figure 2.1. This data, together
with the modeled ring oscillator performance of Figure 6.35, is used to generate a curve
of nominally expected processor full-load current versus throughput (Figure 6.36).
Typical processor usage statistics are required to fairly specify the design
objectives of the dynamic DC-DC converter. The frequency of transitions and expected
histogram of requested throughputs in a typical application are necessary to determine
the relative importance of regulation and tracking metrics. [Pering98] describes four
Ring Oscillator Performance

140
FAST
120 MODELLED
NOM
100
VCO frequency [MHz]
SLOW
80
60
df/dVdd [MHz/V]
40
20
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
Vdd [Volts]
Fig. 6.35: Simulated and modeled ring oscillator performance.

Full load current, Idd as a function of processor throughput

140
120
100
80
Idd [mA]
60
40
20
0
0 10 20 30 40 50 60 70 80 90 100
Throughput [MHz]
Fig. 6.36: Expected processor full-load current.
DVS voltage scheduling algorithms and reports simulation results on three benchmark
applications. These applications are shown to have distinctly different latency
requirements, workload demands, and desired throughput statistics, proving that there
are no “typical usage statistics” for which to design. Thus, to increase its utility in a
general-purpose processing DVS environment, the dynamic DC-DC converter must be
made to be a good low-voltage regulator (for improved energy efficiency) and a good
tracking system (for low-latency applications).
6.3.3 External Component Selection
Tracking and regulation metric trade-offs through filter element sizing have
been examined in Chapter 5. Here, minimization of output capacitance for superior
tracking metrics, with acceptable output voltage ripple and low-voltage efficiency, is
the primary design objective. Q L , L, and C are chosen according to (Eq 3-23), (Eq 3-
25), and (Eq 3-26) to sustain full load current in a 4 µs minimum repetition period with
acceptable output voltage ripple. (Eq 4-12), (Eq 3-29), and (Eq 5-12) provide estimates
to total losses in the power FETs, conduction loss in the filter elements, and additional
load energy dissipation due to output voltage ripple.
L = 3.5 µH and C = 4.7 µF are selected as a reasonable compromise between
tracking and regulation metrics. A fourfold improvement in tracking time and a sixfold
improvement in tracking energy are expected over previous dynamic DC-DC converters
[Wei96], [Namgoong97], [Kuroda98]. Power train and output voltage ripple losses are
kept below 4% at the low throughput corner. Figure 6.37 shows the charge delivered per
PFM pulse, the PMOS and NMOS conduction intervals, the output voltage ripple, and
the normalized regulation energy dissipation as a function of processor throughput for
L = 3.5 µH, C = 4.7 µF, and V bat = 3.6 V.
Charge delivered per PFM pulse PMOS and NMOS conduction times
550 3
500
2.5
450
400
2
350
QL [nC]
us
300 1.5
250
1 Tpmos
200
150 Tnmos
0.5
100
50 0
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Processor throughput [MHz] Processor throughput [MHz]
Zero−to−peak output voltage ripple Energy Dissipation

0.05 0.04
0.035
0.045
Energy dissipation normalized to energy delivered
0.03 Total
0.04
0.025
0.035
∆V / Vdd
0.02
0.03
0.015
PMOS
0.025
0.01
inductor
0.02
0.005 NMOS
∆V load energy penalty

0.015 0
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Processor throughput [MHz] Processor throughput [MHz]
Fig. 6.37: Regulation parameters. Pulse-skipping is applied for M < 48 MHz.

6.3.4 Frequency Detector
Figure 6.38 shows the frequency detector, which generates a digital
representation of the VCO frequency error averaged over a 1 µs period. The operating
system’s process scheduler determines the desired processor throughput, requesting an
integer multiple, M, of 1 MHz.
A seven-bit counter clocks rising edges from the VCO output frequency, f VCO .
The reference frequency, f REF = 1 MHz, which is derived from the 4 MHz DVS system
clock, asserts the asynchronous reset of the counter, resetting its output to zero every 1
µs. Just prior to the asynchronous reset, the output of the counter is given by:
f VCO
count(k) = floor  ---------------- + remainder(k-1) (Eq 6-16)
 1 MHz
where remainder(k-1) is the remainder of the truncation of (Eq 6-16) performed in cycle
(k-1).
This output is latched and subtracted from the 7-bit digital representation of
the desired frequency, M, yielding an 8-bit two’s complement digital error signal:
f err ( k ) = M – count(k) (Eq 6-17)
Operating System M 7 M 7
Loads Desired fCLK
Reg.
(in MHz)
Counter
RST
7 8 To Loop
fREF = 1 MHz
Σ Filter
fVCO
Fig. 6.38: Digital frequency detector.

which is proportional to the frequency error, averaged over cycle k, with an LSB of 1
MHz.
The frequency detector introduces a cycle-by-cycle quantization error which
becomes increasingly significant at lower processor throughputs. At the minimum
throughput of 5 MHz, cycle-by-cycle quantization error can be as high as 20%.
However, as illustrated by Figure 6.39, while the error is truncated every 1 µs, the
remainder of the error accumulates in the frequency detector, forcing the average
quantization error to zero. Thus, quantization contributes no DC offset to Vdd and f VCO ,
but does introduce additional AC ripple.
The frequency detector continuously evaluates, regardless of the converter’s
loading conditions, and therefore, consumes static power. So that its power
consumption scales at lower output voltages, it is operated from the voltage scaled
supply, V dd . The effective capacitance includes a 7-bit counter switching at the VCO
output frequency, a 2-bit clock divider switching at 4 MHz, and a 7-bit register and 8-
bit adder switching at 1 MHz. The average power dissipation is given by:
2 2
P FreqDetect = ( 1.1 pF ) ⋅ f VCO ⋅ V dd + ( 3.6 pF ) ⋅ ( 1 MHz ) ⋅ V dd (Eq 6-18)
cycle (k-1)
remainder = 0.41
cycle k cycle (k+1)
count = 7, remainder = 0.08 count = 6, remainder = 0.59
fVCO = 6.67 MHz
fREF = 1 MHz
Fig. 6.39: Quantization error in the frequency detector.

contributing 10 µW at the 5 MHz, 1.05 V operating point, and 1.2 mW at the 100 MHz,
1.05 V operating point.
The VCO output is driven from the processor to the dynamic DC-DC converter
IC. If swung rail-to-rail, its power consumption might prove to be the dominant
contributor to overall dissipation in the DVS loop. At the low throughput corner:
2
P VCO = ( 20 pF ) ⋅ ( 1.05 V ) ⋅ ( 5 MHz ) = 110 µW (Eq 6-19)
At the high-throughput corner:
2
P VCO = ( 20 pF ) ⋅ ( 3.3 V ) ⋅ ( 100 MHz ) = 22 mW (Eq 6-20)
If, instead, the 20 pF of parasitic capacitance is driven by the low-swing I/O transmitter
of Chapter 2 powered by the 200 mV output of the DC-DC converter of Section 6.2, the
total power dissipated in driving the inter-chip capacitance is significantly reduced.
2
P VCO = ( 20 pF ) ⋅ ( 0.2 V ) ⋅ ( 5 MHz ) = 4 µW (Eq 6-21)
at the low-throughput corner, and:
2
P VCO = ( 20 pF ) ⋅ ( 0.2 V ) ⋅ ( 100 MHz ) = 80 µW (Eq 6-22)
at the high-throughput corner.
The dynamic DC-DC converter includes a receiving pad to decode the
incoming 200 mV signal. A description of the receiver can be found in [Burd98]. Its
power consumption is given by:
2
P receiver = ( 15 µA ) ⋅ V bat + ( 0.9 pF ) ⋅ V dd ⋅ f VCO (Eq 6-23)
yielding 45 µW at 5 MHz, 1.05 V, and 1.0 mW at 100 MHz, 3.3 V. The total power
savings effected by the low-swing VCO transceiver is 1.8x at the low throughput
corner, and 20x at the high throughput corner. These numbers include the dissipation in
the 0.2 V regulator of Section 6.2.
6.3.5 Loop Filter
The loop filter translates f err into an update command for the DC-DC
converter. It implements the pulse-width modulation and pulse-skipping algorithms. It
is responsible for hand-off between regulation and tracking modes.
Tracking mode is initiated by a new frequency request from the process
scheduler. In tracking mode, the converter is capable of slewing its output up and down.
When f err > 0 , the VCO frequency is too low, and the converter is commanded to
deliver charge to the output capacitor. The PMOS device initiates the PFM pulse, T pmos
is the controlled variable, and the NMOS power FET acts as a synchronous rectifier.
When f err < 0 , the VCO frequency is too high, and the converter is commanded to
remove charge from the output capacitor. The NMOS device initiates the PFM pulse,
T nmos is the controlled variable, and the PMOS power FET acts as a synchronous
rectifier. When – 4 < f err < 4 , control is handed to regulation mode.
In regulation mode, the converter can only deliver charge to the output
capacitor, it cannot remove it. When f err ≥ 0 , a PFM pulse is initiated by the power
PMOS device. When f err < 0 , the converter idles and the loop filter continues to
monitor the frequency error until f err ≥ 0 .

g 16 x 16 M<6:3>
2 SRAM 4
FF clk4
4
Vdd to Vbat
fmag update
P_on
ferr 2’s complement 7 >> + 4
8
REG 8 8
Ton N_on
to sign / mag
ferr<7>
fsgn
>
enable
clk4 TRACK
Fig. 6.40: Loop filter implementation.
Figure 6.40 shows a block diagram of the loop filter implementation. f err
swings at V dd ; all other signals are driven at V bat . The “enable” block implements the
pulse-skipping function, clocking f err on the falling edge of clk4 under the following set
of conditions:
• Neither power FET is conducting, and
• TRACK is high, or
• TRACK is low and f err<7> is high
The 8-bit two’s complement f err is level-shifted to V bat and converted to an 8-bit sign /
magnitude representation. In tracking mode, f sgn determines which power FET is
controlled.
The PWM algorithm is given in (Eq 6-15). An intermediate variable, update, is
a 4-bit unsigned word:
–g
update = FF + 2 ⋅ f mag (Eq 6-24)
which stores Ton in LSB. The loop filter saturates at update = 15, constraining the
maximum on-time to 3.75 µs. Feedforward and gain terms are set as a function of the
four MSBs of the desired frequency, M. Unique values of FF and g are chosen for low-
to-high and high-to-low tracking transitions.
The “Ton” block negotiates power FET sequencing and converts update into a
controlled conduction interval:
T on = update ⋅ 250 ns (Eq 6-25)
The loop filter consumes no static power: It switches only during active PFM
pulses. The energy dissipated per DC-DC converter switching event is data dependent,
but for high-level energy budgeting, it is approximated by:
2 2
E filter = ( 1.7 pF ) ⋅ V dd + ( 9.2 pF ) ⋅ V bat (Eq 6-26)
which equals 120 pJ (0.2%) at the low throughput corner and 138 pJ (negligible) at the
high throughput corner.
6.3.6 Current Comparators
The prototype converter uses four sets of offset-cancelled comparators,
identical to the one shown in Figure 6.14, for zero-current detection and current
limiting in the power transistors. To conserve quiescent power, strobed biasing and
gated clocks are employed.
6.3.6.1 PMOS current limit
The PMOS current limit protects the power FETs and external filter elements
during large signal tracking transitions. The peak conducted PMOS current is limited to
0.5 A or 1.0 A 1 in tracking mode.

comparator
trip point
vx iL
xN x1 +
Poff
vx REF
REF
iL iREF -
IlimP comparator t
Power PMOS Reference generator tCMP
Fig. 6.41: PMOS current limit implementation.
The circuit implementation is shown in Figure 6.41. It consists of one offset-
cancelled comparator, a x1 reference FET, identically matched to the xN power FET,
and a known current i REF. The comparator begins to switch when inductor current, i L ,
conducted through the PMOS power FET induces a source-to-drain voltage drop greater
than that induced by i REF flowing through the reference FET. The accuracy of the
comparator trip point:
i L = iREF ⋅ N (Eq 6-27)
is determined primarily by the control on the absolute value of i REF, and the matching
of the x1 reference FET to the xN PMOS power FET.
This circuit is activated only during tracking PFM pulses which are initiated
by the PMOS device. It includes a strobed bias network and gated clocks for low-power.
It dissipates no static power during regulation mode.
6.3.6.2 NMOS current limit
The NMOS current limit is nearly identical to the PMOS current limit of
Figure 6.41. It is activated only during tracking PFM pulses which are initiated by the
1. In the prototype, the current limit may be adjusted with the Ilim_1A pin.
NMOS device, and dissipates no static power during regulation mode. Peak negative
NMOS current is limited to -0.5 A or -1.0 A.
6.3.6.3 NMOS zero-current detection
The i NMOS comparator implementation was described in Section 6.2.2.3 for
application in the low-voltage regulator IC. The NMOS off comparator performs the
identical function in the dynamic DC-DC converter: It commands the turn-off transition
of the NMOS synchronous rectifier when i dsN crosses zero from above.
The equivalent input-referred offset voltage (Vos = 0.5 mV) and delay (t cmp ~
50 ns 2 ) of the comparator are listed in Section 6.2.2.3. In the DVS application, the
worst-case NMOS turn-off current error is:
0.5 mV 1.05 V
I ε = -------------------- + ( 50 ns ) ⋅ ----------------- = 3.1 mA + 15.0 mA (Eq 6-28)
160 mΩ 3.5 µH
and
0.5 mV 3.3 V
I ε = ------------------ + ( 50 ns ) ⋅ ----------------- = 12.5 mA + 47.1 mA (Eq 6-29)
40 mΩ 3.5 µH
for the low and high throughput operating points. This translates to worst-case energy
dissipation penalties of 0.57 nJ (0.8%) and 6.2 nJ (0.4%), respectively. In an effort to
reduce these dissipation penalties, an integral feedback loop, similar in principle to
adaptive dead-time control (see Section 4.2.3), is used to null the comparator, logic,
and power FET gate-drive delays. Figure 6.42 describes the approach.
The circuit implementation includes two identical offset-cancelled
comparators. The NMOS off comparator commands the power NMOS turn-off
2. Includes 30 ns comparator delay, and up to 20 ns additional logic and gate-drive delay.

iREF
REF REF comparator
+ iL
1x matched reference FET Noff trip point
iL
vx pGND
-
1000x NMOS power FET
pGND t
NMOS off comparator
tCMP
Reference generator
vx iREF = N * ILSB
+
up/dn N
+ -1
z
pGND 5 bits
-
Update comparator
Digital integrator
Fig. 6.42: NMOS off delay cancellation.
transition. The update comparator monitors the results and adapts the NMOS off trip
point to null its delay.
The NMOS off comparator begins to switch when
v REF = v pGND (Eq 6-30)
where pGND is a Kelvin connection to the power NMOS source terminal. The reference
generator includes a matched reference FET and a digitally-programmable current
source, i REF, so that the trip point of the comparator is given by:
W NMOS
i L = i REF ⋅ -------------------- = 1000 ⋅ i REF (Eq 6-31)
W REF
Proper adjustment of i REF is ensured by the integral feedback loop. A digital integration
scheme is selected to allow maintenance of state without static power dissipation. The
effective LSB is i NMOS ~ 2 mA.
Gated clocks and strobed biasing are used to eliminate static power. The
comparators are enabled by the power PMOS turn-on − during positive PFM pulses only
− and are disabled 125 ns after NMOS turn-off. The reference generator, with 0 to 62
µA of static current, is enabled 125 ns after NMOS turn-on, and is disabled at NMOS
turn-off. The overall energy dissipated per NMOS off event is given by:
1 2 2
E = --- LI ε + ( 8.0 pF )V bat + V bat ⋅ ( ( 310 µA ) ( T p + T n + 125 ns ) + ( 30 µA )T n ) (Eq 6-32)
2
(Eq 6-32) includes the energy dissipation penalty associated with early or late NMOS
turn-off, and assumes i REF = 30 µA. For V bat = 3.6 V, E = 1.2 nJ (1.7%) at the low
throughput corner. Here, it is interesting to note that the adaptive timing control
actually costs 60 pJ of additional dissipation. At the high throughput corner, E = 4.1 nJ
(0.2%), and the adaptive timing control conserves 4.0 nJ.
6.3.6.4 PMOS zero-current detection
The PMOS off comparator is nearly identical to the NMOS off comparator. It
commands the turn-off transition of the PMOS synchronous rectifier when i dsP crosses
zero from below. It includes an adaptive timing control loop to null comparator, logic,
and power FET gate-drive delays.
The comparators are enabled by the power NMOS turn-on − during negative
PFM pulses only − and are disabled 125 ns after PMOS turn-off. The bias is never
enabled during regulation mode. Strobed biasing and gated clocks assure that it
dissipates no static power.

6.3.7 Power FETs
The integrated power FETs are binary weighted, with two control bits each for
independent dynamic NMOS and PMOS sizing. The NMOS and PMOS gate-width
LSBs are 10 mm and 20 mm, respectively. The minimum drawn channel length of 0.6
µm is used.
Figure 6.43 shows the power FETs, gate-drive, and dynamic transistor sizing
modules. The FETs are dynamically sized versus requested throughput, M, a-priori,
with appropriate control bits Wp0, Wp1, Wn0, Wn1 stored in RAM. Switching and
gate-drive loss are traded with conduction loss at each operating point according to (Eq
4-11). The total FET energy dissipation is given by:
1 2  Rp Rn  2
E diss = --- ⋅ I p ⋅  T p ⋅ -------- + T n ⋅ -------- + V bat ⋅ ( C overhead + W p ⋅ C p + W n ⋅ C n ) (Eq 6-33)
3  W p W n
where subscripts p and n indicate contributions due to PMOS and NMOS power
transistors; I peak is the peak PFM pulse current, found from (Eq 3-19); W is the gate-
width in LSB; T is the conduction time interval, found from (Eq 3-20); R is the
effective channel resistance of an LSB, listed in Table 6.3; and C is the effective
switched capacitance of an LSB:
C = C gd + C gs (Eq 6-34)
C p = 49 pF and C n = 32 pF also accounts for dissipation in the gate drive. C overhead is
the overhead capacitance, equal to:
C overhead = 3C gdp + 3C gdn + 3C dbp + 3C dbn + C x = 120 pF (Eq 6-35)
Figure 6.44 shows the gate-widths and expected energy dissipation for the
prototype IC implementation.
Table 6.3: Simulated power FET LSB channel resistance.

Rp Rn
slow, 3.0 V 440 mΩ 224 mΩ
nom, 3.6 V 343 mΩ 189 mΩ
fast, 4.2 V 289 mΩ 168 mΩ
Vbat Vbat
Cgdp 2 Cgdp
Cdbp 2 Cdbp
Power PMOS
Cgsp 1LSB 2 Cgsp 2LSB
Cgdn 2 Cgdn
Cdbn 2 Cdbn
Power NMOS Cx
Cgsn 1LSB 2 Cgsn 2LSB
8.98 10.33
p0
20 mm / 0.6 µm
22x 196x
PMOS LSB
8.98 10.33
NMOS LSB
n0 10 mm / 0.6 µm
11x 98x
Wn0 Wp0
n0 p0
3x 1.5x 24x
vgn_in 1x vgp_in 3x
1x 6x 6x
3x 48x
n1 Wp1 p1
Wn1
nmos size pmos size
Fig. 6.43: Power FETs, gate-drive, and dynamic sizing module.

Power FET size and losses

4
FET size [LSB]

2
1 Wpmos
Wnmos
0
0 10 20 30 40 50 60 70 80 90 100
0.025
Epmos
Normalized dissipation
0.02
Enmos
Eoverhead
0.015
0.01
0.005
0
0 10 20 30 40 50 60 70 80 90 100
Throughput [MHz]
Fig. 6.44: Prototype power FET size and losses.
6.3.8 Summary of Expected Efficiency
Figure 6.45 plots the expected converter efficiency versus throughput at full-
load and at one-quarter-load. The mechanisms of steady-state loss in the DVS system
are summarized in Table 6.4. All losses in the power train, controller, and processor
load are considered. The DVS system is expected to dissipate 138 µW and 3.4 mW of
static power at the low throughput and high throughput corners, with the converter
consuming the majority of the power. Here, the primary mechanisms of dissipation
include the processor VCO, and the VCO receiver, frequency detector, and master bias
of the DC-DC converter. Considering all losses in the processor and converter at full-
load, the system energy per operation is expected to be 0.3 nJ/instruction at 5 MIPS and
1.05 V, and 4.6 nJ/instruction at 100 MIPS and 3.3 V.

Expected DVS Efficiency

1
0.95
0.9
0.85
Efficiency
0.8
1/4 full load
full load
0.75
0.7
0.65
0.6
0 10 20 30 40 50 60 70 80 90 100
Processor Throughput [MHz]
Fig. 6.45: Expected converter efficiency vs. processor throughput at heavy and medium loads.
Table 6.4: Mechanisms of loss in the DVS system.
5 MHz 5 MHz 100 MHz 100 MHz

Mechanism of
Equation or Source 1.05 V 1.05 V 3.3 V 3.3 V
Loss
0 mA 1.2 mA 0 mA 135 mA
PROCESSOR
Processor Figure 6.36 0 1.26 mW 0 446.0 mW
VCO Simulated result 6.3 µW 6.3 µW 0.98 mW 0.98 mW
Low-swing VCO (Eq 6-21) and (Eq 6-22) 4.0 µW 4.0 µW 80.0 µW 80.0 µW
interconnect
TOTAL LOAD uP + VCO + transmitter 10.3 µW 1.27 mW 1.06 mW 447.0 mW
DYNAMIC DC-DC CONVERTER
Master Bias 20 µA static current from 72 µW 72 µW 72 µW 72 µW

Vbat
VCO receiver (Eq 6-23) 45 µW 45 µW 1.0 mW 1.0 mW
Freq Detect (Eq 6-18) 10 µW 10 µW 1.2 mW 1.2 mW
Loop Filter (Eq 6-26) 0 1.9 µW 0 35.1 µW
NMOS off (Eq 6-32) 0.2 µW 18.6 µW 2.7 µW 1.1 mW
FET control Ceff = 1.6 pF at Vbat 0 0.3 µW 0 5.7 µW

per PFM pulse
Power FETs (Eq 6-33) 0.6 µW 74.7 µW 9.6 µW 4.1 mW

Table 6.4: Mechanisms of loss in the DVS system.
5 MHz 5 MHz 100 MHz 100 MHz

Mechanism of
Equation or Source 1.05 V 1.05 V 3.3 V 3.3 V
Loss
0 mA 1.2 mA 0 mA 135 mA
L (Eq 3-29) 0.1 µW 14.7 µW 6.0 µW 2.5 mW

RL(dc) = 0.09 Ω
RL(ac) = 0.3 Ω
C (Eq 3-29) 0.1 µW 11.7 µW 4.7 µW 0.6 mW

Resr = 0.08 Ω
Stray inductance (Eq 3-45) 0 2.3 µW 0.2 µW 96.0 µW

Ls = 9.0 nH
Series resistance (Eq 3-29) 0 5.2 µW 2.1 µW 0.9 mW

Rs(pmos) = 17.8 mΩ
Rs(nmos) = 17.8 mΩ
TOTAL LOSS Σ (All converter losses) 128.0 µW 256.4 µW 2.30 mW 11.6 mW
SYSTEM DISSIPATION 138.3 µW 1.53 mW 3.36 mW 458.6 mW
EFFICIENCY − 83.8% − 97.5%
6.3.9 Layout, Assembly, and Test
The prototype converter was fabricated in a single poly, triple metal CMOS
process through the MOSIS program in August, 1997. Figure 6.46 shows the IC layout,
with die dimensions of 1.68 mm x 3.41 mm. The power section includes 1.6 nF of
integrated bypass capacitance tuned to τ RC = 2.6 ns. Considerable die area is devoted to
the six offset-cancelled comparators, whose offset storage capacitors are implemented
as metal1-metal2-metal3 sandwiches. Separate power FET, high-voltage digital, low-
voltage digital and analog supplies are maintained for isolation and power
characterization.
The IC is assembled in a 68 J-lead ceramic chip carrier, and mounted to the
printed circuit board in a through-hole socket. The pinout and pin description are given
in Figure 6.47, and Table 6.5. Table 6.6 estimates the parasitics added in series with the
power train.
VX PADS
GATE-DRIVE
pGND PADS
pVDD PADS PMOS NMOS
BYPASS • 0.5 µm 1P3M CMOS
BYPASS • Die size: 1.68 mm x 3.41 mm
EEPROM FET CNTRL • Single cell lithium ion input

RAM
CNTRL and
LOGIC
FREQ LOOP • 1.05V to > 3.3V dynamic output
DETECT FILTER
• > 85% energy efficiency

NMOS LIMIT
PMOS LIMIT
• 20 µs 1.05V to 3.3V tracking time
• 4.6 µJ 1.05V to 3.3V to 1.05V tracking energy

NMOS OFF
PMOS OFF
START-UP
BIAS
Fig. 6.46: Chip layout.
Table 6.5: Pin description.
Name Numbers Type Description
VX 1-6, 65-68 Power Power FET switching node
pVDD 10-15 Power Power FET Vbat
pGND 55-60 Power Power FET GND
Vbat 18, 48, 51 Power Digital supply at Vbat
Vdd 20, 31 Power Digital supply at Vdd
GND 19, 21, 30, 47, 50 Power Digital GND

68
67
66
65
6
5
4
3
2
1
VX
VX
VX
VX
VX
VX
VX
VX
VX
VX
10 60
pVDD pGND
11 59
pVDD pGND
12 58
pVDD pGND
13 57
pVDD pGND
14 56
pVDD pGND
15 55
pVDD pGND
16 54
RAM_dOUT vgp
17 53
18
RAM_cs DVS Prototype clk4
52
Vbat vgn
19 51
GND 68 LDCC Vbat
20 50
Vdd GND
21 49
GND PORB
22 48
RAM_dIN Vbat
23 47
RAM_clkout GND
24 46
serialM pwrGD
25 45
readM TESTenable
26 44
TRACK Ilim_1A
enextclk
fclk_out
fclk_in
aGND
aGND
extclk
aVdd
GND
ibias
Vref
Vdd
Vfb
30
31
32
33
34
35
36
37
38
39
40
41
Fig. 6.47: IC pinout.
aVdd 38 Power Analog supply at Vbat
aGND 36, 41 Power Analog GND
vgpa 54 Digital output at Vbat Power PMOS gate
vgna 52 Digital output at Vbat Power NMOS gate
clk4 53 Digital input at Vbat 4 MHz, 50% duty clock input
PORB 49 Digital input at Vbat ResetB signal
pwrGDa 46 Digital output at Vbat Indicates completion of soft-start
RAM_dOUT 16 Digital output at Vbat Data from converter to EEPROM
RAM_cs 17 Digital output at Vbat EEPROM enable
RAM_dIN 22 Digital input at Vbat Data from EEPROM to converter
RAM_clkout 23 Digital output at Vbat EEPROM 125 kHz clock
serialM 24 Digital input at Vdd Serial load of M
readM 25 Digital input at Vdd Enable serial load of M

TRACKa 26 Digital output at Vbat Indicates status of control loop
fclk_outa 32 Digital output at Vdd Decoded VCO output
enextclk 33 Digital input at Vdd Enable full-swing VCO input
extclk 34 Digital input at Vdd Full-swing VCO input

fclk_in 35 Analog input Low-swing VCO input
Vref 37 Analog input Low-swing reference voltage
Vfb 39 Analog input Vdd Kelvin sense
ibias 40 Analog input Attach 10 µA pull-down source

Ilim_1A 44 Digital input at Vbat Sets 1 A or 0.5 A current limit
TESTenable 45 Digital input at Vbat Sets test mode
a. Output is enabled only when TESTenable = 1.
Table 6.6: Estimated package parasitics.
Parameter Package Socket Total
VX inductance 0.6 nH 2.0 nH 2.6 nH

VX resistance 2.8 mΩ 3.0 mΩ 5.8 mΩ
pVDD inductance 1.5 nH 3.0 nH 4.5 nH
pVDD resistance 6.9 mΩ 5.0 mΩ 11.9 mΩ
pGND inductance 1.5 nH 3.0 nH 4.5 nH
pGND resistance 6.9 mΩ 5.0 mΩ 11.9 mΩ
A simplified PCB schematic is given in Figure 6.48. The converter under test
is loaded by an emulated microprocessor which includes an integrated VCO and 4-bit
programmable digital CMOS load. The VCO output, routed to the dynamic DC-DC
converter, can be selected to swing at the full V dd rail, or at a reduced 200 mV rail. At
power-on, the internal 16 x 16 SRAM of the converter is loaded with dynamic transistor
sizing codes, and PWM variables gain LH , gain HL , feedforward LH , and feedforward HL
by the NM93CS06LN EEPROM. Frequency requests are loaded serially using the
readM and serialM pins of the converter. Figure 6.49 shows the serial load for f des = 17
MHz.
Vbat
Vbat
EEPROM 4 3.5 µH
DVS vx Vdd
Prototype
clk4
4.7 µF
CPU Load
fVCO
LV_fVCO
Idd 4
4 MHz
2
Vbat Vdd
Programmable CPU Load
DAS
Level 0.2 V
or
∼
Converters Transmitter
FPGA
VCO
Fig. 6.48: Simplified schematic of the DVS test board.
clk4
readM
serialM
1 0 0 0 1 0 0
Fig. 6.49: Serial load of desired frequency with M = 17.
The prototype IC has been successfully demonstrated to track frequency
requests in the µs to tens of µs time scale, and to regulate with 80% to 90% full-load
efficiencies over the full 5 MHz to 100 MHz dynamic range. The following subsections
detail the results.

iL
TRACK
Vdd
pwrGD
Fig. 6.50: Start-up transient from Vdd = 0 to Vdd = 1.2 V.
6.3.10.1 Start-Up
Figure 6.50, Figure 6.51, and Figure 6.52 show successful operation of the
start-up sequence. In Figure 6.50, the soft-start transient from V dd = 0 to V dd = 1.2 V is
captured. Figure 6.51 provides detail of handoff from soft-start to tracking mode and
shows the relative timing of the pwrGD and TRACK flags. Figure 6.52 shows the VCO
output regulated near 24 MHz when TRACK goes low.
6.3.10.2 Tracking Performance and Current Limit
Figure 6.51 shows a short tracking transition from V dd = 1.20 V to V dd = 1.47
and f VCO = 24 MHz, with V bat = 3.3 V and a 0.5 A current limit. Here, the measured
current limit is 360 mA and tracking time is to the order of 10 µs. In Figure 6.53, this
same tracking transition is shown with an expected 1.0 A current limit (measured to be
0.8 A), reducing tracking time to 6.3 µs.

iL
pwrGD
Vdd
TRACK
Fig. 6.51: Start-up transient, showing relative timing of pwrGD and TRACK.
fVCO
Vdd
TRACK
Fig. 6.52: Start-up transient, showing fVCO = 23.4 MHz when TRACK falls.
iL
Vdd
pwrGD
TRACK
Fig. 6.53: Tracking transition with a 1.0 A current limit.
In Figure 6.54 and Figure 6.55, full-scale 5 MHz to 100 MHz and 100 MHz to
5 MHz tracking transitions are made with V bat = 6.0 V, at medium load, and with a 1.0
A current limit. The low-to-high tracking time of 23.5 µs is slew limited by the forward
PMOS current limit. The high-to-low tracking transition is slower by design and
measured to be 44.0 µs. The -1.1 A reverse NMOS current limit slew limits the early
portion of the output voltage excursion. The feedback loop intentionally slows the latter
part of the transition to a first-order decay, eliminating the possibility of undershoot.
Table 6.7 summarizes tracking performance for a variety of high-to-low and
low-to-high frequency transitions at 1/4 full-load and V bat = 6.0 V. Tracking time is
measured from the rising to falling edges of the TRACK signal, yielding the 0% to
f des – 3 MHz points. Tracking energy is estimated for the entire low-to-high-to-low
iL
Vdd
TRACK
Fig. 6.54: A 5 MHz to 100 MHz tracking transition.
iL
Vdd
TRACK
Fig. 6.55: A 100 MHz to 5 MHz tracking transition.

tracking cycle from C = 4.7 µF, the measured steady-state dissipation as a function of
f VCO , and the measured V dd(t) waveform.
Table 6.7: Tracking performance summary.
Transition Tracking Time Tracking Energya
fVCO = 5 MHz to 100 MHz 23.5 µs 4.6 µJ

Vdd = 1.08 V to 3.78 V
fVCO = 100 MHz to 5 MHz 44.0 µs

Vdd = 3.78 V to 1.08 V

Vdd = 1.39 V to 1.82 V

Vdd = 1.82 V to 1.39 V

Vdd = 1.82 V to 2.95 V

Vdd = 2.95 V to 1.82 V
a. Estimated for the full low-to-high-to-low tracking cycle.
6.3.10.3 Regulation Performance
Figure 6.56 and Figure 6.57 show regulation at f VCO = 24 MHz, with V bat = 3.3
V, under a large 22 mA load, and a small 1 mA load. The PFM period scales with load
as expected, with the average T = 7 µs and T = 140 µs at heavy and light loads. The
peak-to-peak output voltage ripple of 3.8% is near the anticipated value.
Figure 6.58 and Figure 6.59 show regulation at f VCO = 102 MHz, V dd = 3.78 V
for a commanded M = 100, V bat = 4.0 V, and 1/4 full-load. The output voltage is tightly
regulated, with 110 mV maximum peak-to-peak ripple.
Figure 6.60 and Figure 6.61 show regulation at f VCO = 6 MHz, V dd = 1.08 V
for a commanded M = 5, V bat = 4.0 V, and 1/4 full-load. The 29 mV peak-to-peak output
voltage ripple is 2.7% of V dd − slightly larger than anticipated, but still contributing
little additional load energy dissipation.

iL
Vdd (AC)
vgn
vgp
Fig. 6.56: Regulation waveforms at Vdd = 1.47 V, fVCO = 25 MHz, Idd = 22 mA.
iL
Vdd (AC)
vgn
vgp
Fig. 6.57: Regulation waveforms at Vdd = 1.47 V, fVCO = 25 MHz, Idd = 1 mA.
Vdd
VCO
Fig. 6.58: Regulation waveforms: 102 MHz at 3.78 V.
iL
Vdd(AC)
vx
Fig. 6.59: Power circuit waveforms: Vdd = 3.78 V, 1/4 full-load.

Vdd
VCO
Fig. 6.60: Regulation waveforms: 6 MHz at 1.08 V.
iL
Vdd(AC)
vx
Fig. 6.61: Power circuit waveforms: Vdd = 1.08 V, 1/4 full-load.

Regulation efficiency at full−load

94
92
90
Efficiency [%]
88
86
84
82
80
0 10 20 30 40 50 60 70 80 90 100
Throughput request, M
Fig. 6.62: Efficiency in regulation mode.
Figure 6.62 shows the measured full-load efficiencies for a variety of
frequency requests, M. These numbers are generally consistent with expected results,
though they tend to fall off at higher throughput requests. This is attributed to the
higher-than-expected battery voltage, V bat = 5.0 V, necessary to allow the 89 MHz and
100 MHz operating points 3 , and to the additional series resistance of the 68LDCC
package and through-hole socket.
Figure 6.63 shows the mechanisms of power dissipation for various loads at
V bat = 3.3 V, V dd = 1.47 V, and f VCO = 25 MHz. The recorded efficiencies are 87%,
85%, and 74% for 22 mA, 11 mA, and 1 mA loads. Power train dissipation, which
includes losses in the power FETs, package, and all external filter elements, dominates
converter losses, even at light load. The VCO receiver and frequency detector are the
3. All other efficiency data is taken with Vbat = 4.0 V.

Sources of Dissipation, fVCO = 25 MHz, Vbat = 3.3 V, Vdd = 1.47 V

300
250 Digital at Vdd
Power Dissipation [uW]

Digital at Vbat
200 Analog at Vbat
150
Idd = 1 mA Idd = 11 mA Idd = 22 mA
100
50
0
1 2 3
40
Power train
Power Dissipation [mW]
30
Idd = 11 mA Idd = 22 mA
20
10
Idd = 1 mA
0
1 2 3
Fig. 6.63: Mechanisms of dissipation versus load at 25 MHz and 1.47 V.
largest contributors to controller dissipation at light load. Analog power, dominated by
the NMOS off comparator, is the largest dissipater in the controller at heavy load. All
power measurements correlate well with expected results.
6.3.10.4 Synchronous Rectifier Control
Figure 6.64 shows the i L , v gn , and v x waveforms for a single PFM pulse at V bat
= 3.3 V, f VCO = 24 MHz. The DC value of V dd is 1.47 V. Figure 6.65 shows detail
around the NMOS power FET turn-off. Here, the power NMOS is turned off at i L < 2
mA, well within the error budget specified in Section 6.3.6.3, and introducing
negligible LI ε 2 loss.
6.3.10.5 Low Swing I/O Transceiver
The low-swing VCO transmitter failed on the processor test chip. The low-
swing signal is expected to reach 0 V and 200 mV logic levels, but in Figure 6.66 is
iL
vgn
vx
Fig. 6.64: Successful NMOS zero-current turn-off. Vbat = 3.3 V, Vdd = 1.47 V.
iL
vgn
vx
Fig. 6.65: Zoom-in of a successful NMOS zero-current turn-off. Vbat = 3.3 V, Vdd = 1.47 V.
Vdd
Low-swing
fVCO
Full-swing
fVCO
Fig. 6.66: Failed low-swing VCO output.
seen to be corrupted by noise, and to swing only between ± 50 mV . Since the low-
voltage f VCO never reaches the 100 mV reference voltage level, it cannot be
successfully received by the dynamic DC-DC converter. As a result, the full-swing
VCO output is transmitted on the test board, increasing the effective load on the
converter.
6.3.11 Conclusion
The dynamic DC-DC converter prototype IC has been successfully
demonstrated as a dynamic voltage scaling enabler. Compared with the previous work
summarized in Chapter 5, it provides wider dynamic range, comparable full-load
efficiency, improved light-load efficiency, and a four-fold to forty-fold improvement in
tracking metrics.
6.4 A ZVS PWM DC-DC Converter 219
6.4 A ZVS PWM DC-DC Converter
In this section, the design techniques of Chapter 4 are applied to the 6 V to 1.5
V, 500 mA buck converter presented in [Stratakos94]. The chip was fabricated in an
effort to validate many of these design techniques, and to demonstrate the viability of
zero-voltage switching (ZVS) with adaptive dead-time control (ADTC).
Figure 6.67 shows a block diagram of the chip. The IC is operated as an open-
loop continuous conduction mode buck converter, with pulse-width modulation
commanded via an external potentiometer coupled to the on-chip oscillator. Zero-
voltage switching transitions are guaranteed from zero to full load through the
adjustable dead-time control blocks, labelled τ DHL and τ DLH . Power transistors and
drivers are designed to minimize total power transistor losses; in this case, gate and
conduction losses only, as ZVS eliminates all other switching losses.
6.4.1 Prototype Description
The power train of the low-voltage buck circuit, with device sizes and external
component values, is shown in Figure 6.68. All active devices are integrated on a single
die and fabricated in a standard 1.2 µm single-poly double-metal CMOS process. The
Vbat = 6 V
driver
1 MHz
τDHL vgp iL
25% duty
osc vx Vo = 1.5 V
PWM L
driver
τDLH vgn Cx C LOAD
Fig. 6.67: Block diagram of the 6 V to 1.5 V, 500 mA prototype buck converter.
+
vgp
10.2 cm
-------------------
0.9 µm
675 nH
6V
+
vgn
10.5 cm
------------------- 4 nF 20 µF 1.5 V
0.9 µm
- -
Fig. 6.68: Power train circuit schematic.
circuit exhibits nearly ideal ZVS using an adjustable dead-time control scheme similar
to that described in Chapter 4.
Figure 6.69 shows the ideal periodic steady-state waveforms. The inverter
output node voltage, v x , is quasi-square with a nominal duty cycle, D = V o ⁄ V bat , of
25%, and an operating frequency of f s = 1 MHz which allows a compact, yet highly
efficient converter. The inductor current reverses to allow ZVS transitions of both
6V 1 µs
vx
0
0.5 A 1.66 A
iL 0
6V
vgp
0
6V
vgn
0
100 ns 25 ns
Fig. 6.69: Periodic steady-state waveforms.

power transistors, eliminating the loss associated with Miller charge and all stray
capacitance attached to v x .
6.4.1.1 External Component Selection
Because the inverter node transition intervals are designed to be small relative
to the switching period, i L is assumed triangular with peak negative and positive values
I o – ∆I ⁄ 2 and I o + ∆I ⁄ 2 which are constant over the entire dead-time. The ratio of
inverter node transition times is given by the ratio of currents available for each
commutation:
τ xLH ∆I ⁄ 2 + I
- = -----------------------o-
----------- (Eq 6-36)
τ xHL ∆I ⁄ 2 – I o
and approaches unity for large inductor current ripple. In (Eq 6-36), τ x indicates an
inverter node transition time, with subscripts LH and HL denoting low-to-high and
high-to-low transitions, respectively, I o is the average load current, and ∆I is the peak-
to-peak inductor current ripple. Choosing a maximum asymmetry in the transition
intervals of τ xLH ⁄ τ xHL = 4 at full load results in a minimum zero-to-peak inductor
current ripple of
∆I 5
------ = --- ⋅ I o = 833.3 mA (Eq 6-37)
2 3
and, from (Eq 3-2), requires a filter inductance of
Vo ⋅ ( 1 – D )
L = ----------------------------- = 675 nH (Eq 6-38)
f s ⋅ ∆I
Allowing for a 1% peak-to-peak AC output voltage ripple, according to (Eq 3-3)

Vo ⋅ ( 1 – D )
C = --------------------------------- = 13.9 µF (Eq 6-39)
2
8 ⋅ L ⋅ ∆V ⋅ f s
and C = 20 µF is selected.
To slow the inverter node transitions, additional snubber capacitance is added
at v x . The total capacitance required to achieve τ xLH = 0.1T s = 100 ns is
( ∆I ⁄ 2 – I o ) ⋅ τ xLH
C x = --------------------------------------------- = 5.6 nF (Eq 6-40)
V bat
where C x includes the snubber and all parasitic capacitance at v x . C x = 4 nF is chosen as
a reasonable value.
6.4.1.2 Adaptive Dead-Time Control
Adaptive dead-time control, introduced in Section 4.2.3, is implemented using
on-chip one-shots (the τ DLH and τ DHL blocks in Figure 6.67). External potentiometers
allow manual trimming of these delays to estimate the power savings effected by ZVS.
Figure 6.70 shows two measured non-ideal ZVS high-to-low inverter node
transitions. In Figure 6.70a, τ xHL > τ DHL , so that the NMOS turns on early, discharging
C x through its resistive channel and introducing C x V bat 2 loss. In steady-state, if both
power transistors fully (dis)charge C x over the full potential, V bat , nearly 200 mW of
additional power dissipation is introduced. In Figure 6.70b, τ xHL < τ DHL , so that the
NMOS turns on late, inducing greater than 30 ns of body diode conduction and reverse
recovery loss. With 30 ns of high-side and low-side body diode conduction each cycle,
the resulting losses can be in excess of 35 mW.

A nearly ideal ZVS high-to-low inverter node transition is shown in Figure
6.71. Here, the NMOS device is turned on approximately when v x = 0, introducing little
to no switching loss, and no body diode conduction.
6.4.1.3 FET Sizing and Gate-Drive Design
The power transistors are sized according to (Eq 4-11) to minimize their total
losses in periodic steady-state at full load. The minimum effective channel length, L eff
= 0.6 µm, is used. Device parameters R 0 and Q g0 = E g0 ⁄ V bat , which represent the
(a) (b)
Fig. 6.70: Non-ideal ZVS transitions: (a) The NMOS is turned on early. (b) The NMOS is turned
on late. The upper trace is vgn, the lower trace is vx, the vertical scale is 2 V/div, and the horizontal
scale is 20 ns/div.
Fig. 6.71: Ideal ZVS high-to-low inverter node transition. The upper trace is vgn, the lower trace is
vx, the vertical scale is 2 V/div, and the horizontal scale is 20 ns/div.
effective channel resistance and gate charge of a minimum gate-width device, are found
at V bat = 6 V by interpolating results obtained from circuit simulations performed on
extracted layout of large geometry FETs to W 0 = 0.6 µm, the minimum feature size in
the 1.2 µm process. Plugging C g0 = Q g0 ⁄ V bat and all necessary application- and
technology-specific parameters into (Eq 4-38), a first-order estimate to E g0 is made.
Approximate power transistor gate-widths are found by substituting this estimate and
the interpolated value of R0 into (Eq 4-11).
A prediction of the gate-drive design is effected through selection of the
tapering factor between successive inverters, u, and the number of inverters in the
chain, N, with (Eq 4-32) and (Eq 4-33). Iteration using circuit simulation on extracted
layout is beneficial to refine the design. From (Eq 4-12), total FET losses at full load
can be estimated. The design is summarized in Table 6.8.
Table 6.8: Power FET and gate-drive design summary.
PMOS NMOS
R0 23.7 kΩ 6.2 kΩ
Qg0 8.6 fC 9.7 fC
Eg0 58.7 fJ 68.8 fJ
Gate width, W 10.2 cm 10.6 cm
Buffering, u 5.6 5.2
Buffering, N 4 4
Estimated Loss 2.7% 3.2%
The circuit as presented in [Stratakos94] uses the full battery input voltage to
drive the gates of the power transistors. To gain a modest improvement in efficiency,
the reduced-swing gate-drive implementation of Section 4.2.5.6 may be used to
bootstrap the gate-drive from the 1.5 V output of the converter. With V g = Vo = 1.5 V,
total FET losses may be reduced from 5.9% to roughly 4% at full load, but at the
PMOS
τD control
oscillator
gate-drive
NMOS
Fig. 6.72: Chip photograph. Die size = 4.2 mm x 4.2 mm.
expense of considerable silicon area − the total gate-width would be increased by a
factor greater than ten.
The prototype IC (Figure 6.72) was fabricated in a standard 1.2 µm CMOS
process through the MOSIS program. The circuit successfully delivers 750 mW at 1.5 V
from a 6 V supply. Figure 6.73 shows the measured steady-state v gp , v gn, i L , and v x
waveforms at full load. Zero-voltage switched high-to-low and low-to-high transitions
can be observed.
Table 2 reports the measured sources of full-load dissipation. While power
transistor gate and conduction losses are balanced and predicted well by theory and
simulation, the overall measured efficiency of 79% is substantially lower than
anticipated. This can be attributed to several factors. First, due to an undetected layout
error in the one-shots, dead-time adjustment is implemented on the board. Because of
the associated increase in capacitive parasitics over the monolithic implementation,
comparatively large static currents are required to obtain the desired dead-times. Thus,
the power consumption of the ADTC circuitry is greater than an order of magnitude
larger than anticipated, comprising nearly 30% of the overall loss. Second, throughout
the design, efficiency is traded for testability: a number of intermediate signals are
vgn
vgp
iL
vx
Fig. 6.73: Measured steady-state waveforms: vgn, vgp, iL, vx (top to bottom). The horizontal scale
is 200 ns/div. The vertical scale is 2 V/div for the voltage waveforms, and 1 A/div for the inductor
current waveform.
brought off-chip at the expense of additional switching capacitance, resulting in a
severe penalty in dynamic power consumption. For example, the dissipation of the
oscillator is increased by a factor of three in order to enhance its testability. Finally, a
major component of loss is accredited to the package and test board. The IC is
assembled in a 64-pin PGA package, and socketed and wire-wrapped to a prototype
board. Series resistance in the V bat , ground, and v x lines contribute a total of 47.3 mW
of loss (28% of the total loss), and the stray inductance in the loop formed by the input
decoupling capacitor and the power transistors contribute an additional 20 mW of loss
(10% of the total loss). Dissipation from these mechanisms can be significantly reduced
by using a smaller surface mount package soldered directly to a printed circuit board.
Table 6.9: Sources of dissipation.
PMOS NMOS
Gate-drive loss 11.2 mW 13.9 mW
Channel conduction loss 10.1 mW 14.0 mW

Other conduction lossa 5.1 mWb 42.2 mWb
Total loss 3.5% 9.3%
Stray inductancea 20 mWb

Series resistance in L 16.9 mW
Table 6.9: Sources of dissipation.
PMOS NMOS
Output capacitor ESR 2.3 mW
Input capacitor ESR < 1 mW

Oscillator (including pins) 6.2 mW
ADTC (off-chip) 48.4 mW
a. Accredited to the package, test socket, and test board.

b. Estimated result.
The results measured on the prototype indicate that in this circuit, on-chip
losses (including those in the power transistors, drivers and control circuits) can be kept
below 8% at full load. The design approach presented in Chapter 4 is evidently viable
for realizing a high efficiency and compact power converter for portable battery-
operated applications. This circuit requires only one custom IC, three small ceramic
chip capacitors, and one small inductor, and is capable of achieving efficiencies above
90%.
7.1 Conclusions 228
Chapter 7
Conclusions
7.1 Conclusions
High-efficiency low-voltage DC-DC conversion has been shown to be a
critical low-power enabling technology. Recent innovations in low-power digital
CMOS design have assumed that the supply voltage is a free variable and can be set to
any arbitrarily low level with little penalty. This thesis has introduced the DC-DC
converter design techniques which make this assumption more viable.
Voltage scaling for low-power throughput-constrained digital CMOS signal
processors, enabled by small and highly integrated DC-DC converters custom designed
for their individual loads, can provide up to an order of magnitude reduction in overall
power dissipation compared to more conventional 3.3 V designs. Aggressive voltage
scaling applied to ultra-low-swing bus transmitters is used to reduce the power of high-
speed inter-chip I/O by up to two orders of magnitude. This is enabled by a 200 mV
output DC-DC converter. Dynamic voltage scaling (DVS) is proposed to trade general-
purpose processor performance for energy-efficiency at run-time, yielding as much as
an order of magnitude improvement in battery run-time. Special design considerations

7.2 Summary of Research Contributions 229
for the key low-power enabler, called the dynamic DC-DC converter, have been
introduced which increase its utility in a general-purpose processing system.
A number of power system, individual control system, and circuit-level design
techniques have been presented to reduce the size, cost, and energy dissipation of low-
voltage DC-DC converters. Measured results on three prototype DC-DC converter ICs
have successfully demonstrated these design techniques. The approach presented in this
thesis is evidently viable for realizing compact and highly efficient DC-DC converters
for use as low-voltage and low-power enablers in portable electronic systems.
7.2 Summary of Research Contributions
In this research, DC-DC converters have been designed and implemented as
low-voltage and low-power enablers. This has included the development and
demonstration of an array of system- and circuit-level design techniques to increase the
utility of DC-DC converters in nearly any portable electronic application. Several key
research contributions are highlighted below:
• Developed a series of design techniques which decrease the size, cost, and energy
dissipation of low-voltage DC-DC converters. These include new ideas, such as:
Minimum inductor design; adaptive dead-time control; dynamic transistor
sizing; optimal gate-drive strategies; and ultra-low-power digital PWM control;
and the new application of existing ideas: High-frequency operation;
synchronous rectification; soft-switching; and others.
• Demonstrated the concept of adaptive dead-time control with a 6 V to 1.5 V, 500
mA prototype DC-DC converter.
• Successfully demonstrated a high-efficiency DC-DC converter with the lowest
reported output voltage and power levels: Greater than 70% efficiency at 0.2 V
and less than 1 mW.

7.3 Future Research Directions 230
• Developed a new class of converter, called a dynamic DC-DC converter, which
enables as much as an order of magnitude battery run-time improvement for a
general-purpose processor system. This included the identification of the key
system- and circuit-level design considerations, and a successful prototype
build.
7.3 Future Research Directions
This thesis has provided the groundwork for a variety of continuing research
directions. Research might focus on improvements in the design of individual DC-DC
converters, or on the portable electronic systems whose battery run-time they are
intended to improve.
Higher levels of functional integration might be pursued. Recent advances in
microfabricated magnetic and capacitive components can be leveraged to introduce a
fully integrated DC-DC converter module or IC. Integration of several converters on a
single IC, or integration of the DC-DC converter together with its individual digital
CMOS load would offer the smallest size power delivery system. Design of DC-DC
converters as drop-in macros, similar to DSP cores, could be pursued as the next true
low-power enabling technology. Research in computer-aided design and synthesis of
these macros is a necessary next step and requires pioneering work.
Continued investigation of the mechanisms of power dissipation in portable
electronic systems is sure to uncover a variety of new applications for low-power
design enabled by DC-DC converters, particularly dynamic DC-DC converters.

231
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1

High-Efficiency Low-Voltage DC-DC Conversion for Portable

Doctor of Philosophy in Engineering-Electrical Engineering

University of California, Berkeley

Professor Robert W. Brodersen, Chair

Motivated by emerging portable applications that demand ultra-low-power

hardware to maximize battery run-time, high-efficiency low-voltage DC-DC conversion

is presented as a key low-power enabler. Recent innovations in low-power digital

The primary design challenges to high-efficiency low-voltage DC-DC

requirements imposed by the portable environment. Design equations and closed-form

energy efficiency are the primary design objectives.

low-power enabling capabilities of DC-DC converters in portable applications. Voltage

scaling for low-power throughput-constrained digital signal processing is reviewed and

is shown to provide up to an order of magnitude power reduction compared to existing

3.3 V standards when enabled by high-efficiency low-voltage DC-DC conversion. A

new ultra-low-swing I/O strategy, enabled by an ultra-low-voltage and low-power DC-

DC converter, is used to reduce the power of high-speed inter-chip communication by

greater than two orders of magnitude. Dynamic voltage scaling is proposed to

dynamically trade general-purpose processor throughput for energy-efficiency, yielding

up to an order of magnitude improvement in the average energy per operation of the

introduced in this thesis.

Robert W. Brodersen, Chairman of Committee

Chapter 2: DC-DC Conversion as a Low-Power Enabler ...........................................10

Chapter 3: DC-DC Converter Fundamentals ...............................................................42

3.2 DC-DC Requirements in Portable Systems .................................................................45

Chapter 4: DC-DC Design Techniques for Portable Applications..............................79

4.3 System-Level Considerations ....................................................................................116

Chapter 5: Design Considerations for Dynamic DC-DC Converters .......................124

Chapter 6: Prototype DC-DC Converters ...................................................................147

6.3.3 External Component Selection..............................................................................................186

Chapter 7: Conclusions .................................................................................................228

people, I am particularly grateful.

always be my best friend.

I thank my parents for giving me unconditional love, guidance, and support.

creativity I have came from Mom!

home away from Berkeley, and a comfortable spot on the couch.

uncanny imitation (except one) a dozen times.

Sekhar Narayanaswami and I probably would have graduated a year earlier if

physical comic − he’s second only to Chris.

brown belt with black shoes again.

The atmosphere in 550 was ideal. It was populated almost entirely by

my development as an IC designer. Andy was also an inspirational teacher, cunning

satirist, and outstanding cook.

a lot of fun traveling together in Taiwan.

dinner?). He taught me to design power circuits from a system and IC design

perspective. It’s what allowed me to differentiate my work.

While Bob was my advisor, Seth Sanders was my informal co-advisor. He

integral member of your research group.

Current trends in consumer electronics demand progressively lower-voltage

require ultra-low-power circuitry to maximize battery run-time. Perhaps the most

effective way to reduce power dissipation and maintain computational throughput in

style, circuit, and other technology optimizations [Chandrakasan94b]. Such

optimizations can be performed at design time, where a well-known computational

throughput requirement can be met at some minimum voltage [Chandrakasan92], or at

efficiency [Burd95], [Chandrakasan96], [Wei96], [Kuroda98]. In either case, this low-

efficiency low-voltage DC-DC conversion is required to efficiently generate each low-

voltage supply from a single battery source.

Consider, for example, the multimedia Infopad terminal [Brodersen92],

[Sheng92], [Chandrakasan93], [Truman98]. The custom hardware in the InfoPad

O chipset [Chandrakasan94a], is designed to operate at each component’s optimum

supply voltage to minimize its power consumption. Thus, a number of low-voltage

minimum operating power independent of the cell voltage, substantially extending