S ® Training Manual

Direct View
Television
DX-1A Chassis
Models: KV-32XBR400
KV-36XBR400

Circuit Description and Troubleshooting

Course: DTV-02
 Table of Contents
Introduction 2 Testing 35

DTV Converter Boxes 3 Horizontal Drive / H Pincushion Correction /

USA Analog Transmission Format 3 Filament Voltage 37
USA Digital Transmission Formats 5 Basic Horizontal Drive Circuit 37

Digital TV (DTV) Converter Boxes 5 PMW Circuit 37

Filament Voltage 39
New Features 9
G2 Circuit 41
Overall Block 11
HV Converter Block 43
SD to HD Conversion Concept 15
Start Up 43
Video Block 21
Protection / Shutdown 43
Picture with Picture 27
HV Adjustment 43
Power ON Block 29 Testing 45
Power Supplies 29
Communications 47
Standby Power Supply 29
Dynamic Focus Block 51
Primary & Secondary Power Supplies 29
Static Focus Concept 51
Primary Power Supply 31
Dynamic Focus Concept 51
Start Up 31
Circuitry 51
Regulation 31 Adjustment 55
Testing 33 DQP Circuit Corner Focus Correction 57
Secondary Power Supply 35 Convergence Circuit 61
Start Up 35 Concept 61
Regulation 35 Circuitry 61
Adjustment 61 Appendix
Picture Tilt Correction 63 Service Mode Display i
Vertical Pincushion Correction Circuit 65 Digital Satellite System Converter Box ii

Concept 65 DTV Set Top Box iii

Adjustment 65 IEEE-1394 iv
DX-1A Chassis Assembly vii
Vertical Process 67
Board Replacement viii
Audio Block Diagram 71
HV Adj. check Bulletin 492 ixi
Features 71
Signal Path 71
Self Diagnostic Block 73
Self Diagnostic Circuit 75
 1

NOTES
 Circuitry Information
Introduction
The power consumption and self-diagnostics remain the same as other
This model KV32XBR400 is a high resolution TV designed to bridge the Sony TVs. This set’s change to high-resolution video results in circuitry
gap between the current analog TV sets and the forthcoming high defini- changes to the video processing, horizontal frequency (fixed at 33.75kHz),
tion digital TV (HDTV) sets. This set can accept the current standard and high voltage generation.
resolution NTSC TV transmissions, DVD, VHS, and Camcorder video sig-
nals, convert them, and display them on a high-resolution TV screen. An Power Consumption at 120Vac
external set top converter box is necessary to receive Digital TV pro- Snow Dark screen/video 1 Surge
grams.
1.2 A 1.1 A 6 A (degaussing)
Related Models
DX-1A TV Chassis Models
General Servicing Information
Model Screen size Aspect MSRP
Ratio Item Location Comments
KV32XBR400 32 diagonal 4:3 $1999.99 Self Circuits on A & D Standby/Timer LED
Diagnostics boards. Indicator on blinks to ID problem
KV36XBR400 36 diagonal 4:3 $2499.99
front panel. area.
Higher Resolution Inputs
Filament From 7V, A Bd The CRT filament
This TV can also accept standard resolution 480p or high resolution 1080i Voltage (Primary PS) and HOT voltage comes from 2
video signal formats from an external HDTV, satellite, or cable converter transformer, D Bd. sources.
box as component video (Y, Pb, Pr) inputs. These 480p and 1080i sig- High Voltage D board near flyback AFC signal from HOT
nals can have a wide 16:9 aspect ratio. If they do, the display will be in Converter turns ON HV Converter.
letterbox format with black above and below the picture on the 4:3 aspect
G2 (Screen On the CRT board Adjustment is in the
ratio picture tube of these TV sets.
adjustment) board replacement
Only the Digital TV’s 720p resolution video format cannot be displayed on guide (appendix).
this set. The picture will not be synchronized. Focus Control On the FBT Adjust for sharp picture
KV32XBR400 / KV36XBR400Inputs center and sides
Name Format Source Filament Voltage - This CRT voltage comes from two sources:
RF NTSC VHF, UHF, Cable • Unregulated 7V supply from the Primary Power Supply on the A board
Video 1-4 + S or Composite video: Video tape recorder, (used as a preheat).
Stereo Standard resolution 480 camcorder, DVD • The HOT (horizontal output transformer) after a 6Vdc regulator on the
jacks interlaced lines (480i). player, TiVO D board (main filament voltage supply).
recorder
High Voltage Generation - An independent HV oscillator circuit with a
Video 5-6 + Component video: Standard DTV, Satellite, or
Stereo Resolution 480i, 480p or Cable Converter box special high frequency flyback transformer regulates the HV to 31.5kV.
Jacks High Resolution 1080i format The HV converter stage is turned on only after the Horizontal drive signal
Control S Sony Audio Equipment from the HOT is detected.

2
 3
DTV Converter Boxes
In order to compare converter box specifications you need to understand
how resolution is measured in the interlaced and progressive scan meth-
ods. With this information you can also determine which one of the 18
digital formats offers better resolution.
Resolution
The two most popular methods of measuring picture resolution are in
pixels (dots) or in lines. Incremental dots called pixels are often associ-
ated with monitors. Lines of resolution is a measurement for TVs. In the
monitor specifications, the number of vertical pixels is listed first. In the
TV specifications, the number of horizontal lines is listed first. For these
examples of specifications, a high-resolution monitor and (digital) TV stan-
dard were chosen:
picture is not seen and the picture is normally over-scanned (larger than
the TV screen). Therefore, the TV resolution is said to be “480” (horizon-
tal) lines instead of the transmitted 525 lines.
USA Analog Transmission Format
Interlaced and Progressive Scanning
In the NTSC television transmission format a complete picture (frame)
consists of two pictures (fields) interlaced together. Each half picture is a
field of 262.5 scanned lines. Therefore a complete picture is 262.5 x 2 =
525 lines. The two scanned fields are interlaced so the second field of
262.5 lines fits in-between the first field.
Interlaced Scan

Monitor 1024 X
Spec
1800 Field 1 + Field 2 = Frame
If a picture is not interlaced, it is a progressive scan image (not NTSC
1024 x 1800 pixels format). This means the entire picture frame is presented in the first scan
and a second picture is presented in the second scan.
Progressive Scan
TV
Spec X

1080 x 1920 lines
Although the semantics are different (vertical pixels/horizontal lines), the
first number in both specifications is the maximum number of black to
white transitions that can occur as you count from the top of the screen to
the bottom.
In the current NTSC (National Television Standards Committee) TV trans-
mission standard, 525 horizontal lines are transmitted but only about 480
lines are visible. This is because the vertical blanking area above the
Field 1 =
Frame
30 or 60 Frames?
In the NTSC standard the first field takes 1/60 second to scan a screen of
262.5 lines. Then a slightly smaller vertical sync pulse in the second field
is created and the second picture field is shifted lower than the first to fit
in-between. The second field also takes 1/60 sec., completing the entire
picture frame in 1/60 + 1/60 = 2/60 sec = 1/30 sec.
 DTV Set Top Converter Boxes (as of July, 2000)
Video Output Audio Output
RF Inputs Standard Resolution High Resolution Analog Digital

Ch 1-125 Cable DTV *

Format (# Horiz lines)

Ch 2-69 Analog TV

Small dish Satellite

Ch 1-99 Digital TV

Comp Video

RGB,H,V **
RF(Ch 3/4)

IEEE 1394
Y, Pr, Pb
S Video

Optical
L&R

Coax
Mfg. Model
RCA DTC-100 X X X X X X X VGA 1080i/540p X X
Panasonic TU-HDST50 X X ? X X X 720p X X
TU-HDS20 X X X X ? X X X BNC ? X X
Pioneer SH-DO7 X ? X 1080i *** X X X
SH-D505 X X ? X X X BNC 1080i/ X X X
720p/480p
Mitsubishi SR-HD400 X X X X X X X X ? X X
SR-HD500 X X X X X X X X ? X X
Sony DTR-HD1 X X X phono 1080i X X
SAT-HD100 X X X X X X VGA 1080i/480p X X
Sharp TUDTV1000 X X X X X VGA/ 1080i/480p X X X
BNC
Proscan PSHD105 X ? ? X X X X VGA 1080i/540p X X
Samsung SIRT100 X ? ? X X X X ? 1080i/480p X X

* DTV must be 8VSB modulation (like terrestrial ATSC DTV transmissions)

X = Yes ** VGA = computer monitor jack (15 pin D type)
? = insufficient information BNC = BNC connectors, one for each of the signals
blank = No *** Connection to Pioneer model PRO-700HD TV only.

4
 5
30I Picture Format USA Digital Transmission Formats
There are 18 digital transmission formats approved by the ATSC (Ad-
= 2/60
1/60 sec. 1/60 sec. vanced Television Standards Committee) in the USA. The first six offer
+ second or
Field 1 Field 2 HD (high definition/resolution) signals in a 16x9 aspect ratio. The remain-
1/30
ing 12 formats are SD (standard definition) signals in progressive (p) or
The NTSC format is commonly written as “30i” picture format because it interlaced (i) scan. Note that the 480p signal can be a 4:3 or 16:9 aspect
takes 1/30 of a second to complete an interlaced picture. ratio transmission.
Aspect Ratio 18 Digital Transmission Formats
Although the first pictures were round, later TV pictures adopted a rectan- Resolution Aspect Frame Resolution Aspect Frame
gular shape. The aspect ratio of these pictures is the same as they are Ratio Ratio
today, 4 x 3 ratio. 1. 1080x1920 16:9 30 i 10. 480x 704 16:9 24 p
2. 16:9 30 p 11. 4:3 60 p
3 9
3. 16:9 24 p 12. 4:3 30 i
4 16 4. 720 x 1280 16:9 60 p 13. 4:3 30 p
Movie theaters show films in a wider 16x9 aspect ratio. This 16x9 picture 5. 16:9 30 p 14. 4:3 24 p
is also the way most films are shot. To present the original 16x9 picture
on a 4x3 TV screen, one of two common methods is adopted to fit the 6. 16:9 24 p 15. 480x 640 4:3 60 p
picture: 7. 480x 704 16:9 60 p 16. 4:3 30 i
In method 1, the 16x9 picture is cropped or cut off at the left and right. The 8. 16:9 30 i 17. 4:3 30 p
main action part of the picture (usually the center or near center) is the 9. 16:9 30 p 18. 4:3 24 p
only part transmitted.
Shaded A standard definition transmission contains less data, permitting space
Center
Method 1 area for another digital video stream to coexist on the same frequency (chan-
of 16 x 9
Cropping Cropped/ nel). Therefore, a station can have more than one program stream on a
picture
removed digital channel. The maximum number of programs is six.
In method 2, the 16x9 picture is shrunken and placed on the TV screen.
The entire picture is seen but with black areas above and below the pic- Digital TV (DTV) Converter Boxes
ture. This method of viewing the entire 16x9 picture on a 4x3 set is called TV broadcasters are transmitting their analog signals on one channel and
a Letterbox picture. Letterbox pictures can be selected on some DVD their DTV signals on another. A list of their analog and digital channel
players and TV sets from the menu if the DVD or TV transmissions offer assignments by state is located at www.transmitter.com.
it. To receive a DTV station on an analog TV, a set top converter box is
Entire used. The box receives digital RF and outputs analog composite video to
Method 2
16x9 the TV. The boxes can also output higher resolution video signals to a
Letterbox
Picture high-resolution analog TV. These cable boxes are flexible at their input
and outputs:
RF inputs:
Channels 1-99 Digital TV
The TV converter boxes listed in the chart all decode DTV signals from off
the air (terrestrial) in the USA and Canada. These TV stations conform to
the DTV ATSC format that approves an 8VSB modulation method. The
new digital channel numbers are frequencies within the current analog
Channels 2-69.
Ch 1-125 Cable DTV
At this time some cable TV companies are providing DTV service using
8VSB modulation and other cable companies sell DTV service using QAM
modulation. The 8VSB modulation means this method is probably the
same as the off the air ATSC (DTV) signal. This means if the DTV con-
verter boxes can receive the cable band, they can decode the cable DTV
signal. Cable companies using a QAM (Quadrature Amplitude) Modula-
tion method require their DTV boxes for processing.
950-1.45GHz Satellite
In competition with cable companies are Direct Broadcast System (DBS)
companies that provide satellite TV channels. The larger analog signal
DBS dishes that operate on the ”C” band were not as popular as the
smaller “Ku” band digital signal dishes. A satellite manufacture can either
provide the TV service directly to the consumer, rent transponders (space)
to other providers, or both. Some of the larger companies are:
Satellite Manufactures Providers
GM Hughes Electronics
EchoStar/Dish Network (HD 1080i) Direct TV
DBSC (Direct Broadcast Satellite Corp) PrimeStar
Direct Sat
Tempo
ACC (advanced Communications Corp)
Satellite reception is vulnerable to rain scattering the signal and the sun’s
microwave energy overpowering the satellite signal. The solar outages
may occur only for minutes during the time span of a week or two during
the spring and fall equinoxes. At these times the sun is behind the target
satellite adding noise to the signal.
6
A few converter boxes can receive digital satellite signals. This combina-
tion of DTV and satellite decoding in one box is feasible because the
decoding circuitry is similar. It is uncertain if these converter boxes can
decode the new satellite high definition DTV signals.
Video Outputs
The converter boxes output standard resolution and high-resolution sig-
nals. All the boxes can down convert a 1080, 720 or 480 line input signal
into a standard resolution 480i picture for an analog TV. This standard
resolution output comes from the S or composite video jacks of the box.
For the higher resolution TVs that are coming out now, there is a compo-
nent (Y, Pr, Pb) and/or RGB output from the box. The RGB +sync output
could be five individual BNC jacks or a single VGA connector, such as the
ones found on the back of a home computer for its monitor.
After the correct mechanical connection is made, the signal format from
the box must match that of the high resolution TV. The box’s output
signal formats are menu selectable for box to TV compatibility. For ex-
ample if the TV accepts 1080i signal format, the box’s output must corre-
spond with the same output signal format.
If a 1080 format DTV signal is received, the box will convert it from an RF
signal, unscramble it, separate the audio, video and data, and then
uncompress the audio and video. The video will be changed into compo-
nent video or RGB voltages that are input to the TV. The sync is on the Y
line in the component video signal.
If a standard resolution 480 format DTV signal is received, the same sig-
nal processing occurs but there is an additional scan converter to double
the information before leaving as a 1080i format signal for the hich scan
TV.
Audio Outputs
All the converter boxes have composite video output and corresponding
analog audio L&R channel outputs. Some boxes have digital optical and/
or coax outputs for a Dolby  AC-3  decoder (often in a receiver). One
converter box has an IEEE 1394 output for decoding the signal in a SVHS
 7
recorder. The IEEE-1394 format is also called i.LINK, or Firewire ”
because of the convenience or high speed. Customarily, both video and
audio is sent on this 4-wire cable. More about the IEEE-1394 format is
found in the appendix of this book.

Dolby is a registered trademark of Dolby laboratories.

Fire Wire is a trademark of Apple Computer Inc.
i.LINK is a trademark of Sony.
NOTES

8
 9
Parent Menu
New Features
This allows the owner to block TV programs according to their content.
Entering the owner’s four-number password enables viewing of the blocked
FD Wega Picture Tube programs. The owner’s password can be cleared with the master pass-
The Sony flat screen picture tube is a full flat screen inside and outside. word 4357 (“HELP”). The owner’s password can also be reset from the
service mode by pressing 8, then enter.
Sony Glass Non-Sony
screen Picture Tube
FD Set Up Menu - 16:9 Enhanced
Electron beam
A 480p input signal can be in 4:3 or 16:9 video format.
Favorite Channel Preview
Pressing the Favorites remote button reduces the main picture and dis-
plays a small picture of another (favorite) station. As you move the joy- Letterbox Black
picture
16:9 Pix border
stick down the list of numbers, the preview picture changes to that station.
Select that station by pressing enter.

Favorite Channel Display The wide 16:9 video format produces a picture on a 4:3 picture tube that
is too tall. From the Auto/ON/OFF selections of the set up menu, choose
16:9 Enhanced = ON to reduce the vertical size of the picture so the
Preview picture is the correct aspect ratio.
Main Pix The “Auto” selection reduces the picture size if there is an ID-1 signal in
the vertical blanking area of the input signal. The ID-1 signal identifies the
video signal as 4:3 or 16:9 format. Sony 16:9 camcorders insert the ID-1
Channel Numbers information into the video during recording.

New Picture Mode = Pro

The basic video modes are Vivid for use in bright daylight, Standard for
reduced brightness in the home, and Movie for evenings. The Pro video
mode is new. This mode darkens the picture and centers its dark to bright
operating range for the widest dynamic picture swing. This mode is meant
for pro movie watchers in a darkened room where the subtle dark to gray
changes are made evident. The video settings (picture, brightness, color,
etc) can be changed in any mode.
Video Menu - DRC-MF
Select an Interlace or Progressive mode display from the Video menu
under “DRC-MF”. Interlace is selected when watching moving images.
The Progressive mode is selected only when many non-moving images
are displayed, such as text or a still photograph. Selecting the Progres-
sive mode stops the flickering that occurs in an interlaced picture when
the two interlaced fields are not exactly the same. This interlace/progres-
sive is not an option with a 1080i input
NOTES

10
 11

Overall Block V Pin

Top & bottom
lines bowed in
The only conventional block within this TV is the vertical block. The re- Distortion (exaggerated)
maining blocks are different because this TV is a high-resolution type with
a “Wega”® flat screen. Therefore, changes to the power supply, horizon-
tal frequency, convergence, focus, and video processing support the im- Horizontal Deflection
proved picture. The higher 33.75kHz horizontal frequency is made by IC201 and fed to
Power Supply the H Drive/Output stage on the D board. The output stage is fed regu-
The power supply is in three parts to divide the load on the boards: lated voltage from the +135V Secondary power supply via the PWM cir-
cuit of IC5002.
Power Supplies
The horizontal drive stage not only supplies the H Deflection yoke (H DY)
Board Purpose with scan voltage, but also supplies G2 and filament voltage for the CRT.
Standby A Outputs Standby 15V, 7V, & 5V. A regulated +200V is also output to supply the RGB output amplifiers on
Primary Power A Outputs Set 9V, Set 5V, & Set 3.3V to local the C board.
Supply parts on the A, B, & BD boards. Outputs Horizontal AFC pulses from this stage are needed by the convergence
Pri-Pre 15V to start the Secondary PS. and dynamic focus stages for sync. The AFC pulses are used to start the
Secondary D Outputs +200V, +135V, +24V (audio), Main HV Converter.
Power Supply 12V, Main 9V, & Main 5V to the D board. HV Converter
Regulated HV and focus voltage is made by the HV Converter stage. It
The Primary power supply starts the secondary supply using a Pri-Pre
uses +200V from the secondary power supply to run and AFC pulses
15V line. Once the Secondary power supply operates, Main 9V outputs
from the horizontal deflection stage to start.
to start the horizontal and vertical oscillators in Y/C CRT Drive IC201.
Horizontal Pincushion Correction
Vertical Deflection
To keep the lines at the left and right of the screen straight, an east/west
In some Sony TV sets, there is no V Drive output the Y/C IC until data and
(E/W) H pincushion correction signal is made in IC201. The E/W signal is
clock are input. Unlike these TV sets, this IC201’s vertical will output
used to modulate the PWM IC5002 that controls picture width. By chang-
when power is applied. The sync source is dependent upon whether
ing the width line-by-line, the left and right sides in the large picture can be
progressive, interlace or a sub picture is chosen. The vertical oscillator
straightened.
output is amplified by IC5004 on the “D” deflection board to drive the DY
deflection yoke.
Vertical Pincushion Correction
H Pin Sides bowed in
As the TV screen becomes larger, the yoke can not perfectly control the (exaggerated)
Distortion
beam at the screen perimeter. An additional coil on the top and bottom of
the CRT neck assembly is fed V Pin correction signal from IC201 and
IC5514. The additional coil eliminates any minor inward/outward bow at
the top and bottom of the picture.
 VID
TUNERS IC3303/ MAIN
IC3048
IC3408 9V
VIDEO 1-4 SW
DRC/MID IC3414 A BD.
SYNC SW +200V
480i 480p SYNC (HOT)
VIDEO 5-6
B BD. 1080i C BD.
IC201
Y/C RGB
H DRIVE = 33.75kHz CRT IC9001-3
E/W RGB CRT
CRT DRIVE
OUT CATHODES
FILAMENT VPIN
COIL ON IK
200V V DRIVE
Q5026-8, C BD. CRT
Q5035-6, NECK
Q5030 G2 IC5514 VTIM
IC5004 V STBY
H DRIVE V PIN (IC5513)
V OUT DY FOCUS 15V
H OUTPUT OUT STANDBY 7V
H 5V IC5501
100V DY HV
IC5511 NVM
VTIM IC5513, DF/DQP (D BD.)
IC5002 CY
IC5515 COILS
PWM IN IC701
CONV. IC707
DY MAIN
IC8002 NVM
+135V HV uCOM
AFC CONV. D6530

200V POWER
340VDC ON
SECONDARY SET VOLTAGES
P.S 9V
+ 15V
D BD. - PRIMARY 5V
PRE
P.S 3.3V
MAIN VOLTAGES 15V
12V,9V,5V,24V A BD.

OVERALL BLOCK 48DTV02 1273 19/2/00

12
 13
Convergence of the Three Beams High Resolution Input - Video inputs 5 and 6 are for Y, Pr and Pb compo-
The good news is that the complex convergence signal is made in one nent signals only. They can be standard (480i) or high resolution (480p or
IC5513 and the signal is amplified in the second IC5515. The output 1080i). The 480p signal is already high resolution at double the H freq so
signal drives a convergence yoke inside the main horizontal and vertical it need not go through the DRC circuit. It is switched directly into the MID
deflection yoke. The convergence stage affects the beams at the perim- circuit.
eter of the screen. The high-resolution 1080i picture is at the same horizontal frequency as
Dynamic Focus Correction the TV set (33.75kHz), so it does not go into the DRC or the MID circuit.
The 1080i signal is switched directly to the Y/C CRT Drive IC201 on the A
As a beam is deflected, the points of focus form a curve. The focus points board.
have to be moved to match the flat screen of the TV. A signal from DF
IC5511 modulates the DC focus voltage to prevent poor focus at the left Since the 1080i signal is a wide 16:9 ratio picture, it looks squeezed in on
and right sides of the screen. a 4:3 aspect ratio picture tube. To make the picture look correct, the
vertical can be reduced using a “16:9 enhanced” menu command. Verti-
Video Processing cal reduction can be automatically done if there is a code in the vertical
Standard Resolution Input – A standard resolution NTSC signal can be blanking area of the input signal called ID-1. This signal identifies the
selected from either tuner or any video input. However, this high resolu- aspect ratio of the picture.
tion TV runs at a different horizontal frequency of 33.75kHz. To accept a
standard NTSC signal (480i) that runs at 15,734 Hz, the video signal is
improved and the horizontal sync more than doubled.
The Digital Reality Creation Circuit (IC3303) analyzes each pixel of a line
to add another line. Therefore the DRC circuit doubles the number of
video lines of a standard NTSC signal. The DRC also doubles the hori-
zontal sync frequency before passing the signal onto the MID circuit on
the same board.
The Multi Image Driver (MID) Circuit (IC3408) stores the lines and out-
puts the signal based on a new horizontal frequency that matches the TV.
At the higher frequency, the picture finishes before the scan. Blank lines
are added as filler by this MID stage before leaving the board.
 VID
TUNERS IC3303/ MAIN
IC3048
IC3408 9V
VIDEO 1-4 SW
DRC/MID IC3414 A BD.
SYNC SW +200V
480i 480p SYNC (HOT)
VIDEO 5-6
B BD. 1080i C BD.
IC201
Y/C RGB
H DRIVE = 33.75kHz CRT IC9001-3
E/W RGB CRT
CRT DRIVE
OUT CATHODES
FILAMENT VPIN
COIL ON IK
200V V DRIVE
Q5026-8, C BD. CRT
Q5035-6, NECK
Q5030 G2 IC5514 VTIM
IC5004 V STBY
H DRIVE V PIN (IC5513)
V OUT DY FOCUS 15V
H OUTPUT OUT STANDBY 7V
H 5V IC5501
100V DY HV
IC5511 NVM
VTIM IC5513, DF/DQP (D BD.)
IC5002 CY
IC5515 COILS
PWM IN IC701
CONV. IC707
DY MAIN
IC8002 NVM
+135V HV uCOM
AFC CONV. D6530

200V POWER
340VDC ON
SECONDARY SET VOLTAGES
P.S 9V
+ 15V
D BD. - PRIMARY 5V
PRE
P.S 3.3V
MAIN VOLTAGES 15V
12V,9V,5V,24V A BD.

OVERALL BLOCK 48DTV02 1273 19/2/00

14

SD to HD Conversion Concept
This TV has features designed to bridge the gap between the current
analog sets and newer higher resolution digital TV sets. The KV32XBR400
TV is a high resolution set capable of receiving the current standard defi-
nition (SD) NTSC signal. The NTSC standard resolution of 480i lines is
upgraded to a 960i (interlaced) or 480p (progressive) line picture, to be
compatible with this TV. The user selects interlaced scan if there is mo-
tion in the picture or progressive scan if there is a still picture signal in
order to stop interlace flicker. A higher resolution (480p or 1080i) signal
that does not need to be upgraded can be input to video 5 or 6 for ad-
vanced placement in the video chain.
Interlaced or Progressive Scan
Most technical people do not know how many horizontal lines are present
on the screen in a single scan from the top of the screen to the bottom.
The confusion about the number of lines shown at one time relates to the
different interlace/progressive scan modes.
In the progressive scan mode the entire picture is presented in one scan
of the picture tube (left to right, top to bottom). In an interlaced scan the
entire picture consists of two fields so the picture is presented in two
scans of the picture tube. The second field is displaced from the first so
the lines fit in-between each other making the completed picture:
Field 1 Field 2
"6i" Interlaced Picture consisting of
alternating lines from fields 1 & 2
The resolution of the TV picture is measured in horizontal lines of a com-
plete picture followed by the letter for the type of scan (i or p). For ex-
ample, the NTSC signal contains 525 horizontal lines. The number of
viewable lines is reduced to 480 because of the time required for V & H
retrace, creating a blanking area above and below the picture. Therefore
the standard resolution NTSC signal displays a 480i picture. 480 is the
15
number of lines in the total picture. The i suffix identifies an interlaced
picture. Since the picture is interlaced, there is only half the number of
lines presented in a single scan. In this case, there are 240 lines dis-
played in a single scan. This is equivalent to a 240p picture that displays
240 lines in a single scan (480i is the same as 240p).
In a single scan
1
2
3
4
5
6
12i Interlaced scan 6p Progressive
=
picture is 6 lines per field scan picture
Similarly a 480p picture is like a 960i picture because both these pictures
present 480 horizontal lines per scan. This is important to understand as
the standard resolution NTSC picture is changed to a higher resolution in
the “DRC” video processing stage of this TV.
Standard Definition Video Input
The Tuner and Video 1-4 inputs accept only the NTSC 480i-line standard
definition signal identified by the 15.75kHz horizontal frequency. The 480i
input signal is interlaced (i), consisting of two 240-line fields presented/
scanned one at a time that total the 480 lines. Therefore a 480i NTSC
picture normally displays 240 lines each time the picture is scanned. The
NTSC signal passes through the DRC and MID circuits.
DRC Circuit
In this model KV32XBR400 high resolution TV, a single scan must con-
tain 540 lines, more than double of a NTSC signal. The DRC circuit al-
most bridges the gap between the 240 line input signal and the 540 line
TV requirement. The DRC circuit doubles the number of horizontal lines
by analyzing the pixel data to construct new lines. Therefore the DRC
circuit brings the total line count from 240 to 480. The DRC circuit also
doubles the horizontal frequency to 31.5kHz to support these lines.
 B BD. A BD.

Yo -7
TUNER/ Y, Pb, Cr-7
VIDEO 480i Pr Cb-7
IC3408, C BD.
1-4 IC3303 IC3410
STANDARD IC3048 DRC MID-XA
NTSC SW CIRCUIT IIC
H+V CIRCUIT
RESOLUTION BUS
CRT
H+V CATHODES
DATA/CLK Y, Pb,
SYNC IIC DATA/
Pr CONT CLK
BUS
IC3603 IC201
480i VIDEO IC9001-3
ID-1 IC3414 Y/C
RGB
DECODE YUV CRT
VIDEO 5 OUTPUT
SWITCH DRIVE
VIDEO 6 480p
480i
1080i
480p
1080i
OSD VERT
OUTPUT
IC5004
(D BD.)

SD TO HD CONVERSION CIRCUIT 12DTV02 10/2/00

16
 17
The MID circuit centers the picture by adding 30 blank lines above and
Progressive Scan - In this example of the progressive scan video pro- below the picture (60 lines total). This simple method permits the TV to
cessing, an NTSC still picture signal is input from a DVD player (in pause). keep the vertical frequency at 60Hz. Therefore the MID circuit increases
The user chooses progressive scan from the menu to reduce picture flicker. the number of lines from 480p to 540p but these extra lines are blank.
Flicker occurs in an interlaced picture when the two fields are not exactly There are still only 480 active (picture) lines.
the same images. The flicker is more noticeable in the movement area(s) 480 active lines
of the picture where the fields are different.
540p
In the progressive scan mode the DRC circuit doubles the number of lines
from 480i (actually 240 lines) to 480p to make the NTSC signal compat- 540 lines
ible with the TV. 480p
Tuner Expand
A/V DRC MID Vertical
Video 1-4 Switches circuit circuit
480p + 60 = 540p lines
480i 960i 480p Progressive
Progressive or
DRC Adds 60
interlaced output 480i MID Circuit
Interlace Scan - In a second example of the video processing, an NTSC circuit blank lines/scan
signal with live pictures is input from an antenna. The user chooses the 960i
interlace scan mode from the menu because of the moving images. Each Interlaced
interlaced field displays a slightly different transitioning picture making 960i + 120 = 1080i lines
movement seem smoother.
In the interlaced scan mode the DRC circuit still must double the number 1080 lines
of lines to meet the TV’s 480-line/scan requirement. The resolution is Expand
changed from 480i (actually 240 lines) to 960i (actually 480 lines) by the Vertical
1080i
DRC circuit.
960 active lines (2 fields)
MID Circuit
Vertical Expansion
Fortunately, the model KV32XBR400 TV’s horizontal deflection stage scans
at a 33.75kHz rate to display high definition (1080i) video signals. How- To keep the 60 blank lines invisible, the vertical size is expanded slightly
ever The horizontal frequency output the DRC circuit is double that of (picture overscaned) so the 480 lines fill the 4:3 aspect ratio screen. This
NTSC at 31.5kHz. This is slower than the KV32XBR400’s 33.75kHz rate. is seen in the previous diagram where the 60 blank lines are shown (ex-
Since the TV scans at a faster rate than what is input, the picture is fin- aggerated) in black.
ished faster, leaving blank lines at the bottom.

240/480 480
lines lines

15.75kHz/31.5kHz 33.75kHz
 B BD. A BD.

Yo -7
TUNER/ Y, Pb, Cr-7
VIDEO 480i Pr Cb-7
IC3408, C BD.
1-4 IC3303 IC3410
STANDARD IC3048 DRC MID-XA
NTSC SW CIRCUIT IIC
H+V CIRCUIT
RESOLUTION BUS
CRT
H+V CATHODES
DATA/CLK Y, Pb,
SYNC IIC DATA/
Pr CONT CLK
BUS
IC3603 IC201
480i VIDEO IC9001-3
ID-1 IC3414 Y/C
RGB
DECODE YUV CRT
VIDEO 5 OUTPUT
SWITCH DRIVE
VIDEO 6 480p
480i
1080i
480p
1080i
OSD VERT
OUTPUT
IC5004
(D BD.)

SD TO HD CONVERSION CIRCUIT 12DTV02 10/2/00

18
 19
High Definition Video Input 1080i Picture Process
The Video 5 and 6 inputs can be standard or high definition format sig- The 1080i-video format is a high-resolution picture with a 16:9 aspect
nals. The MID circuit distinguishes the video format by their horizontal ratio at a 33.75kHz horizontal frequency. The 1080i picture actually has
frequencies: 540 lines/scan (half 1080). Although 540 lines would fill this picture tube
Video 5 or Video 6 Input Formats Horizontal Frequency vertically, the picture tube is the wrong aspect ratio. The 16:9 picture is
480i 15.734kHz the correct width on the TV, but is too tall because it is displayed on a 4:3
480p (4:3 aspect ratio) 31.50kHz picture tube. To compensate, the vertical size is automatically reduced
480p (16:9 aspect ratio) 31.50kHz when a 33.75kHz input signal is detected. The final 1080i picture is a
1080i (16:9 aspect ratio) 33.75kHz “letterbox” on the KV32XBR400:
480p Picture Process
High Definition 1080i
A high-resolution 480p-video format is detected by its horizontal frequency picture on the 4:3
and selected by the MID circuit for video processing. The resultant pic- aspect ratio
KV32XBR400 TV
ture appearance will depend upon whether the video format of the input
signal is a 4:3 or 16:9 aspect ratio. 16 : 9 ENHANCED (VERT REDUCTION)
4:3 aspect ratio - The MID circuit processes a 480p, 4:3 picture the same
Aspect Ratio Detection
as the 4:3 NTSC picture. The MID circuit adds 60 blank lines to the sig-
nals. The picture is normally overscanned so the 60 blank lines are not The picture’s aspect ratio is always 4:3 for a standard 480i input and 16:9
seen. 540p for a 1080I input. Unfortunately a 480p signal can be in either aspect ratio
480p MID so the TV must be adjusted manually. The MID circuit monitors the hori-
4:3 pix 480 lines zontal frequency of the input signal when video 5 or 6 is selected. If the H.
Circuitry
input frequency is 15.734kHz or 31.5kHz, blank lines are added and the
Adds 60 Vert size picture is normally over-scanned vertically for a 4:3 picture. If the H. input
blank lines increased frequency is 33.75kHz, IC201’s (A board) vertical oscillator signal is am-
16:9 aspect ratio - The MID circuit does have to add 60 lines to the 480p, plitude reduced to maintain the correct aspect ratio for a 1080i, 16:9 pic-
16:9 picture when the horizontal frequency is changed. When this 16:9 ture on a 4:3 picture tube. Vertical reduction must be manually selected
picture is placed on a 4:3 screen, the picture is too tall (screen width was from the user’s setup menu when a 480p 16:9 signal is input.
reduced).
To maintain the aspect ratio of the picture, the vertical size must be manu- Picture Compensation using Horizontal Frequency
ally reduced so the picture looks normal on the TV’s 4:3 screen. Resolution Aspect Horiz Freq Vertical Lines
Ratio Compensation added
MID
540p 540p 480i 4:3 15.734kHz Normal Overscan Yes
480p
16:9 pix Circuitry 480p 4:3 31.50kHz Normal Overscan Yes
480p 16:9 31.50kHz Manual Reduction Yes
4:3 Vertical 1080i 16:9 33.75kHz Automatic Reduction No
Pix Tube size
reduced
 B BD. A BD.

Yo -7
TUNER/ Y, Pb, Cr-7
VIDEO 480i Pr Cb-7
IC3408, C BD.
1-4 IC3303 IC3410
STANDARD IC3048 DRC MID-XA
NTSC SW CIRCUIT IIC
H+V CIRCUIT
RESOLUTION BUS
CRT
H+V CATHODES
DATA/CLK Y, Pb,
SYNC IIC DATA/
Pr CONT CLK
BUS
IC3603 IC201
480i VIDEO IC9001-3
ID-1 IC3414 Y/C
RGB
DECODE YUV CRT
VIDEO 5 OUTPUT
SWITCH DRIVE
VIDEO 6 480p
480i
1080i
480p
1080i
OSD VERT
OUTPUT
IC5004
(D BD.)

SD TO HD CONVERSION CIRCUIT 12DTV02 10/2/00

20
 21

Video Block 3D Comb Filter - Color Bar input

Channel Name Location Comments
This Video Block Diagram will show the video signal processing as it
changes from an NTSC composite video signal to separate Y & C, com- 1 Input CN3201/pin 1 2Vp-p
ponent Y, Pb, Pr and finally to RGB for the CRT cathodes. 2 Y Output CN3201/pin 3 2Vp-p
3 C Output CN3201/pin 5 1.7Vp-p
Composite Signal Input (B Board) Time base = 20usec/div
The NTSC format video from one of the two tuners or video inputs 1-4 is Component Video Conversion (B Board)
selected by composite video switch IC3201. The user makes the selec-
The separate Y & C main signal is matrixed into component Y, Pb, and Pr
tion from the remote to the Main uCom IC701 through the I2C bus into
signals inside IC3048. This IC3048 can therefore act as a switch to choose
IC3201 (not shown).
between the component video input from Video 5, Video 6 or the main
There are three outputs from IC3201: signal from the 3D Comb filter.
IC3201 Outputs An additional RGB signal from the closed caption / V Chip IC3602 can be
Name Location Output Type Destination matrixed into the signal path by IC3048 if these features are selected by
Main CN3201/pin 1 Composite or Y (if S 3D Comb filter the user.
video input TV) IC3501 There are three outputs from IC3048:
Sub IC3201/pin Separate Y / C Y/C Sub IC3048 Outputs
56, 58 processor Name Output Type Destination
Monitor IC3201/pin Composite Rear panel output Main Signal Component Main/Sub selector
Y & C Separation (B Board) H & V Sync 1Vp-p Sync selector IC3004
The main composite signal enters the BC board that plugs into the larger Comp Video 1Vp-p CCD/V Chip IC3602,
B board. The 3D Comb filter separates the luminance from the chroma, ID-1 IC3603
pixel by pixel to output Y and C signals. The input and outputs of the Comp Video / ID-1 Concept
Comb filter are accessible and shown as 2Vp-p signals with a DC compo- ID-1 Concept
nent in this scope shot:
c h1
ID-1 is a relatively new concept. The ID-1 signal is hidden in the vertical
c h2 1 blanking area of the picture. This ID-1 signal identifies the aspect ratio of
c h3
the picture. IC3603 finds the signal and outputs data to the microproces-
sor. The micro can change the vertical or horizontal size to present the
picture properly. Recently, an ID-2 signal containing the aspect ratio and
copy guard information has been proposed.
Main Signal Path
2

The main component video and sync signals are sent to switches IC3002
C H 1 !2 .00 V ~

C H 2 !2 .0 0 V = STOP (video) and IC3004 (sync). They switch between the main and sub pic-
3
C H 3 !2 .0 0 V = C H P M T B 2 0 .0 us line c h 1p
tures. The outputs go to the Digital Reality Creation IC3303.
 CN3201/
CN3500 BC BOARD B BD.
SUB
44 1 76 Y,Pb,Pr
CN003/ IC3501
COMPOSITE/ (IC3110)
MAIN CN3203 3D COMB
A10 63 Y FILTER
TUNER 47 15 96
SUB A8 6 C 83 84 MAIN
IC3201 CN3500/
TUNER (S VIDEO) Y,Pb,Pr
IC3003 A/V C Y CN3201
A BD. SW -1 IC3002
SUB Y 5 3 DRC CD
MAIN YCT
COMB SEL/ TO
C SUB OUT C Y SEL
VIDEO 1 - 4 48 46 Y,Pb,Pr SYNC-SEL DRC - MF
480i FORMAT Y/C TO: MID-uCOM IC3303
A25 41 YCT SUB IC3090
MONITOR OUT IC3048 HTIM,VTIM MAIN
(IC3110)
YCT RGB IC3004 HD,
VIDEO MAIN DRC
VIN IC3602 VD HD - S
5-6 Y,Pb, Pr SYN
1 CLOSE CAP VD - S
480i/ SEL
SUB PIX V CHIP SUB (IC3110)
480p/
1080i COMPOSITE VIN
HTIM/VTIM SYNC
VIDEO IC3603 TO IC3413
U BD. IC3110 ID - 1 DEC 2
I C/ BUS (TO MID
DATA CLK uCOM IC3090)
VID 5,6
IC3001 COMPONENT
COMP J - F VIDEO TO IC3414

VIDEO BLOCK 1/2 4ADTV02 1254 10/2/00

22

Digital Reality Creation
This 3rd generation device has three main purposes:
• Doubles the number of pixels on each scanning line after analyzing
the pixels in the immediate area.
• Creates double the number of scanning lines by prediction.
• Doubles the horizontal frequency to match the new image.
The input is analog component video and the output is an 8 bit parallel
port for each of the three component lines - Y, Pb and Pr. The digital
output goes to the MID circuit IC3408.
23
To summarize the MID functions, 60 lines are added to the picture by the
MID-XA main signal processor IC3408 when the horizontal frequency is
not 33.75kHz. MID-uCom IC3090 instructs oscillator IC201 to reduce the
vertical amplitude when the sync is 33.75kHz (High Definition signal).
Signal and Sync Switches
Using control signal from MID-uCom IC3090, switches IC3414 and IC3413
select final signal and sync for the Y/C CRT Drive IC201.
The component video that leaves the B board is shown in the waveform:

P M 3 3 9 4 , F L U K E & P H IL IP S

Multi Image Driver (MID) Circuit

ch1
The purpose of the MID circuit is to:
1

•
ch2
Displays two images on the same screen (Main and Sub or Main and
High resolution). ch3

• Add 60 blank lines to the picture.

• Change the input signal’s horizontal frequency from 31.5kHz to
33.75kHz.
• Instruct the related MID uCom IC3090 what the input horizontal fre- 2

quency is so it can control the sync path and aspect ratio. Component Video leaving the B board - Color Bar input
Channel Name Location Comments
Any input signal selected is present at the MID-XA signal processor IC3408, 1 MID Y CN3203/pin B8 0.7Vp-p
so it knows what the input horizontal frequency is. Using this information, 2 MID Cb CN3203/pin B9 0.7Vp-p
the interconnected MID-uCom IC3090 can control the signal and sync
routing as well as send information to the Y/C CRT Drive IC201 for verti- 3 MID Cr CN3203/pin B10 0.7Vp-p
cal reduction. Time base = 10usec/div
MID-uCom IC3090 Outputs
Name Destination Purpose The following waveforms show the horizontal sync compared to the Y
DO, CO (data, clock) MID-XA IC3408 Add 60 blank lines signal. After the MID circuit, the frequency is 33.75lkHz.
IIC data bus Y/C, CRT Drive Vertical Reduction
Sync Sel Sync Sw IC3413 Sync for IC201
 OSD,RGB
MAIN FROM MAIN uCOM
Y,Pb,Pr IC701
FROM YO-7 YO-7 H DRIVE
IC3002
(YCT- CRO-7 CRO7 V DRIVE
IC3410
SEL) IC3303 C BD.
D/A
HD,VD DRC - MF CBO-7
IC3408
SYNC
MID - XA
FROM H+V CBO-7 RGB
IC3004 IC201 TO CRT
(DRC-SYN- Y,Pb,Cr
CN3203/ Y/C
SEL) MID-uCOM CRT
CN003 VIDEO
IC3090 DRIVE
II C BUS DO,CO Y B8
CN202/
DATA/ MID CB B9
CONT: CONT. CN9001 IC9001,
CLK CR B10 R
TO IC3414 MID-uCOM 1 IC9002
IC3402 64M
(YUV SW) IC3090 IC3414 G 3 IC9003
SDRAM 5
Y,Pb,Pr YUV SW. RGB
COMPONENT MID B OUT
8
VIDEO HIGH DEFINITION H B14
MAIN H, IK
FROM IC3001 VIDEO 5 OR 6 IC3413
B15
(AV-SW1) SYNC PROG VERT SYNC 10 G2
SEL MID MUTE
SW. SYNC
V P
HTIM MUTE
HD HORIZ. II C BUS
IC3048 (YCT POWER
B BD. MAIN) OFF MUTE
FROM MAIN
VTIM uCOM
INTERLACE IC701/67,
VERT Q708,Q730
IC3048,(YCT MAIN)
A BD.

VIDEO BLOCK 2/2 4BDTV02 1255 10/3/00

24
 25

Component Video leaving the B board - Color Bar input (vertical blanking area of ch 1) is still at 3Vp-p (power On level). The
normal green signal (ch 2) shows the IK signal is reduced to 1.8Vp-p
c h1
because the IK loop is complete. The last waveform (ch 3) does not show
1
c h2
the missing red IK signal because of sampling errors in the digital scope
c h3
used. IK drive pulses

3 39 , U & S

ch1

C H 1 ! 50 0 m V~
3

C H 2 ! 2 .0 0 V = ch2

C H 3 ! 2 .0 0 V = C H P M T B 1 0 .0 u s lin e ch1p T

ch3

Channel Name Location Comments 1

1 Mid Y CN3203/pin B8 0.7Vp-p

2

2 Mid H CN3203/pin B14 3.8Vp-p

3 Mid V CN3203/pin B15 3.8Vp-p C H 1 ! 2 .0 0 V =

C H 2 ! 2 .0 0 V = Vertical blanking
Time base = 10usec/div C H 3 ! 1 .0 0 V =
3 C H P M T B 5 0 0 u s - 1 .0 8 d v c h 1 -

IK drive signal in the vertical interval - Color Bar input

RGB Drive / AKB Circuit Channel Name Location (C board) Comments
The Y/C CRT Drive IC201 has several functions: 1 R Drive CN9001/pin 1 4Vp-p (open
• Amplifies the RGB signal and applies it to the CRT cathodes circuited)
• Mixes the main signal with the RGB On-Screen Display (OSD) 2 G Drive CN9001/pin 3 3Vp-p
• Automatic Cathode Balance (AKB) or IK (cathode current) 3 B Drive CN9001/pin 8 1.4Vp-p
The AKB circuit monitors the CRT cathode currents and adjusts the RBG Time base = 0.5msec/div
drive levels to compensate for CRT aging. By adjusting RGB drive levels
to simulate the same cathode currents, white balance can be maintained. Technical Note: If one or two cathodes falls below AKB adjustment range,
the video will NOT blank as in other AKB circuits. However, if a cathode
To accomplish this task, at power ON three IK drive pulses (about 3Vp-p)
draws too much current, (Ik pulse gets large) the picture will blank, and
from IC201 are sent to each CRT cathode (video is muted). The cathode
the standby light will blink five times and repeat.
currents from all three cathodes are returned to IC201 on the single IK
line. The three pulses are used to adjust the RGB drive pulses (and RGB In normal operation, if you increase the screen voltage, the IK return pulses
gain) to produce equal amplitude IK return pulse levels. When the AKB (ch 3) will increase in amplitude because more cathode current is drawn.
loop closes, the AKB drive pulse is reduced (1.8Vp-p - ch 2). Finally, the Because of the AKB closed loop, IC201’s output IK drive pulses (ch 2) will
video signal is unmuted to display a picture. decrease to lower the cathode current.
To see the full operation in the next scope shot, the red drive wire has
been opened at CN9001/pin 1. The CN9001/pin 1 connector is shorted to
ground to simulate a defect red cathode. Notice the red IK drive pulse
 OSD,RGB
MAIN FROM MAIN uCOM
Y,Pb,Pr IC701
FROM YO-7 YO-7 H DRIVE
IC3002
(YCT- CRO-7 CRO7 V DRIVE
IC3410
SEL) IC3303 C BD.
D/A
HD,VD DRC - MF CBO-7
IC3408
SYNC
MID - XA
FROM H+V CBO-7 RGB
IC3004 IC201 TO CRT
(DRC-SYN- Y,Pb,Cr
CN3203/ Y/C
SEL) MID-uCOM CRT
CN003 VIDEO
IC3090 DRIVE
II C BUS DO,CO Y B8
CN202/
DATA/ MID CB B9
CONT: CONT. CN9001 IC9001,
CLK CR B10 R
TO IC3414 MID-uCOM 1 IC9002
IC3402 64M
(YUV SW) IC3090 IC3414 G 3 IC9003
SDRAM 5
Y,Pb,Pr YUV SW. RGB
COMPONENT MID B OUT
8
VIDEO HIGH DEFINITION H B14
MAIN H, IK
FROM IC3001 VIDEO 5 OR 6 IC3413
B15
(AV-SW1) SYNC PROG VERT SYNC 10 G2
SEL MID MUTE
SW. SYNC
V P
HTIM MUTE
HD HORIZ. II C BUS
IC3048 (YCT POWER
B BD. MAIN) OFF MUTE
FROM MAIN
VTIM uCOM
INTERLACE IC701/67,
VERT Q708,Q730
IC3048,(YCT MAIN)
A BD.

VIDEO BLOCK 2/2 4BDTV02 1255 10/3/00

26
 27
left when both pictures are standard 480i video resolution. The confusing
Picture with Picture part is that when video 5 or 6 is selected and a 480p or 1080i signal is
The picture with picture feature in the Sony model KV32XBR400 and detected, the main picture moves to the right. There is no swap button to
36XBR400 TVs displays two signals side by side. The picture-in-picture exchange pictures.
feature containing a small “sub” picture in one of the corners of the main
picture is not used in this TV set.
Standard Resolution Input
When only standard resolution signals are selected in the picture-with-
If the left or right picture is defective or missing, the signal path is required picture mode, the left picture will pass through the DRC-MF circuit for
to localize the defect. There are two signal paths, one for each picture. In detail improvements. The right picture will enter the MID-XA circuit di-
comparing the two diagrams, you will note that the main picture is on the rectly to be reduced and merged with the main DRC picture on the same
screen.
CN003/ 480i
CN3203 Y,Pb,Pr
MAIN
A10
TUNER MAIN
TU - V IC3303 B BD.
SUB MAIN
A6
A/V SWITCHES DRC -
TUNER SUB
COMPOSITE TO MF
TU - V SUB
A BD. COMPONENT
MATRIX
MAIN
VIDEO 1 - 4 A BD.
CN3203/
VIDEO 5 - 6 CN003
IC3408 IC201
U BD. MID CRT
SUB XA MAIN + DRIVE
SUB

MAIN TUNER
VIDEO 1 SUB
MAIN IC9001 - 3
2 TUNER
480i SUB VIDEO
3 VIDEO 1
PIX IN 480i CRT OUT CN9001/
4 2
DRC PIX CN202
VIDEO 5 - 480i 3
PROCESS C BD.
6 - 480i 4

INPUTS ARE 480i

PICTURE WITH PICTURE - STANDARD RESOLUTION

High Resolution Input
If video 5 or 6 inputs were selected, the MID circuit measures the signal’s The right 480i main picture will come from the tuner or video 1-4 signals
horizontal frequency to identify the video signal. If the frequency is higher along the top 480i path through the DRC-MF IC3303.
than 15.75kHz, the signal is either 480p or 1080i. The MID uCom toggles
switches to set up the signal path shown in the diagram below. When a The right side picture in Twin View cannot select video 5 or 6 inputs (they
480p or 1080i signal is detected, this picture will be placed on the left side are skipped during the selection).
of the screen.

CN003/
CN3203 480i
MAIN A10 Y,Pb,Pr
TUNER MAIN
A/V SWITCHES IC3303
PIX
COMPOSITE TO DRC -
A BD. COMPONENT MAIN MF
MATRIX IC3408
VIDEO 1 - 4 MID
XA
IC3001
VIDEO 5 - 6 COMP
J-F HD
U BD. B BD. PIX MAIN
+ CN3203/
HD CN003

C BD. A BD.
VIDEO 5,6 480i IC201
IC9001 - 3 CRT
Y,Pb,Pr PIX IN DRC
VIDEO DRIVE
1080i/480p PROCESS
OUT CN9001/
TO CRT
CN202

HIGHER STANDARD
RESOLUTION RESOLUTION
PICTURE WITH PICTURE - HIGH RESOLUTION INPUT
VIDEO 5 MAIN TUNER
6 VIDEO 1
2
3
4

28
 29

Power ON Block Primary & Secondary Power Supplies

Before power ON can occur, the front panel master ON/OFF button (S01
on the HA board) must be pressed in. This latching switch behind the
Power Supplies button supplies the AC relay (RY6501) with standby 7V. Pressing the
There are four power supplies in the XBR400 TV: switch again would unlatch the switch and the set would shut OFF.
KV32XBR400 Power Supplies Power ON can be activated from the remote control or when the front
panel button is latched in. The second half of front panel switch S01 (not
Name Board Start Purpose
shown) grounds out the power ON input to Main uCom IC701. IC701
Standby A Plug in 5V for Main uCom powers ON the TV by turning on relay driver Q6527. Q6527 grounds one
7V & 15V for power relay end of relay RY6501 and momentarily turns on Q710 via C724. Q710
Primary A Power ON Unreg 11V, 7V, 5V become supplies a higher +15V to AC relay RY6501 because a relay needs more
regulated 9V, 5V, 3.3V. voltage to close the contacts than to hold them closed.
Secondary D Primary Pre +200V for HV stage,
15V, Main +135V for H. Output, +15V, Primary Power Supply
Relay +24V for Audio stage This power supply only needs 340Vdc from the bridge rectifier D6530 to
HV Converter D Horiz Output 31.5kV HV for CRT, Focus start up and run. Three voltages with the prefix “set” are used on the A
(not shown) AFC-PLS voltage. and plug in B and BC boards. The most important voltage is the Pri Pre
15V output that starts up the Secondary power supply on the D board.
Except for the Standby power supply, the Primary, Secondary and HV
Converter supplies are similar. The last three supplies use the same IC in
Secondary Power Supply
a similar configuration. How they are turned on and the voltages they
deliver is what makes them different. The Secondary Power Supply needs three items to operate:
Each power supply is turned on in the order listed. The first power supply
Three Items needed to run the Secondary Power Supply
is operational when the TV is plugged into AC. When the TV is powered
ON, the second and third supplies are turned ON one after the other. Item From Purpose
These supplies power the horizontal stages. Finally, the fourth power 340Vdc (B+) Bridge Rectifier D6530 Powers the Driver/Output
supply is turned ON after the horizontal output transformer develops scan, Pri Pre 15V Primary Power Supply Starts the oscillator when
filament voltage and AFC pulses. The last power supply is not shown on voltage secondary more than 15.6Vdc.
this diagram, but knowing when the HV is powered on is important for
troubleshooting. Main Relay Main uCom IC701 Enables IC6501 when
(normally HIGH) HIGH

Standby Power Supply
When the TV is plugged in, the standby power supply outputs three volt-
ages: +15V, +7V, and +5V. A small transformer develops the +15V and
+7V. The +7V is regulated down to +5V to power the Main uCom IC701.
This secondary power supply produces the remainder of the low voltages
to power the TV. The +200V feeds the HV Converter power supply. The
+135V powers the Horizontal stages. The +15V makes Main 12, Main 9
and Main 5V used throughout the D board. The +24V feeds the audio
output stage.
 STANDBY 5V
STANDBY
STANDBY 7V SOURCE IC6010 SET 9V
F6001 P.S.
6A STANDBY 15V
IC6007 SET 5V SOURCE

IC6003 SET 3.3V

DCC
DEGAUSSING STANDBY UNREG.
COIL
CIRCUIT 5V 11V 7V 5V
STANDBY 7V STANDBY 15V DGC
COIL
IC6001
D721 AC IC701
D722 PRIMARY
RELAY MAIN uCOM
Q710 POWER SUPPLY
S 01
C724 MAIN PRI
AC FRONT PANEL RELAY PRE
OUT POWER (HA BD.) POWER ON R6006 15V A BD.
SET (HA BD.)
ON
CN7003/
CN6013/ CN702/ 1 CN6005/
1 2 1 3 2 1 5
CN6502 CN6503 CN6504 CN6501
Q6530, AC
Q6532 OVP RECT D BD.
Q6527 +
PROT. OCP
LATCH +135V
RY6501
+200V
AC IC6501
SECONDARY +135V
D6530 R6526 POWER SOURCE
MAIN SUPPLY +- 15V
RELAY +24V
AUDIO

POWER ON BLOCK 6DTV02 1261 10/3/00

30

Primary Power Supply
The primary power supply on the A board consists of three parts:
1. Oscillator 2. Output stage 3. Regulator Stage
Start Up
The oscillator within IC6001 starts if the V Sense input voltage at pin 1 is
above 1.3Vdc. Sample voltage from pin 18 is then used to run the inter-
nal oscillator. The initial frequency is approximately 200kHz. The low
amplitude initial oscillator signal is output IC6001/pins 12 and 16 into the
driver/output stage.
Driver / Output stage
The oscillator voltage output at pins 12 and 16 use drivers Q6007 and
Q6008 to develop T6003 secondary voltages. IC6001’s oscillator will shut
down if the driver transistor’s current is excessive. To prevent premature
shutdown, the timer capacitor C6064 delays the shutdown.
VC1 Enables the Regulator
Although the oscillator is running, at this initial frequency of 200kHz, there
is insufficient current from T6003 to produce any unregulated 5, 7, or 11V
voltage because of the load. There is little load on D6005 and D6009,
producing about 15V each at the cathodes (normally about 18Vdc). The
voltage from D6005 is returned to IC6001/pin 8 to serve as regulated B+
for the internal drivers that amplify the oscillator signal leaving pin 12.
The VC1 voltage also enables the internal regulator circuit (responds to
the error voltage input IC6001/pin 2) to change the oscillator frequency.
B+ for IC6001’s Internal Drivers
At start up IC6001 uses current limited B+ from pin 18 to amplify the
oscillator signal and get it out to pin 16 (internal drivers). When VC1 is
present, the internal drivers switch to this stable regulated B+. The B+ for
the internal drivers for IC6001/pin 16 comes from Vb at pin 14. D6003
and C6009, external to IC6001/pins 10 and 14 (Vb), complete an internal
voltage boost circuit. This boost circuit starts with VC1 voltage (input pin
8) that is connected internally to VC2 pin 10 (less 0.6Vdc). This VC2
voltage is filtered by C6009 and passes through blocking diode D6003
31
into pin 14. Internal pulses from IC6001/pin 14 add to D6003’s DC volt-
age, producing the boost voltage at Vb pin 14. This boost voltage is
approximately +10V above the reference voltage at IC6001/pin 15 and
used internally to serve as the B+ for the top internal drivers that amplify
oscillator signal leaving IC6001/pin 16.
Secondary Power Supply Starting
The Pri Pre 15V output of D6009 is only approximately 10Vdc at start up
when the oscillator frequency is high (normally about 18Vdc). When is
reaches 15.6Vdc, it starts the Secondary Power Supply. Therefore, the
Secondary Supply cannot start until the Primary Supply is running.
Regulation
Concept
T6003’s secondary output voltages are dependent upon the match be-
tween the output resonate circuit (T6003 = L, C6014 = C) and the oscilla-
tor frequency. When IC6001’s oscillator frequency is the same as the
resonate circuit frequency, there is maximum power transferred in T6003
producing maximum output voltage. By setting the oscillator frequency
above resonance, T6003’s output voltage can be regulated.
85kHz = Normal Operation
T6003
Output
200kHz = Start Up
Voltage
Output Voltage Control
The regulating stage uses error detector IC6002 and optical isolator
PH6001 to monitor the unregulated +7V output from T6003. If the un-
regulated +7V output is LOW as it is at initial start up, the voltage fed back
to IC6001/pin 2 goes HIGH, decreasing the oscillator frequency. The
decrease in frequency increases the output of the T6003 transformer,
until +7Vdc is reached.
Regulation Feedback Voltages
Unreg 7V Output (D6011) PH6001/pin 2 IC6001/pin 2
Low high high
 D6012
T6003
A BD.
UNREG.
5V SOURCE
AC R6606
RECT.+ 0.47 OHMS
340VDC D6013
FROM
D6530 UNREG. 11V
R6059
(D BD.) R6007 SOURCE
18 PRI
R6008 VD Q6008 PRE 15V (D
N BD.)
VGH 16 R6002 D6009
CH
R6009 V
160V R6010 D6005
SENSE VS 15
1 IC6001
3V DRIVER Q6007
R6011 MCZ3001D
VGL 12 N
D6011
CH
UNREG.
7V
TIMER OCP R6043 C6014 SOURCE
9
VC1 VC2 VB F/B
6 8 10 14 2
R6049 R6050
+ 1.86V R6022
C6064 1
D6003 PH6001 IC6002 R6029
+ OPTICAL ERROR DET.
C6009 2 3 1
ISOLATOR uPC1093C

18.4V

PRIMARY POWER SUPPLY 7DTV02 1263 10/3/00

32
 33
In the following scope shot both drive outputs from IC6001/pins 12 and 16 Hot ground is at CN6501/pin 6 (black wire).
are shown. The outputs are complementary, the duty cycle is 50% and
the frequency has dropped down from 200kHz to about 85kHz. Oscillator Output Operation
ch1: pkpk= 325 V
ch1
ch1: freq= 84.8kHz The details of how the oscillator develops output voltage in T6003 are
ch2
explained here. When the oscillator in IC6001 starts up (V Sense = 3V,
T
no feedback VC1 voltage yet), the signal is amplified using unregulated
voltage input pin 18 and a 200kHz signal is output IC6001/pins 12 and 16.
1 This is shown in the following waveform:
PM3394, FLUKE & PHILIPS

ch1: pkpk= 349 V

ch1
ch1: freq= 209kHz

2
ch2
CH1! 100 V=

CH2!5.00 V= MTB2.00us- 1.18dv ch1-

Primary PS Oscillator - Normal operation - 85kHz

T

Channel Name Location Voltage

1
1 Top Driver Output Q6008/gate 340Vp-p
2 Bottom Driver Out Q6007/gate 12Vp-p (4.6Vdc)
Time base = 2usec/div. 2

CH1!79.9 V=

Testing CH2!10.0 V= MTB1.00us- 1.28dv ch1+

Primary PS Oscillator - Start Up = 209kHz

Checks for Primary power supply operation
Channel Name Location Voltage
Check Point Normal
1 Top Driver Output IC6001/pin 16 340Vp-p
1. R6006 340Vdc P.S. Input voltage
2. CN6005/ pin 5 >+15.6Vdc Pri-Pre 15V. Checks P.S. Output 2 Bottom Driver Out IC6001/pin 12 12Vp-p (4.6Vdc)
3. IC6001/ pin 2 1.9Vdc If step 2 voltage is low, measure Time base = 1usec/div.
(Feedback IC6001/pin 2. If pin 2 is High (4V) -
problem is around IC6001. If pin 2 The two signals applied to the Q6008 and Q6007 drivers are complemen-
voltage)
is Low (0-1V), problem is the tary. This means only one MOSFET is conducting at a time. A positive
feedback path IC6002, PH6001. voltage applied to top MOSFET Q6008’s gate turns it ON so its Drain to
4. IC6001 voltages. See the next chart. Source resistance drops, increasing the voltage to T6003’s primary wind-
ing. This voltage passes through the primary winding of T6003 into C6014.
As the increasing voltage charges C6014, a magnetic field is built up in
IC6001 Voltages (Power ON, Video 1 input, Dark screen) the primary of T6003. This magnetic field induces voltage into the sec-
1. 2. 3. 4. 5. 6. 7. 8. 9. ondary windings that is rectified to supply low voltages to the TV set.
3.0V 1.8V 2.2V 2.5V 0V 0V 4.5V 18.4V 0V The cycle continues when Q6008 turns OFF and Q6007 turns ON. The
10. 11. 12. 13. 14. 15. 16. 17. 18. charged C6014 discharges through the primary of T6003 and Q6007 to
10V 0V 4.5V -0.2V -28V -32V -32V -0.3V 313V ground. The cycle then repeats.
 D6012
T6003
A BD.
UNREG.
5V SOURCE
AC R6606
RECT.+ 0.47 OHMS
340VDC D6013
FROM
D6530 UNREG. 11V
R6059
(D BD.) R6007 SOURCE
18 PRI
R6008 VD Q6008 PRE 15V (D
N BD.)
VGH 16 R6002 D6009
CH
R6009 V
160V R6010 D6005
SENSE VS 15
1 IC6001
3V DRIVER Q6007
R6011 MCZ3001D
VGL 12 N
D6011
CH
UNREG.
7V
TIMER OCP R6043 C6014 SOURCE
9
VC1 VC2 VB F/B
6 8 10 14 2
R6049 R6050
+ 1.86V R6022
C6064 1
D6003 PH6001 IC6002 R6029
+ OPTICAL ERROR DET.
C6009 2 3 1
ISOLATOR uPC1093C

18.4V

PRIMARY POWER SUPPLY 7DTV02 1263 10/3/00

34
 35

Secondary Power Supply Regulation

The +135V line to the Horizontal Output stage is fed back to IC6501 for
The Primary and Secondary power supplies are similar because they use regulation of the secondary power supply. Error Control IC6503 and Optical
the same IC and driver/output stage. They differ in start up and output Isolator PH6502 control regulation. If the +135V output rises, the voltage
voltages. at IC6501/pin 2 lowers to correct. A reduced voltage increases the oscil-
lator frequency and decreases the output voltages of T6501.
Start UP
Although IC6501 is identical to IC6001 in the Primary power supply, IC6501/ Testing
pin 18 in this supply is not connected to 340Vdc. This makes VC1 at pin The typical error correction feedback voltage at IC6501/pin 2 is 2Vdc. By
8 the primary source of power to start this IC after pin 1 senses voltage. measuring the +135V B+ at R6598 and the feedback at IC6501/pin 2, you
The start up sequence is listed as follows: can determine if the problem is in the basic oscillator stage or the error
1. 340Vdc (B+) is applied to this stage from bridge rectifier D6530. regulator stage.
2. Pri Pre 15V voltage from the Primary power supply is applied to IC6501/
pin 8. It must be at least 15.6Vdc to enable IC6501’s internal oscilla- 1. Measure B+ at 2. Measure 3. Problem area
tor. R6598 (0.27 ohms IC6501/pin 2
3. Main Relay signal from Main uCom IC701/pin 72 (HIGH at CN6501/ at 1W) Voltage
pin 5) turns ON Q6531, PH6503 and Q6528. Q6528 turns OFF Q6503, B+ is LOW or 0V Higher than 2V Oscillator stage IC6501
enabling voltage to appear at IC6501/pin 1.
Lower than 2Vdc Error regulating stage
4. R6646 and R6513 deliver at least 1.3Vdc to IC6501/pin 1. IC6503/PH6502
5. IC6501 turns ON using voltage from pin 8 to run the oscillator.
6. An internal diode connected between pin 8 and 10 supplies voltage to B+ is HIGH Higher than 2V Error regulating stage
VC2. (shutdown Stby IC6503/PH6502
light blinks 3 times) Lower than 2Vdc Oscillator/Driver Stage
7. Oscillator pulses from VC2 pass blocking diode D6502 to make a
(“pump up”) voltage for the internal predriver amplifier stage. IC6501
8. Oscillator signal outputs IC6501/pins 12 and 16. IC V l (P ON Vid i D k )
In summary, these items are necessary to run the Secondary Supply: IC6501 Voltages (Power ON, Video 1 input, Dark screen)
Three Items needed to run the Secondary Power Supply 1. 2. 3. 4. 5. 6. 7. 8. 9.
Item From Purpose 2.5V 1.8V 2.2V 2.5V 0V 0V 4.0V 18.3V 0V
340Vdc (B+) Bridge Rectifier D6530 Powers the Driver/Output 10. 11. 12. 13. 14. 15. 16. 17. 18.
(CN6501/pin 1) 10V 0V 4.7V 0V -15V -19V -19V 0V 1.5V
Pri Pre 15V Primary Power Supply Starts the oscillator when
Hot ground is at CN6501/pin 6 (black wire).
voltage secondary more than 15.6Vdc.
(CN6501/pin 5)
Main Relay Main uCom IC701 Enables IC6501 when
(normally HIGH HIGH
at CN6504/pin 2)
 T6501 GND
D6530 PIT
AC R6526 AU + 24
0.1 OHM TO AUDIO
D6516
NO
AC R6646
CONNECTION
PRIMARY DC D6515 +200V
POWER 18
Q6507 SOURCE
R6513 D6517 TO HV
SUPPLY VD VGH 16 N
1 CH SOURCE
Q6503 V D6513
N SENSE R6533 R6598
VS 15
R6504 OFF 135V
SOURCE
R6552 R6517 Q6506
STANDBY 5V VGL 12 N - 15V
CH SOURCE
1
IC6501
Q6528 R6535
DRIVER + 15V
3 PH6503 MCZ3001D
N R6501 SOURCE
ON OPTICAL
OCP 9
ISOLATOR D6514 R6590
C6532
2 V B 14 R6556
MAIN 1 1
RELAY FROM ON Q6531 D6502
PH6502 IC6503
MAIN uCOM N VC2 10 OPTICAL CONTROL
R6557 IC701/72 4
F/B 2 ISOLATOR 2 4 DM-58
(A BD.)
8 VC1 5
START
PRI
PRE 15V
CN6005/6 D BD.
(A BD.)

SECONDARY POWER SUPPLY 8DTV06 1262 10/6/00

36
 37
quency, but the MID circuit stored the video and output the signal at a
Horizontal Drive / H Pincushion Correc- new H freq. of 33.75kHz, independent of the source.
PM3394, FLUKE & PHILIPS

tion / Filament Voltage ch1

1

ch2

Overview
ch3 2
The purpose of the horizontal drive circuit is to manufacture a magnetic
field that is used to sweep the CRT’s electron beam from left to right on ch4

the screen. Within the basic horizontal drive circuit there is a PWM circuit 3

that supplies the Horizontal Output transistor with voltage and provides
horizontal pincushion correction. The horizontal drive circuit also makes
the CRT filament voltage. CH1!2.00 V~

CH2!2.00 V~

CH3!10.0 V~ STOP

Basic Horizontal Drive Circuit 4

CH4! 125 V= ALT MTB5.00us L=2 ch2p

This circuit is split between an oscillator on the A board and an output Horizontal Drive Signals
stage on the D board. The 33.75kHz horizontal oscillator is in the Y/C
Channel Name Location Voltage
CRT Drive IC201. IC201 outputs a 2Vp-p rectangular waveform from pin
40 while there is B+ at pins 55 & 61 and the 2.7MHz X201 crystal is 1 15.75kHz H signal NTSC generator from the
running. The horizontal drive waveform is buffered by Q211 and enters Input generator
the D board. 2 33.75kHz osc output IC201/pin 40 2.2Vp-p
On the D board, an N channel MOSFET driver and an output transistor 3 H Driver input Q5028/gate 12Vp-p
amplify the signal to provide sufficient current to drive the HOT T5001 and 4 Horiz Output Q5030/Collector 1kVp-p
the H DY deflection yoke.
Time base = 5usec/div.
At the output stage, the HOT T5001 has a secondary winding that pro-
vides filament voltage while its main winding provides +200V for the RGB
video output ICs. While the H DY yoke provides horizontal beam deflec- PWM Circuit
tion (sweep), a voltage divider consisting of capacitors C5058-C5060 tap The PWM circuit has two functions. First it provides a regulated 102Vdc
off a sample of the H spike from the H Output Q5030/Collector to start the output for the H Output transistor. Second it compensates for horizontal
HV converter stage. This AFC-PLS is also used in the convergence and pincushioning and keeps the picture straight at the sides.
dynamic focus stages.
The waveforms of the horizontal drive stage show typical signal shapes. No horiz Pix is
The difference between this set and a conventional one is that the hori- pincushion bowed
correction inward
zontal frequency is 33.75kHz (ch 2), not 15.75kHz (ch 1). When compar-
ing the input sync (ch 1) to the horizontal oscillator (ch 2), notice that they
are not in phase. This is because the DRC circuit doubled the H fre-
MAIN X201
61 33
9V RGB
MID HS 55 CN203/ Q5035,
IC201 HD VIDEO
IC3413/4 CN5505 Q5036, MAIN OUTPUT
39 Y/C CRT 40 2 Q5026-7 12V
SYNC SW. (C BD.)
DRIVE H DRIVE
(B BD.) Q211
CXA2150Q
A BD. 47 7
E/W Q5016
AFC-PLS 37
CN201/ 200V
DRIVE
Q5030/C CN5503 REG.
H. PROT
D5013
IC701/44
CRT
Y/C (A BC.) 135V HEATER
Q5004
OCP

HOT
IC5002, T5001 HOT
102V
Q5003, 1 R5096
Q5011 2
C5035
PWM CIRCUIT + 100
D5015 IC5006
+135V
R5013 8 6V
R5095 D5014 REG.
7 D5024

Q5030 R5094 D5012 G2 R5164

H OUT TO
T5002 D5025
C5058 C BD.
HDT H DY
N
R5142-4
D5023 UNREG.
N AFC-PLS TO: 7V (A BD.)
CH C5059
Q5028 IC8001/8 HV CONV.
DRIVER IC5511/19 DQP CONT.
D BD. D5018
C5060 IC5513/14 DY-CONV.
50V
IC201/39 Y/C CRT DRIVE

HORIZONTAL DRIVE 14DTV02 1266 10/10/00

38

Regulator
The PWM circuit regulates +135Vdc from the secondary power supply
down to 102Vdc. It is driven by H drive pulses from Drivers Q5026-7.
These pulses are amplified and output to HOT T5001/pin 1. To control
the output voltage, the output is sampled and used to change the pulse
width of the H drive pulses. These changes regulate the output voltage to
102Vdc at T5001/pin 1.
Pincushion correction
If the PWM output voltage at T5001/pin 1 were changed, the horizontal
picture size would vary accordingly. A vertical pincushion signal made by
IC201/pin 47 is applied to this PWM stage to increase the picture width
and compensate for pincushion distortion.
The first waveform shows the input E/W (east/west) pin correction signal.
The second waveform is the PWM output. The corresponding modula-
tion (sum of E/W signal and horizontal drive) changes the width of the
output pulses (ch2), but that is not easily seen at this scope’s time base.
39
Filament Voltage
There are two sources of filament voltage. When the set is turned ON,
unregulated 7V from the primary power supply (A board) is reduced by
D5025 and D5024 to approximately (7V-1.2V =) 5.8Vdc. This is the first
filament voltage source used warm up the CRT quickly at power ON.
There is no danger from this unregulated 7V supply. Excessive voltage
on the unregulated 7V-line causes Main uCom IC701 to shut down the TV
set (protection circuit not shown here). Consequently, filament damage
from an unregulated primary power supply is unlikely unless a technician
bypasses the protection circuitry during troubleshooting.
The second filament voltage is applied when the horizontal oscillator sig-
nal produces horizontal sweep. The horizontal output transformer T5001/
pin 8 outputs 7.7Vdc when running. This voltage is regulated to 6.1Vdc
by IC5006 to become the main filament voltage.

ch1

1
ch2 T

CH1! 500mV~

CH2!50.0 V= MTB5.00ms ch1+

Horizontal Pincushion Correction

Channel Name Location Voltage
1 E/W Drive Cn5505/pin 7 0.7Vp-p
2 PWM Output T5001/pin 1 150Vp-p.
102Vdc
Time base = 5mesc/div.
MAIN X201
61 33
9V RGB
MID HS 55 CN203/ Q5035,
IC201 HD VIDEO
IC3413/4 CN5505 Q5036, MAIN OUTPUT
39 Y/C CRT 40 2 Q5026-7 12V
SYNC SW. (C BD.)
DRIVE H DRIVE
(B BD.) Q211
CXA2150Q
A BD. 47 7
E/W Q5016
AFC-PLS 37
CN201/ 200V
DRIVE
Q5030/C CN5503 REG.
H. PROT
D5013
IC701/44
CRT
Y/C (A BC.) 135V HEATER
Q5004
OCP

HOT
IC5002, T5001 HOT
102V
Q5003, 1 R5096
Q5011 2
C5035
PWM CIRCUIT + 100
D5015 IC5006
+135V
R5013 8 6V
R5095 D5014 REG.
7 D5024

Q5030 R5094 D5012 G2 R5164

H OUT TO
T5002 D5025
C5058 C BD.
HDT H DY
N
R5142-4
D5023 UNREG.
N AFC-PLS TO: 7V (A BD.)
CH C5059
Q5028 IC8001/8 HV CONV.
DRIVER IC5511/19 DQP CONT.
D BD. D5018
C5060 IC5513/14 DY-CONV.
50V
IC201/39 Y/C CRT DRIVE

HORIZONTAL DRIVE 14DTV02 1266 10/10/00

40
 41

G2 Circuit G2 (RV9002) Voltage Range

RV9002 Position G2 Voltage
Operation CCW 292.4Vdc
The G2 circuit controls the voltage to the screen grid of the CRT. The Normal 484Vdc
higher the voltage the more electrons are accelerated in the gun struc- 2/3 CW 590Vdc is maximum before shutdown
ture, resulting in a brighter picture.
The source of the G2 voltage is approximately 1kV from the Horizontal Operating Voltages
Output Transformer (T5001) secondary winding. The G2 control circuit
uses three transistors to shunt some of the G2 source voltage to ground. Normal Operating Voltages
The remaining voltage is applied to the CRT’s G2 grid. A simplified dia- Transistor Collector Base Emitter
gram of this voltage divider is shown below: Q9002 10.9V 0V 0V
Approx. Q9008 12.0V 5.4V 4.8V
1kV from CRT G2 Q9012 10.4V 5.4V 4.8V
Resistor string
the HOT voltage
T5001/6 Q9014 438.5V 11.5V 10.9V

Automatic Video Mute

At power OFF, the Main uCom IC701 outputs a HIGH that turns on Mute
transistor Q9002. Q9002 lowers the G2 voltage, blanking the video when
Shunt
the TV is shut off. The HIGH remains present as long as the TV is plugged
Transistors
G2 HV Adj in (standby voltage is present).
Q9014,
RV9002
Q9012,
Q9008

Within the shunt circuit are three transistors. Q9008 is used as a refer-
ence while Q9012 and Q9014 set the resistance to ground.
Rotating RV9002 varies the conduction of Q9012 and Q9014, and conse-
quently the shunt resistance. A lower shunt resistance produces a lower
G2 voltage. The G2 voltage range of the screen control is listed in the
chart.
 G2 R9062 R9056
VOLTAGE R9055 R9085 R9064 R9084 100k 100k
489VDC
FROM HOT
T5001/6 R9063 484VDC
(D BD.) 100k CRT
907VDC 180k OHMS R9077 C9032
1/2W G2
EACH 1k
12V N GRID
D9013 + Q9014
G2-DUMP D9014 G2-REF R9067
C BD. PROT

R9076

D9015
PROT
R9005 Q9008
D9003 R9004
Q9002 G2-REF Q9012 10.4V
D9001 R9078 G2-REF
MUTE
N N
N
+ 5.4V
C9036 D9016 PROT
FROM MAIN
POWER 10 D9017 PROT
uCOM
OFF MUTE
IC701/67 RV9002
(A BD.) R9009 10k R9010 100k
+ R9079 R9081 C9047
10k G2
+ 0.01
C9038 CHIP
C9037 R9063
4.7
2.2

G2 CIRCUIT 18DTV02 1267 10/3/00

42
 43

HV Converter Block Protection / Shutdown

There are two protection circuits for the HV stage. The first circuit shuts
This HV Converter is similar to the two low voltage power supplies be- down the HV oscillator if the HV is excessive (without affecting the sound).
cause they have the same MCZ3001D ICs. This power supply differs The second circuit shuts down the entire TV set if the +200V current de-
only in the start up, voltage output, and over voltage (OV) protection. The mand is excessive.
Flyback Output transformer of this power supply generates regulated
31.5kV and focus voltage for the CRT. Excessive current drawn by this Excessive HV Protection
stage will permit Q8009 to shut down the TV set, but there will be no The HV oscillator in IC8002 is stopped if the HV sampled from the flyback
Standby light blink indication. is excessive. The oscillator stops when via Q8003 or Q8004 grounds
IC8002/pin 1.
Start Up Sample high voltage from the flyback transformer normally takes two paths
to keep Q8003 and Q8004 turned OFF. The first path is from D8014
Three items are necessary to start this HV power supply:
through 33V zener D8025. If the sample HV is excessive, zener D8025
HV Converter Inputs (Starting) conducts, turning ON Q8010. A LOW voltage outputs to IC8001/pin 7.
Name From Destination The LOW input and output turns Q8003 ON, grounding IC8002/pin 1.
This shuts down the HV Converter stage.
1. +200V D6515 & D6517 / cathode(D Bd) IC8002/18 (199V)
The second shutdown path is from D8014 through R8078, and IC8001 to
2. +15V D6514 / cathode (D Bd) IC8002/8 (14.7V)
Q8004. An excessive voltage will similarly turn Q8004 ON, shutting down
3. AFC- H Out Q5030/C (D Bd) IC8002/1 (1.6V) the HV Converter. RV8001 and RV8003 form a voltage divider along the
PLS (CN5501/pin 3 = 9Vp-p feedback path to set the shutdown point.

The Start sequence is as follows: Excessive Current Protection

1. The Primary power supply produces low voltages for the Horizon- Excessive current drawn by the +200V line into this HV Converter stage
tal stage (D board). causes the TV to shut down. There is NO Standby light blink indication
2. The Secondary power supply produces +135V for the Horizontal when this HV stage shuts down the TV. The +200 line feeds IC8002, the
stage, along with +200V and +15V for this HV Converter stage. two converter transistors (not shown), and flyback transformer. Exces-
3. The Horizontal Output stage is needed to develop AFC-PLS pulses sive HV will also cause the TV to shut down by drawing too much current
(CN5501/pin 3 = 9Vp-p) for the HV Converter. through the flyback.
4. AFC-PLS pulses turn ON Q8001 and turn OFF Q8002. In summary, shutdown without a Standby light indication indicates a prob-
5. IC8002/pin 1 rises. (1.3Vdc is the minimum to start IC8002). lem in this HV stage.
6. IC8002’s oscillator starts and drives the flyback transformer.
7. The voltage at IC8002/pin 2 decreases from 4V to 2Vdc as the HV HV Adjustment
climbs to 31.5kV.
8. Regulated HV and focus voltage output the Flyback transformer. The adjustment procedure for these three controls is straightforward. First
the shutdown controls are preset (ineffective). Then the RV8002 HV con-
trol is set to the shutdown trip point. The two shutdown controls are reset.
Finally the HV control is set. A HV probe connected to a DVM is required
for this adjustment procedure.
 Q8009 SHUTDOWN LATCH
+200V D8003 Q6530,Q6532
(FROM OCP
D BD.
SECONDARY
POWER R8053-
SUPPLY) R8055
V 18
ON OFF VD HV TO
AFC SENSE
PLS 1
IC8002 CONVERTER PICTURE TUBE
(Q5030/C Q8002 HV DRIVER TRANSISTORS
Q8001 + FLYBACK
H OUT) MCZ3001D FOCUS
8 2 VOLTAGE
START R8056 VC1
HV C8004 F/B (PICTURE
CONV. 100 OFF TUBE)
+15V
(SEC P.S.)
Q8004 IC8003, IC8004 Q8022-3, Q8018
OFF RV8002 PH8001 ERROR DYNAMIC FOCUS
HV DET AMP
Q8003
D8025
D8020 33V
+ 7 DF DRIVE
1 +
- 6 DQP CONTROL
C8005 Q8010 IC5511/11
IC8001 47
OP AMPS D8004
NJM2901M 5.1V

- 4
2 R8078 D8014
+ 5
R8042
RV8001
(COARSE)

RV8003
(FINE)

H.V. CONVERTER BLOCK 9DTV02 1264 10/3/00

44
 45
The procedure is as follows: Converter IC8002 Voltages
1. Replace RV8001, RV8002, and RV8003 (they are epoxyed). Pin 1 2 3 4 5 6 7 8 9
2. Turn RV8001 and RV8003 both CCW from the top of the D board.
Volts 1.63 1.75 2.25 2.47 0 0 4.56 14.7 0
3. Turn the set ON with a black screen (HV unloaded).
4. Adjust HV RV8002 for 35.5kV (shutdown threshold). Pin 10 11 12 13 14 15 16 17 18
5. Adjust RV8001 and RV8003 until the set just shuts down. Volts 10.3 0 4.14 0 108 98.6 103 0 200
6. Turn HV RV8002 CW to turn the set ON. Input a white signal. Bring
the HV up to 35kV to make sure the set does not shut down. (This
rechecks the RV8001 and RV8003 adjustments.) Additional Important Voltages related to IC8002/pin 1 Voltage
7. Adjust HV RV8002 for 31.5kV. Electrical Location Physical Location Voltage
8. Guard against premature shutdown by following bulletin 492 IC8001/pin 1 14 pin Surface mounted IC under 0V
(appendix). RV8001/RV8003
IC8001/pin 2 0V
Testing C8004/ + lead Behind IC5515 s large heat sink 0.02V
next to large 820uf, 250V C8023.
1. HV Check - Measuring the voltage at D8025/Cathode verifies HV.
Normally D8025/Cathode = 31.6Vdc when there is HV, and 0V when HV 3. HV may be starting, then shutting down - Monitor D8025/Cathode for
is missing. D8025’s Anode voltage should not be higher than 0.6Vdc in 3.16V at start up. If it is 0V, there is no HV. Check the converter transis-
normal operation (measured). D8025 is located next to the potted (epoxy tors and suspect IC8002 and the flyback to cause OCP shutdown (via
sealed) RV8001/RV8003 controls at the left edge of the D board. Q8009). If the cathold voltage momentarily rises to beyond 31Vdc, there
is HV but it may be excessive. Turn the RV8001 and RV8003 controls
CCW and adjust the HV. Follow the HV adjustment procedure. If shut-
D Bd A Bd down still occurs suspect D8025, C8005, and D8004.

D8025
Flyback

KV32XBR400 rear

2. HV Converter Check - If no HV is output, look for +200V input at

IC8002/pin 18 and more than 15.6V at IC8002/pin 8.
Look for HV Conv start voltage at IC8002/pin 1 (normally 1.6Vdc but must
be more than 1.3Vdc. to start).
 Q8009 SHUTDOWN LATCH
+200V D8003 Q6530,Q6532
(FROM OCP
D BD.
SECONDARY
POWER R8053-
SUPPLY) R8055
V 18
ON OFF VD HV TO
AFC SENSE
PLS 1
IC8002 CONVERTER PICTURE TUBE
(Q5030/C Q8002 HV DRIVER TRANSISTORS
Q8001 + FLYBACK
H OUT) MCZ3001D FOCUS
8 2 VOLTAGE
START R8056 VC1
HV C8004 F/B (PICTURE
CONV. 100 OFF TUBE)
+15V
(SEC P.S.)
Q8004 IC8003, IC8004 Q8022-3, Q8018
OFF RV8002 PH8001 ERROR DYNAMIC FOCUS
HV DET AMP
Q8003
D8025
D8020 33V
+ 7 DF DRIVE
1 +
- 6 DQP CONTROL
C8005 Q8010 IC5511/11
IC8001 47
OP AMPS D8004
NJM2901M 5.1V

- 4
2 R8078 D8014
+ 5
R8042
RV8001
(COARSE)

RV8003
(FINE)

H.V. CONVERTER BLOCK 9DTV02 1264 10/3/00

46
 47
nected to both memories in parallel. The first group of communications
Communications goes to IC707. IC5501 is hard wired differently at pins 2 and 3 to accept
There are three communications networks used in this DX-1A TV chas- the second communications group from IC701.
sis. All three consist of only clock and data lines running on a parallel
ch1
connection with multiple ICs.
Communications Networks ch2
T
Network Location Purpose 1
ch3
0 IC701/pin Dedicated communications to
(clock 0, data 0 lines) 29, 30 the two NVM on the A & D
boards (IC707 & IC5501. 2

1 IC701/pin Main IIC bus to provide

(clock 1, data 1 lines) 28, 31 direction to most ICs on the A,
B, & D boards
2 B Bd. Multi Image Driver (MID) 3

IC3090 to uCom CI3090 communications C H 1 !5 .0 0 V =

IC3089 & link with driver IC3408 and C H 2 !5 .0 0 V = STOP

IC3408 NVM (memory) IC3089. C H 3 !5 .0 0 V = C H P M T B 5 .0 0 m s - 2 .5 8 d v c h 1 -

Memory Communications - TV Channel 7 displayed

Communications Network 0 & 1
Scope Channel Name Location Voltage
Main uCom IC701 generates the clock signal for communications net-
work 0 and 1. Network 0 is used by IC701 to read and write data to NVM 1 WP (read/write) CN702/pin 8 5Vdc
IC707 (A board) and IC5501 (D board). Network 1 is used to send data to 2 Clock CN703/pin 1 5Vp-p
most of the ICs in the TV set. 3 Data CN703/pin 2 5Vp-p
At power ON, the user data in IC707 and deflection data in IC5501 is Time base = 5msec/div.
retrieved by IC701 using network 0 and passed to the appropriate ICs
using network 1. Once the ICs on network 1 receive this data to set their
operating parameters, the TV can function. In this second scope shot, when the TILT rotation number is changed
from the setup menu, the WP pulse (ch 1) goes LOW when the network 0
The Y/C CRT Drive IC201 on the A board and MID uCom IC3090 on the is communicating with IC707. This allows IC701 to write the new rotation
B board can provide return (reply) data to IC701. This data either up- number into NVM IC707.
dates the on-screen display menu (OSD is in IC701) or initiates a safety
shutdown of the TV.
The data at both network 0 and network 1 is always present as long as the
TV is ON. The first scope shot shows the network 0 data being read from
NVM IC707 and IC5501. The clock and data lines from IC701 are con-
 STBY+5V
16 62 R834 A BD.
Q717
50
RESET 8
WP
IC701 47 7 1
MAIN uCOM CLK 0 IC707 2 D BD.
29 6
NVM 3
DAT 0
DAT 1 30 5 4
CLK 1 CN702/
31 28
WP CN6504 1
8 7
R829 CLK IC5501 2
2 5
NVM STBY+5V
3
STBY+5V DATA 1 6
4
R827 CN703/ 8
CN6506
STBY+5V
5
IIC BUS IC201Y/C IC7001
MAIN SUB IC5511
CRT AUDIO
TUNER TUNER DQP CONT.
DRIVE PROC.

DATA 8 IC5513
7 DY-CONV.
CN706/
DAT. CLK CLK
1 2 A29 A30 CN5501
CN203/
CN7001/ CN3203 BC BD.
CN4104
IC3001 IC3090 IC3201 A/V IC3202 IC3601 SUB
IC4103 COMP. I/F MID uCOM SW. AUDIO SW. CCD V CHIP IC3501
AUDIO 9 3D
D/A 10
IC3408 IC3110 Y CT IC3602 MAIN COMB
MID-XA SUB CCD V CHIP
IC3408 IC3089 CN3201/
S BD. Y CT MAIN NVM CN3500
B BD.

COMMUNICATIONS BLOCK 65DTV02 1280 9/29/00

48
 49
PM3394, FL UK E & PHILIPS

c h1
Network 1 Communications - TV Channel 7 displayed
Scope Channel Name Location Voltage
c h2

1
T
1 Clock CN706/pin 7 5Vp-p
c h3

2 Data CN706/pin 8 5Vp-p

2 Time base = 5msec/div.
Communications Network 2
Communications network 2 is only used between three ICs on the B board.
3

CH1!5.00 V=
MID uCom IC3090 communicates with MID IC3408 to retrieve processed
CH2!5.00 V= data such as the input horizontal frequency and uses it to select video
CH3!5.00 V= CHP MTB5.00m s- 2.58d v c h 1-
signal paths.
Memory Communications during picture Tilt
MID uCom IC3090 also communicates with memory IC3089 and IC3408
Scope Channel Name Location Voltage to set up the twin picture (picture with picture) parameters. This data in
1 WP (read/write) CN702/pin 8 5Vp-p memory IC3089 is accessed in the service mode using MID uCom IC3090
to interface to IC701. MID uCom IC3090 is connected to communica-
2 Clock CN703/pin 1 5Vp-p
tions network 1 and 2.
3 Data CN703/pin 2 5Vp-p
Time base = 5msec/div.

Although not shown, network 0 data and clock are accessible at the 10-
pin rear panel service connector.

Network 1 communications is also always present when the TV is ON. A

scope shot of the two 5Vp-p signals is shown:

1
ch1

ch2
T
2

CH15.00V~ STOP

CH25.00V= MTB5.00ms- 1.32dvHxx

 STBY+5V
16 62 R834 A BD.
Q717
50
RESET 8
WP
IC701 47 7 1
MAIN uCOM CLK 0 IC707 2 D BD.
29 6
NVM 3
DAT 0
DAT 1 30 5 4
CLK 1 CN702/
31 28
WP CN6504 1
8 7
R829 CLK IC5501 2
2 5
NVM STBY+5V
3
STBY+5V DATA 1 6
4
R827 CN703/ 8
CN6506
STBY+5V
5
IIC BUS IC201Y/C IC7001
MAIN SUB IC5511
CRT AUDIO
TUNER TUNER DQP CONT.
DRIVE PROC.

DATA 8 IC5513
7 DY-CONV.
CN706/
DAT. CLK CLK
1 2 A29 A30 CN5501
CN203/
CN7001/ CN3203 BC BD.
CN4104
IC3001 IC3090 IC3201 A/V IC3202 IC3601 SUB
IC4103 COMP. I/F MID uCOM SW. AUDIO SW. CCD V CHIP IC3501
AUDIO 9 3D
D/A 10
IC3408 IC3110 Y CT IC3602 MAIN COMB
MID-XA SUB CCD V CHIP
IC3408 IC3089 CN3201/
S BD. Y CT MAIN NVM CN3500
B BD.

COMMUNICATIONS BLOCK 65DTV02 1280 9/29/00

50
 51
This means the focus point must be moved up at the left and right sides to
Dynamic Focus Block meet the flat picture tube screen.

Static Focus Concept Dynamic Focus Concept

An electron beam within the picture tube consists of many electrons that
are slowed down by the focus electrode. After passing through the focus
electrode, the accelerating electrode brings the beam to a fine point on
the screen. This focus point is positioned by adjusting the voltage at the
focus electrode relative to the accelerating voltage. The accelerating volt-
age is usually fixed at the HV potential from the flyback secondary.
CRT Electrodes:
Focus Accelerating
Focus
Electron point
beam
The job of the dynamic focus circuit is to change the focus points to meet
the flat picture tube screen. This is done by either increasing the static
focus voltage when the beam is at the left and right sides of the screen or
decreasing the static focus voltage when the beam is at the middle of the
screen. Either method accomplishes the same effect. This dynamic fo-
cus correction voltage is shaped like a parabola to match the focus arc.
H D ynam ic focus voltage
N o correction
left right
HV to CRT

DF Flyback Focus V to CRT

As the electron beam is moved from side to side (swept) by the magnetic Transformer
field created by the external horizontal deflection yoke, the focus points
form an arc as shown by the arrowheads. Early picture tube glass screens Circuitry
were made into a similar arc to maintain focus at the left and right sides of The Dynamic focus circuitry is divided into two parts:
the screen.
Right • DF Drive
Focus Arc
Yoke
side • Modulated power supply
Both signals are fed to DFT T8002 to make the dynamic focus voltage. In
Flat the scope shot, the top waveform is the DF Drive and the second is the
CRT modulated power supply. The third waveform is the flyback signal that
Electron screen marks the left and right sides of the screen.
beam PM3394, FLUKE & PHILIPS

ch1
T

Left ch3

side ch4
1

Picture Tube - Top View

3

CH1! 100 V~
4
CH3!50.0 V~ STOP

CH4!10.0 V= ALT MTB5.00us ch1+

 T8001
FLYBACK
TV SCREEN CRT
D BD. HV

HV CRT
CONV FOCUS
VOLTAGE
17

IC5502 13 Q5508,
OP AMP Q5509

DF FOCUS
2/2
11
* DRIVERS
1

CORRECTION T8002
C5509 R8082 DFT
4
AFC-PLS Q8018 6
H OUT Q5501 DF
Q5030/C Q8022, OUTPUT
C8058 3
2 Q8023
19 N L8005
DRIVERS 1
DATA 1 IC5502
IC5511 OP AMP D8017
DAC1
DQP
CONTROL
11 5 1/2
* Q8015
+135V

SW 91VDC
CXA202GAS Q8019,
CLK 2
14 Q8020 P
IIC 21 SWO C8051 DF PROT R8101
BUS 10 Q8016 C8060
SW 4.7
160V
VTIM CN5503/2 R8102
Y/C CRT DRIVE 22k SM CATEGORY 2026AS
IC201/54 DF ON - 0=ON, 1=OFF
* IC5502 = NJM2901M
DF - CHANGES FOCUS START

DYNAMIC FOCUS 15DTV 1268 10/10/00

52
 53

Dynamic Focus Signals DF Drive Signals

Channel Name Location Voltage Channel Name Location Voltage
1 DF Drive signal T8002//pin 3 400Vp-p 1 AFC-PLS IC5511/pin 19 10Vp-p
2 Modulated power supply T8002//pin 1 140Vp-p 2 Dynamic Drive IC5511/pin 11 0.3Vp-p
3 AFC-PLS (H fly pulses) IC5511/pin 19 10Vp-p 3 Delayed DF Drive Q8018/Base 10Vp-p
Time base = 5usec/div 4 Final DF Drive Signal Q8018/Collector 400Vp-p
By examining the channel 2 and 3 waveforms, the modulated power sup- Time Base = 5usec/div.
ply (ch 2) is turned off before and after the H sync pulse (ch 3). This
Modulated power supply
means there is no dynamic focus correction to the left nor right sides of
the screen. However focus correction is applied to the center of the pic- The modulated power supply signal is also made in IC5511 from horizon-
ture as seen by the increasing voltage at the DF drive signal (ch1). The tal and vertical timing pulses input pins 19 and 21. IC5511’s output signal
focus correction at the center brings the focus point to the same level as is AC coupled to switches Q8015 and Q8016 and finally applied to T8002/
the sides. pin 1. The modulated power supply signal passes through T8002 to power
DF Output transistor Q8018 with modulated dynamic focus voltage.
DF Drive In the scope shot of the DF power supply, the channel 2 waveform shows
two switching voltages in between the H sync pulses (channel 1). The
The DF drive signal is manufactured in IC5511 from horizontal and verti-
two positive switching voltages in channel 2 result in low going B+ parts of
cal timing pulse input at pins 19 and 21. The drive signal is output pin 11
channel 4’s waveform. The reduction of B+ corresponds to no focus cor-
and delayed in a chain of amps (IC5502 and Q5501). Driver transistors
rection at the left and right sides of the picture. However, dynamic focus
Q5508-9 and Q8022-23 buffer the signal as it travels from one part of the
correction does take place at the center of the picture when there is B+
D board toward the other near the FBT. The final DF Output transistor
output Q8016/Collector.
Q8018 applies the signal to T8002/pin 3.
PM3394, FLUKE & PHILIPS
In the following waveforms you can see the low going drive signal from
IC5511/pin 11 (ch 2) become inverted and delayed (ch 3). The final drive ch1
1
T

signal (ch 4) goes low to reduce the focus voltage at the right side of the ch2
2

picture. ch3

ch1
T
1
ch4

ch2
2

3
ch3

3
ch4
CH1!10.0 V~

CH2! 200mV~
4
CH3! 200mV~ AVG

CH4! 100 V= ALT MTB5.00us ch1+

CH1!10.0 V~

CH2! 200mV~
4

CH3!10.0 V~

CH4! 100 V= ALT MTB5.00us ch1+

 T8001
FLYBACK
TV SCREEN CRT
D BD. HV

HV CRT
CONV FOCUS
VOLTAGE
17

IC5502 13 Q5508,
OP AMP Q5509

DF FOCUS
2/2
11
* DRIVERS
1

CORRECTION T8002
C5509 R8082 DFT
4
AFC-PLS Q8018 6
H OUT Q5501 DF
Q5030/C Q8022, OUTPUT
C8058 3
2 Q8023
19 N L8005
DRIVERS 1
DATA 1 IC5502
IC5511 OP AMP D8017
DAC1
DQP
CONTROL
11 5 1/2
* Q8015
+135V

SW 91VDC
CXA202GAS Q8019,
CLK 2
14 Q8020 P
IIC 21 SWO C8051 DF PROT R8101
BUS 10 Q8016 C8060
SW 4.7
160V
VTIM CN5503/2 R8102
Y/C CRT DRIVE 22k SM CATEGORY 2026AS
IC201/54 DF ON - 0=ON, 1=OFF
* IC5502 = NJM2901M
DF - CHANGES FOCUS START

DYNAMIC FOCUS 15DTV 1268 10/10/00

54
 55

DF Switching Signals Service mode item “DFON” turns OFF the switching voltage from IC5511/
pin 14. This can be seen in the following chart that contains the DC
Channel Name Location Voltage
voltages of the output stage.
1 AFC-PLS IC5511/pin 19 10Vp-p
DF Output Stage Voltages
2 SWO (Switch control) IC5511/pin 14 0.3Vp-p (main)
DFON data = Q8018/C T8002/pin 3 T8002/pin 1
3 Switch Drive signal Q8016/Base 0.1Vp-p (main)
0 (DF is On) -14Vdc 89Vdc 91Vdc
4 Final DF Drive Signal Q8016/Collector 140Vp-p
1 (DF is Off) 0.3Vdc 0Vdc 0Vdc
The purpose of “DF Protect” transistors Q8019 and Q8020 in the switch-
ing path is unknown as of this writing.

Adjustment
The manual focus adjustment is located on the flyback (the only control).
Input a crosshatch and adjust the focus control until you can see the scan-
ning lines in the picture.
Dynamic focus can be turned ON/OFF and phase adjusted (start loca-
tion) in the service mode. Data group #7 with the heading “2026” con-
tains two items related to dynamic focus:
Service Mode Category 2026
Item Name Purpose
DFON Data 0 = dynamic focus ON
Data 1 = dynamic focus OFF
DF Positions IC5511/pin 14 switching pulses to change the
start of the dynamic focus points on the screen.
 T8001
FLYBACK
TV SCREEN CRT
D BD. HV

HV CRT
CONV FOCUS
VOLTAGE
17

IC5502 13 Q5508,
OP AMP Q5509

DF FOCUS
2/2
11
* DRIVERS
1

CORRECTION T8002
C5509 R8082 DFT
4
AFC-PLS Q8018 6
H OUT Q5501 DF
Q5030/C Q8022, OUTPUT
C8058 3
2 Q8023
19 N L8005
DRIVERS 1
DATA 1 IC5502
IC5511 OP AMP D8017
DAC1
DQP
CONTROL
11 5 1/2
* Q8015
+135V

SW 91VDC
CXA202GAS Q8019,
CLK 2
14 Q8020 P
IIC 21 SWO C8051 DF PROT R8101
BUS 10 Q8016 C8060
SW 4.7
160V
VTIM CN5503/2 R8102
Y/C CRT DRIVE 22k SM CATEGORY 2026AS
IC201/54 DF ON - 0=ON, 1=OFF
* IC5502 = NJM2901M
DF - CHANGES FOCUS START

DYNAMIC FOCUS 15DTV 1268 10/10/00

56
 57

DQP Circuit Corner Focus Correction DQP-- Signal Processing

Channel Name Location Voltage
Focus at the sides of a Wega flat screen picture tube was accomplished 1 DQP negative signal IC5511/pin 4 0.4Vp-p
with the Dynamic Focus Circuitry. Focus at the corners is corrected using 2 Amplified DQP- signal CN5509/pin 6 130Vp-p
a Dynamic Quadrapole circuit. Although they are independent circuits, a
failure in one will make it appear as if the other is also defective. There- Time base = 10usec/div
fore, both the Dynamic Focus and DPQ circuits must be tested when The waveforms in the following scope shot are made by IC5511/pin 6 and
there is poor focus on a portion of the screen. The DQP circuit is also applied to the QP coils at CN5509/pin 4.
used to correct for mis-convergence at the perimeter.
Circuitry c h1

IC5511 manufactures the corner focus correction signal that is amplified c h2

and applied to four coils placed at the neck of the CRT. There are two
signals marked Para 1 and Para 2 that output IC5511/pins 4 and 6. They 1

are amplified and applied to the four QP coils.

At power ON, Q5008 and Q5505 use C5027 to momentary disable the
DQP amplification in IC5504. This is so the beam will be unaffected by
incorrect voltages at start up. T

2
Q5502, Q5507 and IC5502 monitor the horizontal width (AFC-PLS from
Q5030) and corrects for focus if the width changes momentarily. This is
accomplished by changing the DC input voltage of IC5504/pin 2 propor-
tional to the width of the picture. C H 1 ! 20 0 m V~

CH 2 ! 10 0 V= M T B1 0 .0 us H xx
The waveforms in the following scope shot are made by IC5511/pin 4 and
applied to the QP coils at CN5509/pin 6. DQP-- Signal Processing
PM3394, FLUKE& PHILIPS
Channel Name Location Voltage
ch1
1 DQP positive signal IC5511/pin 6 0.4Vp-p
ch2

2 Amplified DQP + signal CN5509/pin 4 300Vp-p

1

Time base = 10usec/div

T
By comparing both output waveforms, we can see the resultant DQP cor-
2 rection signal (difference of the two waveforms) is not that complex.

CH1! 200mV~

CH2! 100 V= MTB10.0us Hxx

AFC-PLS IC5506 R5588 L5505 QP-
Q5030/C 19 PARA 1 4 2 DQP-AMP1 4 6
R5577 LA6500
VTIM 21
C5548
180k
CN5503/2 0.47
IC201/54 IC5511
DQP R5056 POWER ON
MAIN INHIBIT 3.5
CONTROLLER
+12V Q5008 Q5505 OHMS
CXA2026A
C5027
IIC BUS 1 SDA
FROM
IC701/28,31 2 SCL 1
PARA IC5504 L5504
2 6 2 DQP-AMP2 4 4
PWM R5554 LA6500 CN5509 QP+
9 18k
R5564 D5515 D5514 C5531
R5696 R5563
C5533 0.1

IC5502 ADJUSTMENT
C5614 AMP
Q5502
Q5507 SERVICE MODE: CATEGORY 2026AS
HORIZ. DQP FOCUS CORRECTION
AFC-PLS ITEM 1 - DQP - PWM LEVEL
Q5030/C ITEM 3 - DQPD - DC LEVEL
ITEM 4 - QPDV - VERT. MOD
ITEM 5 - DVS - TILT
ITEM 7 - DQPA - AMPLITUDE

DQP FOCUS CORRECTION 67DTV02 1282 9/29/00

58
 59
PM3394, FLUKE & PHILIPS

ch1

ch2
1

T
2

CH1!50.0 V~

CH2! 100 V= MTB10.0us- 1.18dv L xx

DQP-- Signal Processing

Channel Name Location Voltage
1 Amplified DQP - signal CN5509/pin 6 130Vp-p
2 Amplified DQP + signal CN5509/pin 4 300Vp-p
Time base = 10usec/div
Adjustment
The waveforms from IC5511 can be changed from the service mode to
affect the starting point of focus correction on the screen, the amount of
focus, and convergence. These items are found in the service mode
category 2026AS.
AFC-PLS IC5506 R5588 L5505 QP-
Q5030/C 19 PARA 1 4 2 DQP-AMP1 4 6
R5577 LA6500
VTIM 21
C5548
180k
CN5503/2 0.47
IC201/54 IC5511
DQP R5056 POWER ON
MAIN INHIBIT 3.5
CONTROLLER
+12V Q5008 Q5505 OHMS
CXA2026A
C5027
IIC BUS 1 SDA
FROM
IC701/28,31 2 SCL 1
PARA IC5504 L5504
2 6 2 DQP-AMP2 4 4
PWM R5554 LA6500 CN5509 QP+
9 18k
R5564 D5515 D5514 C5531
R5696 R5563
C5533 0.1

IC5502 ADJUSTMENT
C5614 AMP
Q5502
Q5507 SERVICE MODE: CATEGORY 2026AS
HORIZ. DQP FOCUS CORRECTION
AFC-PLS ITEM 1 - DQP - PWM LEVEL
Q5030/C ITEM 3 - DQPD - DC LEVEL
ITEM 4 - QPDV - VERT. MOD
ITEM 5 - DVS - TILT
ITEM 7 - DQPA - AMPLITUDE

DQP FOCUS CORRECTION 67DTV02 1282 9/29/00

60
 61

Convergence Circuit
1T

Concept
The purpose of the convergence circuit is to create a dynamic signal that
is applied to the convergence (CY) winding within the main yoke. The
convergence winding is positioned so the dynamic signal will move one or
two electron beams more than the third. This is how an electronic signal
2
can unite all three beams together on the screen. The convergence cir-
cuitry corrects at the four sides and right corners of the TV screen in this
TV.
CH1!1.00 V~ STOP ENV
Correction Correction CH2!5.00 V~ MTB5.00ms ch1+
areas areas
Convergence Output
Channel Name Location Voltage
TV screen
1. VTIM (Vertical timing) input IC5513/pin 3 1.8Vp-p
Convergence correction areas
Circuitry 2. Convergence Output CN5510/pin 3 10Vp-p
At power ON, convergence data stored in the Non-Volatile Memory IC707 Time Base = 5msec/div
is retrieved by Main uCom IC701 (not shown) and sent to IC5513 via the
I2C bus. Within ICI5513, this data shapes the vertical and horizontal
signal input to pins 3 and 14 and produces two outputs.
Adjustment
The convergence yoke signal is adjusted in the service mode. Data group
The H Stat output at IC5513/pin 8 corrects for left and right mis-conver-
#6 with the heading “D-Conv” has nine adjustment parameters that cor-
gence. The V Stat output at IC5513/pin 9 corrects for top and bottom mis-
rect for mis-convergence, mostly at the right side of the TV screen.
convergence. The two signals are combined externally and amplified by
IC5515 into a 10Vp-p waveform at the convergence yoke CN5510/pin 3.
IC5513’s input and output signals are listed in the chart:
IC5513 s Input / Output Signals
Name IC5513/pin Voltage Purpose
VTIM 3 1.8Vp-p, 4.8Vdc Input Vert sawtooth
ramp
AFC-PLS 14 10Vp-p, 0.74Vdc Input horiz pulse
Ref 5 5Vdc reference for IC5515
H Stat 8 100 mV p-p left/right conv. signal
V Stat 9 200 mV p-p top/bottom conv. signal
 VTIM D BD.
IC201/54 3 IC5515
STK390-910
AFC-PLS CY PART
14
Q5030/C 5V REF. OF MAIN
IC5513 5 1
+
R5693 H STAT YOKE
DY-CONV 8 3 3
CXA8070AP -
DATA CLOCK 16 9 2
1
IIC R5699 V STAT
BUS 17 8 4 CN5510

10 R5648
R5712 R5711
MAIN
+12V
+15V -15V
SOURCE

IC5003
+15V
12V REG

SERVICE MODE
CATEGORY D - CONV
9 ADJUSTMENT ITEMS

CONVERGENCE CIRCUIT 16DTV02 1272 10/10/00

62
 63
Horizontal Trapezoid Correction Circuit
Picture Tilt Correction
The trapezoid correction signal takes the same path the tilt correction DC
voltage did. This signal comes from IC201/pin 51 as a 60 Hz 0.3Vp-p
When flat screen picture tubes were first manufactured, lines that were
sawtooth waveform. IC5510 brings the signal level up to 2Vp-p for the
not straight were very noticeable. This meant additional pincushion and
main sawtooth plus 4Vp-p for the low going spike.
convergence circuitry was required to improve the picture quality.
If the yoke were a little off center, the slight tilt of the picture would also be ch1

noticeable. A picture tilt circuit was added to Sony flat screen Wega
ch2
TVs to correct for this tilt. The user can perform Tilt Correction from the
setup menu. The coarse adjustment is performed in the service mode by
changing the data in category 2150D, item 6 (NSCO).
The circuit required a DC voltage to be applied to a N/S coil suspended
about the perimeter of the yoke housing at the bell of the tube. Applying 1
2

a voltage to this N/S coil produces a magnetic field. The field offsets the
three beams as they emerged from the electron gun structure, rotating T

the picture. CH1 2.00 V=

CH2 2.00 V= MTB5.00ms- 1.32dv H xx

A sawtooth waveform is also added to this DC voltage for horizontal trap-
ezoid correction. Therefore, there is a DC voltage and a sawtooth signal Horizontal Trapezoid Correction Waveform
present at the coil. Both the DC level and sawtooth amplitude can be Channel Name Location Voltage
controlled in the service mode.
1 V Saw 1 CN201/pin 5 0.3Vp-p
Tilt Correction Circuit
2 N/S Coil CN5509/pin 12 6Vp-p
The tilt correction DC voltage and the horizontal trapezoid correction
Time base = 5msec/div.
sawtooth signal are created by IC201. The signal and DC voltage leave
IC201/pin 51 and are amplified by IC5510 before being sent to the N/S
coil. The voltages in normal operation and when the user has set the tilt Adjustment
to both extremes (+7) are shown in the chart.
Tilt - The DC voltage from IC201/pin 51 can be adjusted in the service
mode, as well as from the user’s setup menu. Access the coarse adjust-
Tilt correction Voltages
ment by locating category 2150D-1 in the service mode. Scroll down to
Location Name 0 rotation -7 rotation +7 rotation item number 6 - NSCO to change the tilt from the service mode.
CN201/pin 5 Output of IC201 4Vdc 5Vdc 3Vdc H Trapezoid - The sawtooth amplitude from IC201/pin 51 can also be
CN9102/pin N/S coil 0V -4.8Vdc 5Vdc controlled from the service mode, independent of the DC voltage. In the
12 same category as for tilt (2150D-1), scroll down to item 7 - HTPZ. Chang-
ing its data changes the signal amplitude and corrects for trapezoid dis-
tortion.
 N/S COIL

R5670 MAIN
+12V
PICTURE
A BD
TUBE
R5669
REAR
5
CN5509/
IC201 Y/C LA6500 CN9102
1 +
CRT DRIVE V SAW 1 R5678 4 12
CXA2150Q 51 - YOKE
5 2 0V
25 26 CN201/
3
CN5503
0.25V N/S
IIC 4V
BUS COIL
R5679 W BD.
C5601 38.2
DATA CLK1 OHMS
R5613
31 28
CLK O -12V 270
IC701 29 IC707 11
MAIN uCOM R5688
NVM
M306V2- 30 N24C8 R5705 D BD.
DX1A 1
DATA O

ADJUSTMENTS
USER: SET UP MENU - TILT CORRECTION
SERVICE MODE: CATEGORY 2150D-1
ITEM 6 - NSCO - 0-15
ITEM 7 - HTPZ - HORIZ. TRAPEZOID

PICTURE TILT CORRECTION 66DTV02 1281 10/10/00

64
 65

Vertical Pincushion Correction Circuit Vertical Pincushion Correction Signal

Channel Name Location Voltage

Concept 1 VSAWO CN201/pin 6 0.3Vp-p

The geometry on a flat screen picture tube is more critical than that on a
curved picture tube. This new circuit applies an electronic signal to a coil
at the CRT electron gun to straighten the top and bottom lines on a pic-
ture.
Straighten top
& bottom lines
using VPIN
adjustment
Circuitry
At power ON, data stored in the Non-Volatile Memory (NVM) IC707 is
retrieved by Main uCom IC701. IC701 distributes the data to various ICs
in the TV via the I2C bus. The Y/C CRT Drive IC201 is sent just the data
that pertains to it. Within IC201, a correction signal is made consisting of
mixed horizontal and vertical components. This signal is amplified by
IC5514 and applied to the pincushion coil.
The correction signals before and after amplifier IC5514 is shown in this
scope shot.
PM3394, FLUKE & PHILIPS
2 Pincushion CN5509/pin 2 0.5Vp-p = main waveform
Output 3.5Vp-p including spike
Time base = 5msec/div.
The Vertical Pincushion coil resistance is 18.9 ohms between CN9102/
pins 1 and 2 without the plug connected.
Adjustment
The vertical pincushion signal is adjusted in the service mode with the aid
of an external cross hatch generator. Data group #4 with the heading
“2150D-1” contains the VPIN adjustment in its fifth item. The fourth item
VCEN also changes the DC level of the VPIN signal.
VPIN must be adjusted in all three deflection modes:
1. Full - (normal NTSC) 4:3 signal input.
2. V Comp1 - (480p) 16:9 video 5 or 6 input.
3. V Comp2 - (1080i) 16:9 video 5 or 6 input.

ch1

ch2

CH1! 200m V~ STOP

CH2!1.00 V~ MTB5.00ms L=2 ch1p

 R5698 MAIN
9V
A BD.
R5697 IC5514
V PIN OUT LA6500
5
CN5509/
IC201 Y/C 1 CN9102
CRT DRIVE + V PIN +
V SAW O R5700 4 2
CXA2150Q 50 6 2 - 0V
25 26 CN201/
0.25V 3
CN5503
IIC 4V
BUS R5615 W BD. CRT
C5616
DATA CLK1
R5710
31 28
CLK O -12V 270
IC701 29 IC707 1
MAIN uCOM NVM SLIGHT V PIN -
M306V2- 30 N24C8 BOW R5704
DX1A INWARDS 1
DATA O
D BD.

SM CATEGORY 2150D-1
TV SCREEN 5 ITEMS -
ADJ. IN ALL 3 MODES:
1. FULL (NORMAL)
2. V COMP1 - 480P 16:9
NO CORRECTION
3. V COMP2 - 1080I/VERT ENHANCED

VERTICAL PINCUSHION CORRECTION CIRCUIT 20DTV02 1271 10/10/00

66
 67
The waveforms of this stage show the basic operation from sync input
Vertical Process (ch1) through drive (ch 2) to feedback (ch 3 & 4).
The vertical sync source selection on the B board is new, but the oscillator c h 3 : d c = 2 6 .2 m V
ch1
and output stage is traditional. ch4 : dc = 16 3m V
T
ch2

Vertical Sync 1

The vertical frequency is 60Hz but the sync is selected by IC4313 from ch3

one of three sources:

ch4
1. MID circuit when Progressive scan is selected by the user (IC4313/ 2

pin 13 input). 3
2. Main video input from input switch IC3048 when interlace scan is se-
lected (IC4313/pin 1 input).
3. Sub video input from sub picture switch IC3001 when this picture is C H 1 !2 .0 0 V =
the only one selected (from the Twin mode). (IC4313/pin 2 input) C H 2 !2 .0 0 V =
4
C H 3 !1 .0 0 V ~

Switch IC4313 selects one input that outputs pin 14. The selection is C H 4 !2 .0 0 V = C H P M T B 5 .0 0 m s ch1 -

based upon control voltages from MID uCom IC3090 and the Main uCom Vertical Stage Waveforms
IC701 input IC4313/pin 9-11. Channel Name Location Voltage
1 Mid VS (sync) CN003/pin B15 3Vp-p
Vertical Oscillator
2 V Drive + CN5503/pin 4 1.8Vp-p
The vertical oscillator inside IC201 starts and outputs pins 52 and 53 when
Main 9V is applied to IC201/pins 55 and 61. Data need not be present for 3 Protect signal CN5505/pin 7 1Vp-p
vertical drive to output like other Y/C “Jungle” ICs. 0.8Vdc
4 Timing CN5501/pin 1 3.5Vp-p
Vertical Output Time base =5msec/div.
The vertical stage is traditional. The vertical oscillator signal is amplified
in IC5004 and used to drive the vertical deflection yoke. Vertical Compression / 16:9 Enhancement
To make sure the vertical stage is operational, a sample of the vertical When a 16:9 video signal is input from video 5 or 6, the aspect ratio is
signal is returned to IC201/pin 35. If IC201 detects a loss of vertical pulses, incorrect for this 4:3 TV screen and the picture will appear too tall. The
it blanks the picture. If the loss remains for two seconds, IC201 sends vertical is compressed slightly to maintain the correct aspect ratio. The
data to Main uCom IC701 to shut down the set and store the vertical user chooses this compression from the menu. In the setup menu under
failure code. 16:9 enhancement, he can choose AUTO or ON. In AUTO, the MID
circuit on the D board detects the higher horizontal frequency associated
Vertical pulses from IC5004/pin 3 are sent to the MID uCom IC3090/pin with a 1080i 16:9 picture and reduces the vertical sweep. A 480p signal
35 to identify the end of the scan for interlace/progressive scan timing. can be in either aspect ratio. Therefore the user must manually select ON
for the vertical compression.
 V SYNC
PROGRESSIVE V SYNC FOR
V SYNC FROM 13 OSD MAIN
IC3408 uCOM
IC701/97
VTIM (INTERLACE) 1 IC3413
FROM IC3048/15 YCT MAIN SYNC SW A BD. MAIN
SN74LV 9V
SEL V OUT(SUB PIX) 2 CN3205/
4053A CN003
FROM IC3001/23 COMP J-F
42 55
14 C15 B15
SYNC SEL 10 MID 61
IC3090/10 MID uCOM
9 11 VS IC201 VFB TO
TH CONT/X SW MID uCOM
Y/C
IC701/52(A BD.) B BD. IC3090/35
CRT DRIVE
Y/C CRT DRIVE (B BD.)
CXA2150Q
FOR PROG./
4 53 + INTER TIMING
D BD. V DRV
3 52 - PROT
CN201/ 35
CN203/ CN706/
CN5503
CN5505 CN5501
7 1
R5029
4Vp-p
R5046 R5052 R5599 V PROT
TH5001 1Vp-p
7 1 1.8 1.5 10k
-15V 4 YDY
IC5004 V OUT 6
TIMING
(D BD.)
STR9379 CN5002 +15V
5 5
1 6 3 L5001
+15V N
(D BD.) + Q5005
D5002 R5023 D5001
5.1V R5018

VERTICAL PROCESS 13DTV02 1269 10/6/00

68
 69
P M 3 3 9 4 , F L U K E & P H IL IP S
To keep the information in the vertical blanking area hidden in the vertical
c h 2 : p k p k = 1 .5 5 V
area above the picture, the vertical drive waveform from IC201 is altered. ch1
c h 2 : fre q = 6 0 .0 H z
After the electron beam retraces to the top of the screen, normal down- T

ward scan begins. After the blanking interval, the beam drops down the ch2

screen before resuming sweep. The vertical ramp’s amplitude is also 1

reduced. This can be seen when comparing the normal and compressed
vertical waveform. Notice there is an irregularity at the beginning of the
vertical ramp in the compressed vertical mode.
2

PM3394, FLUKE & PHILIPS

ch1
ch2: pkpk= 1.78 V

ch2: freq= 122 Hz

Ramp
T
Irregularity
ch2

C H 1 !2 .0 0 V =

C H 2! 500m V~ M T B 2 .0 0 m s - 0 .9 0 d v c h 1 +

Normal 2
Vertical Drive Signal - Reduced (16:9 Mode)
vertical Channel Name Location Voltage
ramp 1 MID VS (sync) CN3205/pin C15 3.5Vp-p
CH1!2.00 V=
2 V Drive (osc) CN5503/pin 4 1.3Vp-p
CH2! 500mV~ MTB2.00ms- 0.90dv ch1+

Time base = 2msec/div.

Vertical Drive Signal - Normal
Channel Name Location Voltage
1 MID VS (sync) CN3205/pin C15 3.5Vp-p
2 V Drive (osc) CN5503/pin 4 1.5Vp-p
Time base = 2msec/div.
 V SYNC
PROGRESSIVE V SYNC FOR
V SYNC FROM 13 OSD MAIN
IC3408 uCOM
IC701/97
VTIM (INTERLACE) 1 IC3413
FROM IC3048/15 YCT MAIN SYNC SW A BD. MAIN
SN74LV 9V
SEL V OUT(SUB PIX) 2 CN3205/
4053A CN003
FROM IC3001/23 COMP J-F
42 55
14 C15 B15
SYNC SEL 10 MID 61
IC3090/10 MID uCOM
9 11 VS IC201 VFB TO
TH CONT/X SW MID uCOM
Y/C
IC701/52(A BD.) B BD. IC3090/35
CRT DRIVE
Y/C CRT DRIVE (B BD.)
CXA2150Q
FOR PROG./
4 53 + INTER TIMING
D BD. V DRV
3 52 - PROT
CN201/ 35
CN203/ CN706/
CN5503
CN5505 CN5501
7 1
R5029
4Vp-p
R5046 R5052 R5599 V PROT
TH5001 1Vp-p
7 1 1.8 1.5 10k
-15V 4 YDY
IC5004 V OUT 6
TIMING
(D BD.)
STR9379 CN5002 +15V
5 5
1 6 3 L5001
+15V N
(D BD.) + Q5005
D5002 R5023 D5001
5.1V R5018

VERTICAL PROCESS 13DTV02 1269 10/6/00

70
 71
The output of IC3201 is sent to IC3202. IC3202 is an analog switch that
Audio Block Diagram only handles audio. The input choices are:
• Main signal
Features • Sub signal
The XBR400 audio section features:
XBR400 Series Audio Section Features (Menu selection)
• Video 5

Feature Description Circuit location

• Video 6
Selection of Main Vs Sub sound is used in the Twin mode. The outputs
Steady Reduces dynamic range to Audio Processor go to the rear monitor output jack and the S board for TruSurround Sound
Sound prevent drastic volume changes IC7001 processing.
when switching channels or when
a commercial comes on.
TruSurround Simulates a 3D sound using the IC4101, IC4103 S Board
Sound stereo signal and only the TV The L/R channel audio is applied to both TruSurround IC4101 and Switch
speakers IC4102. The TruSurround IC4101 outputs the L/R audio if the TruSurround
Simulated Adds echo to a Mono signal to Audio Processor mode is not selected.
Surround simulate a larger room. IC7001 When TruSurround is selected, the second output from TruSurround
Separate Tweeter is located at the bezel for IC4101 to D/A IC4103 is used. IC4103 converts the digital data to a
Woofer and better HF dispersion. control signal that instructs switch IC4102 to return L/R audio to a differ-
Tweeter ent part of IC4101 for TruSurround sound processing. The output of IC4101
15Watts/ IC packages. Power comes from IC7002 & IC7005 is into the Audio Processor IC7001 on the A board.
channel fusible resistors on the D board.
RMS
A Board
Fixed or Output is present only when the IC7001
IC7001 handles the simulated and steady sound processing. It also ad-
Variable speaker is switched OFF from the
audio menu. The fixed or variable level justs the volume, treble, bass, and balance based upon the user com-
Output can be chosen mands. Its output is split into three paths. The speaker path is to a high
and a low pass filter, then to the 15W power amplifiers IC7002 and IC7005.
Signal Path The third path is through buffer IC7007 to the TV’s rear panel audio out-
B Board put jack. This path is muted (not shown) when the TV speaker is ON. If
the user turns the speaker OFF from the menu, it is implied the user has
IC3201 (CXA2069) is an analog switch that selects both audio and video. an external amplifier or audio processor connected to the rear audio jack
Using I2C data from the Main uCom IC701 (not shown), IC3201 can se- so this jack is unmuted (enabled). The user must then select a variable or
lect between the following: fixed output level.
• Main Tuner
• Sub Tuner
• Video 1 - 4
 W-L SPEAKERS
LINE OUT
IC7007 A BD.
BUFFER
MONITOR NJM4558
CN7008
OUT 7 L
INPUTS: IC7002 H-L
IC3203 POWER AMP
MAIN BUFFER TA8216
NJM4558 H-R
SUB IC3201 (HIGH PASS) 3 R
AUDIO 1 ANALOG
SW MAIN IC7006
AUDIO 2 (A/V) LOW PASS
SUB IC3202
AUDIO 3 CXA2069 NJM4558
MON ANALOG IC7001
AUDIO 4 SW AUDIO
AUDIO 5 AUDIO PROCESSOR 5
AUDIO 6 TEA6422 BH3868 IC7005
POWER AMP
A14 DATA/CLK TA8216 W-R
B BD. A15 1
CN3205/CN003 IIC BUS
5 7 9 10
U BD. CN7001

THICKER CN4101
5 7 9 10
LINES
DENOTE S BD.
L/R
SIGNAL IC4101 TRUSURROUND NJM2180
PAIR

IC4102 IC4103
ANALOG SW D/A IIC BUS
NJU4066 CXA1315

DX1A AUDIO BLOCK DIAGRAM 17DTV02 1270 10/10/00

72
 73
OSD Diagnostics
Self Diagnostic Block
In addition to the blinking Stby LED, the Main uCom records the number
The Self-Diagnostic circuit is a program of the Main uCom IC on the A of times the failure occurred. This is useful when the user complains of
board. This program monitors seven general faults that result in one or an intermittent shutdown.
more of the following:
Access the Diagnostic Mode
♦ TV shutdown (AC relay is turned off);
♦ TV Latched OFF** (AC relay is held off); or To enter the test screen, first press these remote control buttons one at a
♦ A dark picture (no RGB signal). time: Display, 5, Vol —, Power On.
As an indication of failure, the Main uCom blinks the Standby LED a num- The screen will list the circuit monitored and the number of times the
ber of times, pauses, then repeats. failure has occurred.
Clear the OSD Diagnostic numbers
Faults Monitored by Main uCom IC
To clear the number of failures from the test screen press:
Stby Symptom Bd Monitored Test point Normal
LED Circuit Voltage Press 8, Enter.
(verification)
Blinks Front of TV
0X Shutdown D +200V Q8009/C 0.1Vdc
OCP (HV)
2X Shutdown D +135V CN6506/pin 0V
D6017
OCP 8 CN6506
3X Shutdown A Unreg 7V D6017/C 0V
OVP
3X Shutdown D +135V CN6506/pin 0.1V 8 IC6007
OVP 7
4X Shutdown D V Out CN5505/pin 0.78V
Loss 7 Q8009
5X Blanking C/A IK balance CN202/pin 8 3 pulses 10
/G2 in vertical FBT CN5505
adj interval.
6X Shutdown A Set 5V IC6007/ 5.0Vdc
OCP Output
D Board A Board
7X Shutdown D H Out CN5505/pin 0V
IC6007
OCP 8
** TV latched OFF. Press power button twice to turn TV back on

I O G n/c
 UNREG.
UNREG. STANDBY 7V
D BD. 3X 7V LED
OVP C BD.

IC6007
5V REG.
+135V D6017
3X
OVP LOW B RGB
D6018
OCP SET 5V TO CRT
7
6X CN202/
+135V CN9001 IK SIGNAL
2X 8
OCP WHITE BAL
DATA/ 5X
IC701 IC201 FAILURE
CLK
8 MAIN Y/C
0X 0X V OUT
uCOM CRT 7
CN6506/ 4X LOSS
Q8009 POWER OFF DRIVE
CN703 H OUT
+200V LATCH OSD 8
OCP D BOARD RGB CN203/ 7X OCP
(HV) CN5505
1

CN6504/
CN702 D BD.
AC
RELAY
ON/OFF

X
NUMBER OF TIMES THE
STANDBY LIGHT BLINKS
AFTER SHUTDOWN

SELF-DIAGNOSTIC BLOCK 10DTV02 1260 10/4/00

74

Self Diagnostic Circuit
When the TV shuts down and the standby LED blinks, the Main uCom
IC701 knows which failure activated the shutdown. The number of times
the Standby LED blinks indicates the problem board or section.
Shutdown - Standby light does not blink
Circuit - The current on the +200 volt line is monitored by R8043 and
Q8009. This 200-volt line supplies the High Voltage Converter stage,
which feeds the flyback. A short in the flyback or excessive high voltage
will demand sufficient current to shut down the TV. Since there is no
connection to the Main uCom IC701, the standby LED will not indicate
this failure.
Unstable standby voltage or a defect in the basic latch circuit (Q6530 and
Q6532) will also cause the TV to shut down without the standby light
blinking. This last problem is rare.
Testing - To determine if the +200V line to the HV Converter stage is
causing shutdown, monitor the voltage at Q8009/Collector at power ON.
The voltage should not rise above 0.2Vdc at power ON. A higher voltage
means the problem is on the D board in the Converter.
Shutdown - Standby light blinks two times
There are two +135V OCP monitoring circuits. The first circuit will cause
the Standby light to blink two times and the second will cause the light to
blink seven times. Both sensing and output circuits are on the D board
but the indicating circuit is on the A board.
Circuit - R6598, R6591, Q6520, Q6521, and Q6524 monitor the current
on the +135V line from the Secondary Power Supply. The +135 volt line
supplies:
♦ Velocity modulation (V) board
♦ Horiz Output (Q5030) and PWM (Q5003) stage (D board)
♦ The HOT supplies +200V to the RGB Output ICs (C board).
Testing - The blinking LED indicates the failure, but the problem could be
in one of three locations: The H. Output/PWM stage, the sensing circuit
on the D board, or the sensing circuit on this A board. Verify this problem
75
by monitoring CN6506/pin 8 as you power ON. If the voltage does not
rise above 0v at power ON, the problem is not on the +135V line. If the
voltage reaches 1.2V, disconnect the V board and try again. If the CN6506/
pin 8 voltage still rises to 1.2V, test the H Output and PWM transistors or
replace the entire D board.
Shutdown - Standby light blinks three times
Circuit - There are two possible causes for this LED indication caused by
excessive voltage. Two power supply voltages are monitored, +135V on
the D board and Unreg. 7V on the A board. On the D board, the maxi-
mum voltage on the +135V line is +140V. This is monitored by IC6505
and Q6522. On the A board, the maximum voltage on the unregulated 7V
line is 8.2V. This is monitored by D6014.
Testing - The problem can be on either the A or the D board. Locate
D6017/Cathode or D6014/Anode and monitor this voltage as you power
the TV. If the voltage rises above 1V, the problem is in the A board’s
power supply (regulation). To test the power supply on the D board, monitor
CN6506/pin 7. If this voltage rises above 0.6Vdc, the problem is on the D
board.
Shutdown - Standby light blinks four times
Circuit - A vertical failure because of the output IC or power supply (both
on the D board) will cause the Y/C, CRT Drive IC201 to send emergency
data to Main uCom IC701. IC701 turns the TV by opening the AC relay
(IC701/pin 69 goes LOW).
Testing - Measure the +15v and -15V to the vertical output IC5004/pins 2
and 4 before you suspect the IC5004 itself.
Blanking - Standby light blinks five times
Circuit - The Ik signals are measured by Y/C, CRT Drive IC201 and are
used to adjust the RGB gain to maintain color balance. As the picture
tube ages, the Ik signals may fall below the threshold for automatic bal-
ance and mute/blank the picture.
Testing - Increase the G2 control on the CRT’s C board. If that does not
return cathode current to within operating range so the picture will ap-
pear, examine each filament to see if it is lit.
 D BD. UNREG.7V
A BD. UNREG.7V
R6598 R6015 (PRI P.S.)
+135V +135V SOURCE
(SEC P.S.) 1k
D6014
D6018
7V
R6591
R6593 STBY 5V R6019 IC6007
D6017 5V REG.
Q6520, Q6524 4.7V
Q6521 CN6506/
P CN703
OCP 43 SET 5V
8 44 OCP
SOURCE
R6612
IC701
MAIN
R6602
1 +15V uCOM
IC6506 D6501 STANDBY
OVP 48
LED
P
Q6522 7 45 OVP
D6537 OVP OCP
+200V
(SEC P.S.) Q8009 Q6530, DAT O
30
R8043 OCP Q6532 TO/FROM
1 OHM D8003 LATCH YC/, CRT
CN6504/ DRIVE
CLK O
CN702 29 IC201/26,27
1 69

200V TO AC
HV CONV. Q6527 RELAY
AC TO
+200V/
AC FROM Q6501 +135V
F BD. AC RELAY POWER
SUPPLY

SELF-DIAGNOSTIC CIRCUIT 1/2 11aDTV02 1258 10/3/00

76
 77
Then use your scope to examine the signal to the cathode. Go to CN9001/ Q214 is turned on for five seconds at power ON to permit comparator
pins 1, 3 and 5 to see if there is a signal coming into the C board. Next IC5007 time to stabilize.
check the signal at the CRT cathodes. If they are present, check the IK Testing - If the Standby light blinks two or seven times, the problem is
signal from CN9001/pin 8 of the C board. You should see three pulses most likely on the D board where the sensing and Horizontal Output stages
and be able to change the level of the signal with the G2 control. If you are. On the D board, if the Horizontal Output (Q5030), PWM (Q5003)
get about 1Vp-p pulses at pin 8, this is the normal output from the CRT/C transistors, and video output ICs (C board) are good, suspect the compo-
board so the problem is on the A board about IC201. nents in the sensing circuit (same board). The sensing parts are Q5004,
IC5007 and Q5018.
Shutdown - Standby light blinks six times Verify that this circuit is causing the shutdown by disconnecting the H.
Circuit - IC701/pin 43 monitors the Set 5V supply from the power supply Output Transistor Q5030 and monitor the voltage at CN5505/pin 8 as you
on the A board. This voltage feeds almost all the boards. A short on the power ON. If this voltage rises above 1 volt, this +135V OCP circuit is
Set 5V line will cause IC701 to shut off the AC relay (IC701/pin 69 goes responsible. Suspect Q214 on the A board and the following main parts
LOW). on the D board:
Testing - At power ON, measure the “Set 5V” at regulator IC6007/Output R5013, Q5004, IC5007, delay cap C5006, Q5018.
on the A board. The trip voltage is 3.7Vdc. If this voltage remains low at
power ON, unplug the B board within the A board and power ON again. Bridge Connectors
10 1
Shutdown - Standby light blinks seven times CN6505 CN6006
There are two +135V OCP monitoring circuits. The first circuit will cause 6 1 1
the Standby light to blink two times and the second will cause the light to CN6501 8 Hot
6
blink seven times. Both sensing and output circuits are on the D board, CN6504 CN702 Ground
but the indicating circuit is on the A board. CN6005
1
Circuit - The second OCP circuit monitors the current through the PWM 11
IC
Output (Q5001-3) that supplies B+ voltage to the H. Output transistor CN6506 CN703 60
Q5030. When there is excessive current drawn by the Horizontal Output 1
07
stage, Q5018 turns OFF, permitting IC201/pin 34 to rise to a threshold of 10
1.2Vdc. IC201 blanks the picture to prevent a CRT line burn and sends A
CN5503 CN201 Board
data to IC701/pin 30 to shut down the TV. D
Board 1
Normal Operating Voltages 10
IC6007
Location At power ON Operating CN5505 CN203

IC5007/pin 8 0.07V 0V 1 O
8
IC5007/pin 9 3V 3V
CN5501 CN706
IC5007/pin 1 2.6V 2.6V
1
Q214/base 5V for 5 seconds 0V I O G n/c
Back of TV
 +12V
A BD. +12V C BD.
CN202/ R9006
CN9001 Q9001 R9068
58 8 R9036
C219 P IK
R9065
0.068 FROM
25V R9008 D9002
R9012 R9041 IC9001/5,
IC9002/5,
DATO R9042 IC9003/5
FROM 25
IC201
IK
MAIN
Y/C, MAIN
uCOM CLKO CRT 9V
IC701 26
D BD.
DRIVE L5001 CN5002
IC5004
R250 R5599 V OUT 5 6
R249 10k OUT
35 7 5
V R5046 R5052 V
CN203/
PROT CN5505 1.8 OHMS 1.5 OHMS +135V YOKE
MAIN Q5004
34 8 R5013
12V OCP
R5104
IC5007
Q5018 COMPARATOR
H PROT Q5001
PROT Q214 - 8 Q5002
1 C5006
MUTE N Q5003
N + 9 10
MAIN PWM OUT
uCOM R5125
IC701/54 MAIN HDT
9V R5108 T5001/1
R5108 H OUT
Q5030

SELF-DIAGNOSTIC CIRCUIT 2/2 11bDTV02 1259 10/3/00

78
APPENDIX
 i

Service Mode Display Service Group Service

Data Video 5
Service Item
Service Mode Access (same as other Sony TVs): 480i
Point the remote control at the TV and press the following buttons:
Display, 5, Volume +, Power ON. WLS = 0

Display
The service mode display has more information.
F/A Flag: 11110111
WSL CBA Flag: 11111111
At the center of the service screen is a Weak Signal Level (WSL) number.
This number is similar to the AGC level in older TV sets. The lower the
Memory Check
WSL number the stronger the TV signal. 0 is a strong station and about
255 corresponds to snow. When a video input is selected, the WSL num- In the service mode you can check the condition of two of three NVM ICs
ber is fixed at 0. (memories). Press the #2 button repeatedly until the Service Group = ID.
At the lower right, G = Good. NG = No good.
480i/480p/1080i Video Format
When Video 5 or 6 is selected, the input format is shown at the right side ID 0 89 Service
of the display. ID0 WSL=0 480I
The video format is detected by the MID circuit when measuring the hori-
zontal frequency of the signal input. The default format is 480i when
there is no video signal input.
Main uCom number A Board NVM
Input signal Horizontal Frequency Main uCom version NVM G G D Board NVM
Standard NTSC 480i 15,734 Hz
High Resolution 480p 31.5kHz Geometry Adjustments
High Resolution 1080i 33.75kHz The geometry adjustments have three memory locations for each item in
the service menu.
Bottom Flag numbers • 480i standard NTSC
These numbers are added in manufacturing to identify where the boards • 480p 16:9 aspect ratio
come from and when they were made. The information is used for qual- • 1080i 16:9 aspect ratio
ity control purposes. After performing the adjustment in the 480i standard mode, change the
user setup menu to 16:9 Enhanced Mode. Selecting ON reduces the
vertical for the 1080i mode. Perform the adjustment again. The middle
480p 16x9 mode requires a generator to access.
12.2 - 12.7GHz S Video
Video
Decoder NTSC Encoder
MPEG 2 Composite
Video

video
DSS Dish
Ch 3/4 RF
Modulator
Output

Tuner Transport audio video

Demultiplexer
950-1450Hz IEEE 1394
Interface
(i-LINK)

audio

Audio Decoder Analog Audio

SMART
card Micro Dolby AC-3
Optical Out
(plug in) (Digital)

access card RJ11 phone

jack

Low speed data

(9 pin D-sub)

DIGITAL SATELLITE SYSTEM CONVERTER BOX 41DTV02 10/3/00

ii
 iii

Antenna Composite Video

VIDEO
Decompression S Video
MPEG 2

or Tuner VSB Demodulator

Componet Video (Y,

Pb, Pr)
Format Decoder
/ Down
Conversion

Transport Packet
Demultiplexer Analog L&R

AUDIO
Cable signal Digital Optical
Decompression
feed Port
Dolby AC-3

Micro

DTV SET TOP BOX 9/13/00


IEEE-1394
Overview
IEEE-1394 is high-speed digital interface that can be used by many types
of products, including computers and consumer electronics. It uses trans-
action-based packet technology to communicate between devices. This
standard was developed to help bridge the gap between PCs and con-
sumer electronic products.
Advantages
The IEEE-1394 has been chosen as the standard interface for digital con-
sumer products because of its many advantages. Listed below are sev-
eral of these advantages:
ƒ It is a hot pluggable and unpluggable system. Devices may be added
or removed at any time and their presence or absence will be recog-
nized by the system.
ƒ It is a non-proprietary standard adapted by the Institute for Electrical
and Electronic Engineers. There are no licensing problems at this
time to stop companies from adapting this format.
ƒ It allows for flexible hookups and easy connection. One thin cable
between devices does it all. The system allows for daisy chaining up
to 63 devices together at one time and also supports branching. It is
Plug and Play and does not require ID jumpers or switches. There is
no need for terminators.
DIGITAL
PC PRINTER CAMCORDER
VCR
TYPICAL IEEE1394 HOOK-UP
iv
ƒ Peer to peer communications are possible. Any device should com-
municate with any other device without the need for a hub or a PC to
be connected.
CAMCORDER CAMCORDER
PEER TO PEER CONNECTION
ƒ The system uses scalable architecture that will allow older, slower
devices to communicate with newer, faster devices at the slower rate.
Different combinations of faster and slower devices can be used on
the same bus.
Hardware
There is hardware currently available to support speeds of 100, 200 and
400 Mb/s (Megabits per second). These speeds are fine for digital video
since it has a data rate of 30 Mb/s. Data rates of 800 and 1600 Mb/s are
already scheduled for release. A data rate of 3200 Mb/s is in the planning
stage.
IEEE-1394 consists of three layers of hardware called the physical, link
and transaction layers. These components may be found in a single IC or
in several ICs. These layers will perform the same function regardless of
how many ICs there are. A description of each layer is listed below:
ƒ Physical Layer – Provides the electrical and mechanical interface
between a device and a connector. This layer also provides initializa-
tion and arbitration between devices. There is a built-in arbitration
subroutine that will make one of the devices the bus master. This
device will assign IDs to the nodes (devices connected) and control
traffic.
ƒ Link Layer – The link layer handles all data packet transmissions and
receptions. The data can be either asynchronous or isochronous.
 v
ƒ Transaction Layer – Manages asynchronous data protocols. This
layer is also responsible for communicating between a device that is
using IEEE 1394, such as a digital camcorder or a capture card, and
the link layer. This would be the system control IC in a camcorder and
the PCI bus in a PC.
ƒ IDs Cleared - All previous ID information is erased.
ƒ Tree ID - The device, which is the bus master, assigns each node a
specific address. This is called the Tree ID Process.
ƒ Self-ID - After IDs have been assigned, the system allows time for
each device to identify itself to the other nodes in the network.

MODE
Multi-Speed Transactions
TRANSACTION
DATA
BUS
LAYER The IEEE-1394 allows for data transmission speed to vary over the net-
work. If necessary, a faster device will change its speed to communicate
with a slower one. The paths taken between devices also limit data rates.
In Example A below, the PC or scanner would have no trouble communi-
cating with the camcorder at a rate of 100 Mb/s. However, the scanner
could not communicate with the PC at its top data rate of 200 Mb/s be-
VIDEO cause the path between the two contains a 100 Mb/s device (the
AND LINK PHYSICAL
AUDIO LAYER LAYER camcorder). The maximum data rate that can be achieved through an-
DATA
other device is limited to the speed of that device. In example B, the PC
EXAMPLE: IEEE1394 INTERFACE IN CAMCORDER
and the scanner would be able to communicate at the scanner’s top rate
Protocol of 200 Mb/s. It is very important that when an IEEE-1394 network is set
up that care is taken to properly place devices that need to communicate
with each other at top speeds.
Data Transfer
There are two types of data transfer possible using IEEE-1394. They are
as follows:
PC CAMCORDER SCANNER
ƒ Asynchronous – This is a memory mapped system. Each packet of 400 Mb/s 100 Mb/s 200 Mb/s
data is sent to a specific address to be stored and buffered by the
recipient. An acknowledge signal is sent when the data is properly
received. BANDWIDTH LIMITED BY SLOWER DEVICE
ƒ Isochronous - Isochronous data needs to be sent and received at a
steady rate that is in close timing with the ability of the receiving de-
vice to process the data. For example, if a digital camcorder pro-
PC SCANNER CAMCORDER
cesses data at approximately 30 Mb/s, then the receiving device must 400 Mb/s 200 Mb/s 100 Mb/s
be able to use this data at the same rate. Data is essentially broadcast
at a predetermined rate and not checked for accuracy.
BANDWIDTH NOT LIMITED BY SLOWER DEVICE
Dynamic Node Addressing
Each device, called a node, is assigned a specific address. This occurs
when a bus reset occurs or a new device is added to the system. Three
steps occur when these events occur:
Cable Technology Trade Names
There are a few trade names associated with the IEEE-1394 standard.
Wire The most notable are Fire Wire, which is an Apple trademark and
A standard six-wire cable is used by the PC industry as an IEEE-1394 i.LINK, which is a Sony trademark.
connection. There is also a four-wire connection used by Sony and other
manufacturers on digital camcorders and similar devices. The six-wire Current Products
cable contains B+, Gnd, and one differential pair for transmitting data and A brief list of products that use IEEE-1394 are:
one differential pair for receiving data. The four-wire cable only contains
the two differential pairs for data. There are adapters available if one ♦ DV Camcorders
device uses a four-wire cable and other uses a six-wire cable. ♦ D8mm Camcorders
♦ High-Resolution Digital Cameras
♦ HDTV
♦ HDTV Set-Top (Converter) Boxes
♦ DSS (Digital Satellite System) Boxes
♦ Hard Disks
♦ DVD-ROM Drives
♦ Printers
♦ Scanners

Future Developments
CABLES IEEE1394 seems poised to take its place as the home networking stan-
Connector dard of the future. Its high speed and ease of use are part of the keys that
may one day make it the bond between all the components in your home.
The connectors are simple, sturdy and reliable. They are designed with
the contacts inside the connector to reduce corrosion and the risk of shock. Sony, along with other industry leaders, is working on a standard called
They are childproof, if there is such a thing, and are based on the Nintendo HAVi. HAVi, which stands for Home Audio Video Interoperability, would
NES™ connector. be an “open architecture” system. This means that software, application
programming interfaces and communication protocols will allow all digital
electronic components to work together regardless of manufacturer. This
might mean that you could control your DTV set top box, digital audio
system and the temperature of your refrigerator all from one central loca-
tion. The amount of products that may use this system is limitless. We
are heading for a digital future and it seems that IEEE1394 will be a large
part of it.
Fire Wire is a trademark of Apple Computer Inc.
i.LINK is a trademark of Sony.
CONNECTORS

vi
 vii

[C]
CN9001

DX-1A
ANT
CN9002

CHASSIS
TO DY HV LEAD

SW CN9102 FOCUS LEAD

[W]
CN9103(N/S) Put one loop

ASSEMBLY MAIN
CN9101 in HV Lead
and secure
with purse lock
[ BC ] 9

SUB
[U]

CN603
AC CORD

CN607
[B] CN706
BUSCONN

DGC CN5501
CN605 CN202
CN203 DY CONN
CN204 CN5505 CN5002
CN3204 CN5003
CN201 to [C] (G-2)
CN5503

CN703
CN6506
[ D] HV REG.

[S]
BLOCK
(Optional)
CN6504
CN606 CN702
CN707
TO

[A]
CL701 CN6006 CN5510 SPEAKERS
CN6501 to CY 12mm
CN6505 Purse
)
CN7004 Lock
CN (38mm
CN6005 6503 CN6502 CN5005 height)
CN7003 CN701 to [VM]

TO
SPEAKERS

[HA]
CN4503 CN4301

[HB]
 Board Replacement

Board Removal Functions Possible Failure After board replacement

Symptoms
D Primary Power Supply Shutdown ♦ Transplant memory IC5501 containing
Slide chassis assembly back away from the (+200V, +135V) Sides bowing in deflection parameters.
pix tube. Protection latch circuit ♦ Adj Focus (on FBT).
Remove 7 screws securing the board. HV Regulator circuit ♦ Enter the service mode and perform touch
Slide the board toward the pix tube and tilt Corner focus circuit up geometry adjustments to D-
up to access the flyback. Conv/CXA8070 (group #6) and
Top/bottom pincushion
CXA2026AS data (group #7)*.
Unsolder the flyback. circuit
H Output / V Output ♦ Adjust HV RV8002 for 31.5kV.
Adj HV shutdown RV8001 (coarse) and
RV8003 (fine) according to safety related
adj in the service manual.
A Standby Power Supply Dead set (check ♦ Transplant memory IC707 containing
Remove 4 screws from the rear panel and Degaussing circuit front panel master system and user data.
fold it down. switch).
Secondary Power Supply ♦ Enter the service mode and verify the TV
Pry the locks from connectors CN3202/3 (9V, 5V, 3.3V) ID (group #19), then perform touch up
while wiggling the B board away form the A geometry adjustments to CXA2150D-1
H & V Oscillators/Jungle
board. data (group #4-1)*.
Both Tuners
Remove 6 screws securing the A board.
Main uCom IC701
Lift the right side of the A board out.
Audio processing
OSD (Menu)

U Rear panel input connectors Loss of video / audio None

Remove 4 screws from the rear panel and 1-6 inputs. Tuner is
fold it down. unaffected.
Pry the locks from its connector and wiggle it

viii
 ix

B Video processing and audio Loss of video, Y or C. Transplant memory IC3089 containing Twin
Remove 4 screws from the rear panel and switching. Loss of sync to main picture parameters.
fold it down. Closed caption/V Chip or sub pix.
Pry the locks from connectors CN3202/3 DRC for line doubling
while wiggling the B board away form the A MID for twin pictures
board.

C RGB CRT signal amplifiers Dark screen (adjust Adj Screen control according to the service
Wiggle the C board off the CRT neck. G2 first) manual: Reduce vertical size to see IK line at
Stby light blinks 5 the top. Blank pix in the service mode by
Unsolder the CRT socket and install on the changing CXA2150P-2/ALBLK data from 0 to
new board. times & repeats.
1. Adjust screen control so the IK line is just
invisible in a dark room.
W Velocity Modulation circuit White outline along
to improve detail object. W board
Remove the C board. clamp
Mark the pix tube neck to reinstall the new W Top/bottom Pincushion &
board assembly. corner focus coils
Loosen the clamp and remove the assembly. Pix
G1
tube

* Refer to the service manual s section 5 for the list of adjustments.

HA/HB boards - Front panel remote & buttons

Dynamic
Convergence Secondary Primary
Power Supply Power Supply

S Bd
(audio)
HV Regulator
Horizontal
Deflection B board
(video)
FBT
Stby
Vertical Circuit
 Front of TV Pry out

CN3202

HA board HB board

D Board A Board

CN3203
Pry out
B board

BC board BC
board

U board
U board

x
 xi

S CONFIDENTIAL
Sony Service Company
National Technical Services Service Bulletin csv-1
A Division of Sony Electronics Inc.
Park Ridge, New Jersey 07656 TV Products
Model: KV-32XBR400, KV-36XBR400
No. 492

Date: July 27, 2000

Subject: Service Manual Correction: Safety Related
Adjustments

Symptom:
(****) There is an error on page 23 of the preliminary service manual in the HV
Service Flowchart.

Solution: Change the incorrect text as follows:

Incorrect:
"Confirm +B, Vd, and check hold-down on D-board with black video with the
following steps:
1. Confirm +B across C6544 to make sure it is 135.3 – 1 Vdc.
2. Confirm Vd at pin 2 CN6506 or at TP-Vd for 4.9 V < Vd < 5.1 Vdc.
3. Apply 5.5 + 0.5 VDC at pin 2 of CN6544, then confirm set holds down."

Correct:
"Confirm +B, Vd, and check hold-down on D-board with black video with the
following steps:
1. Confirm +B across C6544 to make sure it is 135.3 – 1 Vdc.
2. Confirm Vd at pin 2 CN5506 or at TP-Vd for 4.30 V = Vd = 4.65 V.
3. Apply 5.5 + 0.3 VDC at pin 2 of CN5506, then confirm set holds down."
 S and i.LINK are trademarks of Sony Electronics
Dolby Digital is a trademark of Dolby
Fire Wire is a trademark of Apple Computer Inc.
TiVo is a registered trademark of TiVo Inc.

S
SEL Service Company
A Division of Sony Electronics Inc.
1 Sony Drive
Park Ridge, New Jersey 07656

DTV021000 Printed in U.S.A.