--Programa para el bit del Segundo y el minuto menos significativo

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library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity segmenos is port(
clk,reset: in std_logic;
disp: inout std_logic_vector (7 downto 0));
end segmenos;
architecture funsegmenos of segmenos is
begin
process(clk,reset)
begin
if(reset='1') then
disp<="01111110"; --display a cero
elsif(clk'event and clk='1')then
if(disp="01110011")then --cambio de nueve a cero, y acarreo sig contador
disp<="11111110";
elsif(disp="11111110" or disp="01111110")then --cambio de cero a uno
disp<="00110000";
elsif(disp="00110000")then --cambio de uno a dos
disp<="01101101";
elsif(disp="01101101")then --cambio de dos a tres
disp<="01111001";
elsif(disp="01111001")then --cambio de tres a cuatro
disp<="00110011";
elsif(disp="00110011")then --cambio de cuatro a cinco
disp<="01011011";
elsif(disp="01011011")then --cambio de cinco a seis
disp<="01011111";
elsif(disp="01011111")then --cambio de seis a siete
disp<="01110000";
elsif(disp="01110000")then --cambio de siete a ocho
disp<="01111111";
elsif(disp="01111111")then --cambio de ocho a nueve
disp<="01110011";
end if;
end if;
end process;
end funsegmenos;
--Programa para el bit del Segundo y el minuto más significativo
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library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity segmas is port(
clk,reset: in std_logic;
disp: inout std_logic_vector (7 downto 0));
end segmas;
architecture funsegmas of segmas is
begin
process(clk,reset)
begin
if(reset='1') then
disp<="01111110";
elsif(clk'event and clk='1')then
if(disp="01011011")then
disp<="11111110";
elsif(disp="11111110" or disp="01111110")then
disp<="00110000";
elsif(disp="00110000")then
disp<="01101101";
elsif(disp="01101101")then
disp<="01111001";
elsif(disp="01111001")then
disp<="00110011";
elsif(disp="00110011")then
disp<="01011011";
end if;
end if;
end process;
end funsegmas;

--Programa para bit menos significativo de las horas

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library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity horamenos is port(
clk,reset: in std_logic;
aux: out std_logic;
disp: inout std_logic_vector (7 downto 0));
end horamenos;
architecture funhoramenos of horamenos is
begin
process(clk,reset)
begin
if(reset='1') then
disp<="01111110";
aux<='0';
elsif(clk'event and clk='1')then
if(disp="01110011")then
disp<="11111110";
aux<='1';
elsif(disp="11111110" or disp="01111110")then
disp<="00110000";
elsif(disp="00110000")then
disp<="01101101";
elsif(disp="01101101")then
disp<="01111001";
elsif(disp="01111001")then
if(aux='0')then
disp<="00110011";
else
disp<="11111110";
aux<='0';
end if;
elsif(disp="00110011")then
disp<="01011011";
elsif(disp="01011011")then
disp<="01011111";
elsif(disp="01011111")then
disp<="01110000";
elsif(disp="01110000")then
disp<="01111111";
elsif(disp="01111111")then
disp<="01110011";
end if;
end if;
end process;
end funhoramenos;

--Programa para bit más significativo de las horas

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----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity horamas is port(
clk,reset: in std_logic;
disp: inout std_logic_vector (6 downto 0));
end horamas;
architecture funhoramas of horamas is
begin
process(clk,reset)
begin
if(reset='1') then
disp<="1111110";
elsif(clk'event and clk='1')then
if(disp="1101101")then
disp<="1111110";
elsif(disp="1111110")then
disp<="0110000";
elsif(disp="00110000")then
disp<="1101101";
end if;
end if;
end process;
end funhoramas;