Problem 4 A sequential circuit has one input, Xone ontpt,Z, and two flip-ops, QL and 2. timing Singaa fr the ious sown below (assuing zero delays in the Mipops and the gates) Dos this cite use positive or nepative-edie triggered ip-tops? Isthie« Moore cr Meals crit? (Consist he next state tble and sho the tan i digram for this iret 2p) ‘This cseut uses negative edge-uigared flip-flops (since FF states change oa the negative edge) Gt) ‘This «Mealy sequential system (since the output Z depends on input 39, asp) ‘The next state snd oxpt Table ca be derive from stat rausitions a the negative ede of every lock pls Ther are total ofS clock Hines (shown above) proving ino forall posible state tations, fortwo sate vaniabls and one input CX) For example, onthe fist clock pulse (shown in the timing agra For present state Q1Q2-00 and input X=O the ouput Z=1 aud the wext state is Q1-Q2+= 01 Present |__Nest state 1 or lor ort or o ofo 1f1 oft o o 1fo oft tfo 4 roof1 1fo oft o rift ofo tfo 4