Roll No. ...... Total No. of Questions : 09) [Total No. of Pages : 02 B.Tech. (Sem. - 3) COMPUTER ARCHITECTURE ~ SUBJECT CODE: CS - 201 Paper ID : [A0451} {Note : Pleise fil subject code and paper ID on OMR] “ Time : 03 Hours Maximum Marks : 60 Instruction to Candidates: 1) Section - A is Compulsory. 2) Attempt any Four questions from Section - B. 3) Attempt any Two questions from Section - C. Section - A “ 7 yi a) What is the puesto gira b) What is program interrupt? (10 x 2 = 20) ction pipelining? Q1) c) An eight way set-associative cache consists of a total of 256 blocks. The main memory, contains 8192 blocks, each consisting of 128 words. G) How many bits are there in the main memory address? (ii) How many bits are there in the TAG, SET and WORD fields? d) What is the use of Condition Code register? ©) What is parallel computers? f) Give the features of a ROM cell. g) What is DMA? What is its role? h) What is SIMD? i) What are the principles of computer design? j) What is serial interface and parallel interface? R-716 F P.T.O.2) 3) 24) 95) 26) a7) 28) an Section - B (4x5=20) Explain in detail the principle of carry-look-ahead adder. Show how 16- bit CLAs can be constructed from 4-bit address. Explain the working of floating point adder/subtractor. Discuss the various mapping schemes used in cache design. Compare the schemes in terms of cost and performance. What is the architectural distinction between RISC and CISC processors? Explain Microprogrammed Control Unit. What are the advantages and disadvantages of it? Section - C , t o. Explain the foli o any > f- (a) Pipelining in CPU design $uy E ine. (b) Distributed computers. (c) Hardwired vs Microcoded control. (2x 10 = 20) (a) Define the following with the appropriate formulae : (i) Clock sate and CPI (i) MIPS rate (ii), Throughput rate (b) What is memory interleaving? How is it different from cache memory? Discuss interaction with operating system-serial/parallel interfaces taking 8251/8255 as examples. ooo R-716 a