UNIVERSITY EXAM QUESTION PAPERS B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2009.

Fourth Semester Computer Science and Engineering CS 1251 - COMPUTER ARCHITECTURE (Common to Information Technology) (Common-to B.E. (Part-Time) - Third Semester- Computer Science and Engineering - Regulation 2005) (Regulation 2004) Time: Three hours Answer ALL questions. PART A - (10 x 2 = 20 marks) 1. What is a system bus? 2. What are the types of memory? 3. Convert the following binary number to decimal number. (a) 1101012 (b) 1111002 4. What is the purpose of stack? 5. Define pipelining. 6. How are the signed binary numbers represented? 7. Draw the half adder circuit. 8. What is a virtual memory? 9. What are the types of interrupts? 10. Mention the advantage of USB bus. PARTB - (5 x 16=80 marks) 11. (a) Explain the steps involved in the DMA operation. Or (b) Describe the various mechanisms for accessing I/O devices. Maximum: 100 marks

E.COMPUTER ARCHITECTURE' (Common to Information Technology) (Common to B. 8. Or (b) Explain briefly the various types of addressing modes with example. 10.(10 x 2= 20 marks) 1.Third Semester . 2. 6. 5. 15.12. 14. 13. Using 2's complement method perform (10102-11112) 4. Fourth Semester (Regulation 2004) Computer Science and Engineering CS 1251. 7. Explain structural hazard. Maximum: 100 marks . Or (b) Explain the restoring and non-restoring division algorithm.Tech. B.Regulation 2005) Time: Three hours Answer ALL questions. Differentiate DRAM and SDRAM. (a) Design the full adder circuit and explain how it is used in the multiplications two signed number. Draw block diagram of a basic processor.E. (Part-Time) . Differentiate direct and indirect addressing mode. 9. 3. Explain handshaking with respect to data transfer. (a) Describe the functional units of the computer system. Or (b) Write a short note on secondary storage devices in computer system. List the conditions to overcome data hazard./B. Or (b) Describe the multiple bus organization and compare it with single bus organization. Design al MB x 32 bit memory using 256 kB x 8bit static cell. NOVEMBER/DECEMBER2008. (a) Explain the various pipelining hazards and their remedies in the processor. (a) Explain the various cache replacement policies in the cache memory. Write rule for addition in floating point operation. PART A . DEGREE EXAMINATION.

(16) Or b) i) Explain the ripple carry multiplier with (m3m2m1m0)(q3q2q1q0) Inputs. (Part-Time) . (16) Or (b) (i) Explain how the instruction A =B . draw block diagram and explain the operation.Third Semester . (16) B. (a) Explain the operation of hard wired control unit. DEGREE EXAMINATION.(16) 15.E.PART B. (6) ii) Discuss in detail about hazards due to unconditional branching (10) 14 a) Explain about direct mapping and set associative mapping in Cache memory. Fourth Semester (Regulation 2004) Computer Science and Engineering CS 1251 .COMPUTER ARCHITECTURE' (Common to Information Technology) (Common to B.(16) Or b) Explain about virtual memory and its management.Regulation 2005) Time: Three hours Maximum: 100 marks . (a) Demonstrate the division of 11002 bylOl2 using restoring method.C gets executed in a system in detail.Tech. APRIL/MAY 2008. (8) 12. (8) ii) Multiply (-12) and (13) using booths algorithm.(5 x 16 =80 marks) 11. (16) Or b) i) Explain how gating is achieved in registers. (a) i) Explain in detail about direct memory access methods (DMA) (10) (ii) Explain about vectored interrupt with daisy chain arrangement. (a) Write the basic performance equation and using this equation explain how the performance of a system can be improved. (6) Or (b) Write short notes on: (i) Interface circuits (ii) SCSI (iii) Polling (iv) Addressing of I/O devices. (8) 13.E. (8) (ii) Explain briefly stacks and queues./B.

9. (a) (i) With a neat diagram explain Von-Neumarm computer architecture (12) (ii) What are the major instruction design issues?(4) Or (b) (i) Explain various instruction formats in detail.(10) (ii) What is a stack and what are the operations on stack? Give any three applications of stack. What is the difference between hardwired control and micro programmed control? 7. (8) Or (b) (i) Design an array multiplier that multiplies two 4-bit numbers and explain its operation.(16) 14.(6) (ii) Explain various mechanisms of mapping main memory address into cache memory addresses. (a) (i) Design a 4-bit binary adder/subtractor and explain its function(8) (ii) Give the algorithm for multiplication of signed 2's complement numbers and illustrate with an example. Perform 1010100 . PART A . 8. What is pipelining and what are the advantages of pipelining? 6. (a) (i) Describe the functional characteristics that are common to the devices used to build main and secondary computer memories. Define underflow and overflow. Why is the data bus in most microprocessors bidirectional while the address bus is unidirectional? 3. What factors influences the bus design decisions? 10. What is priority interrupt? PART B.(10 x 2= 20 marks) 1. (8) (ii) Write the algorithm for division of floating point numbers and illustrate with an example. (8) 13. List the differences between static RAM and dynamic RAM.(5 x 16 =80 marks) 11. (10) (ii) With a suitable diagram describe the sequence of micro operations involved in fetching and executing a typical instruction. (6) Or (b) What is data hazard? Explain the methods for dealing with the data hazards. Define the terms: spatial locality and temporal locality. 5.Answer ALL questions. (6) 12.1000100 using 1's and 2's complement. 4. (a) (i) What is branch hazard? Describe the methods for dec1hng with the branch hazards. (10) Or . What are tri-state gate? 2.

/B. (ii) Discuss the operations of a bus. What is meant by a multiple bus? Where it is organised? 6. (10) (ii) Describe the working principle of a typical magnetic disk. DEGREE EXAMINATION. What is a superscalar operation? 8. NOVEMBER/DECEMBER 2008. (Part-Time) Fifth Semester Regulation 2005) Time: Three hours Answer ALL questions PART A . When addressing mode will be viewed critically? 3. What is a signed number? Where it is used? 5.(5 x 16 = 80 marks) 11. What is an non-maskable interrupt? What is the action performed on receipt of a NMI? 10. (a) (i) What are the softwares used in a computer to operate all the functional units? Discuss briefly on the bus structures.E. Sixth Semester (Regulation 2004) Electronics and Communication Engineering CS 1251. (8) (ii) Briefly compare the characteristics of SCSI with PCI (8) B. (6+6+4) Or Maximum: 100 marks . (16) Or b) i) Describe the working principles of USB. a) Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer between memory and peripherals. Narne the functional units of a computer and how they are interrelated.COMPUTER ARCHITECTURE (Common to B. What is the principle of semiconductor memory? 9.(10 x 2 = 20 marks) 1. 2.(b) (i) Explain how the virtual address is converted into real address in a paged virtual memory system. 7.E. (iii) Calculate the number of memory addresses for a 4 MB memory with a 16 bit word. How do you ascertain an adder as "fast"? 4. (6) 15. Define data hazards. What are the advantages of USB interface? PART B .Tech.

Discuss the influence of various pipelining hazards on instruction set. MAY/JUNE 2007. (a) What is hardwired control? Explain micro-programmed control and compare it with hardwired control. (a) Explain an algorithm to multiply two positive numbers.Regulation 2005) Time: Three hours Answer ALL questions. What is the need for different memory management schemes? (16) 15 a) Describe DMA and its implementation. ROM and cache memories. (16) 13. size and cost. The computer has an instruction format with four fields: an operation code field. (16) Or b) Write short notes on (i) Interrupts (ii) Standard I/O interfaces. State the advantages of DMA over the other modes of I/O transfer. a register address field to specify one of 60 processor registers. The memory unit of a computer. Also discuss the realization of a multiplier to implement the same. and a memory address. PART A.(10 x 2 = 20 marks) 1. Compare them based on their speed. (Part-Time) Fifth Semester .(b) Describe instructions of a computer and how they are sequenced.E. Maximum: 100 marks .memory? Explain the various memory management schemes. (16) 14. (a) Describe the working principle of RAM. DEGREE EXAMINATION. Specify the instruction format and the number of bits in each field if the instruction is in one memory word. Sixth Semester (Regulation 2004) Electronics and Communication Engineering CS 1251 . has 256 K words of 32 bits each.COMPUTER ARCHITECTURE (Common to B.(16) Or (b) How different arithmetic and logic functions are realized and integrated in an ALU? Explain. (16) Or (b) What is virtual .Tech. What is meant by the stored program concept? Discuss. Which is preferred under what circumstances? (16) Or (b) Explain the concept of Pipelining. 2. a mode field to specify one of seven addressing modes. (16) B./B.E. How is memory organization related to this? (6 + 6+4) 12.

How does the processor handle an interrupt request? PART B . (a) Give the organization of a typical hard wired control unit and explain the functions performed by the various blocks. What are the functions of a typical I/O interface? 10. Multiply the following pair of signed 2's complement numbers using bit-pair recoded multiplier Multiplicand 110011 and Multiplier = 101100. Discuss the principle of operation of a micro programmed control unit? 6. (8) (ii) A computer system has a main memory consisting of 16 M words. What is a ripple carry adder? 5. (8) Or (b). 7. SET and WORD fields of the main memory address format. What is the ideal speedup expected in a pipelined architecture with 'n' stages? Justify your answer. (8) ii) Discuss the various issues to be considered while designing the ISA of a processor. Simulate the same for 23/5. (8) (ii) Simulate the addition and subtraction operations (A + (OR) . Discuss the data flow for a sample instruction. Give appropriate comments. (8) 12 a i) Discuss the principle of operation of carry-look ahead adders. . (8) 13. Define Average Memory. 4. (8) Or (b) (i) Discuss the concept of bit pair recoding.3. What are the remedies commonly adopted to overcome/minimize these hazards? (16) 14 a) i) Discuss the various mapping techniques used in cache memories. (8) (ii) Write an assembly language program using the assembly language you are familiar with to add a sequence of n numbers.  Calculate the number of bits in each of the TAG. (16) Or b) Discuss the various hazards that might arise in a pipeline.(i) What is a stack? State some uses of the same. with 4 blocks per set and 128 words per block. Show how a stack can be implemented using auto increment and auto decrement addressing modes. 8. It also has a 32K-word cache organized in the block-set-associative manner. How do you construct a 8 M x 32 memory using 512 K x 8 memory chips? 9.0 10001 011011 B =1 01111101010 with a five-bit signed excess-15 exponent and a six-bit normalized fractional mantissa.B) on the operands: A =.(5 x 16 =80 marks) 11 a i) What are the various types of Instruction Set Architectures possible? Discuss. Discuss the principle behind the Booth's multiplier. (8) (ii) Discuss the non-restoring division algorithm.Access Time for a computer system with two levels of caches.

Write the sequence of control steps required for three bus structure for the following instruction: Add R4. 8. Answer ALL questions. Maximum: 100 marks . Give the features of a ROM cell. R5. How will the main memory address look like for a fully associative mapped cache? (8) Or (b) (i) Explain the concept of virtual memory with anyone virtual memory management technique.(10 x 2 = 20 marks) 1.(8) (ii) Discuss the operation of any two input devices.600. Registers R1 and R2 of a computer contain the decimal values 1200 and 4. What is the effective address of the memory operand In each of the following instructions? (a) Load 20(R1). Define Locality of Reference. (a) Explain the functions to be performed by a typical I/O interface with a typical input or output interface. Sixth Semester (Regulation 2004) Electronics and Communication Engineering CS 1251 . 5. (8) B. What do you mean by End-around carry correction? 4. R5. 7. R5 (b) Add-(R2). (16) Or (b) (i) Discuss the DMA driven data transfer technique. (8) (ii) Give the basic cell of an associative memory and· explain its operation. What is the difference between a Subroutine and an Interrupt – service routine? 10. (8) I5.E. DEGREE EXAMINATION. Why is the Wait-for-Memory-Function-Completed step needed when reading from or writing to the main memory? 6. 9. What is the use of Condition Code register? 3. APRIL/MAY 2008. R6.COMPUTER ARCHITECTURE (Common to B. PART A. Show how associative memories can be constructed using this basic cell. (Part-Time) Fifth Semester Regulation 2005) Time: Three hours. Discuss the role of Booth algorithm in the design of Fast Multipliers.E/B. 2. Define Bus Arbitration.Tech.

Depict clearly how it controls data transfer during an input operation. Maximum: 100 marks . What is mean by straight -line sequencing? 3. (16) Or (b) Explain Handshake protocol. Explain the use of TLB. Explain in detail with a neat diagram. (16) 15.Tech. (a) Define Cache Mapping Functions. (16) 12./B.(10 x 2 = 20 marks) 1. (Part-Time) Fifth Semester Regulation 2005) Time: Three hours Answer ALL questions. 2. Sixth" Semester (Regulation 2004) Electronics and Communication Engineering CS 1251 . Explain the methods. DEGREE EXAMINATION. What are the advantages and disadvantages of it? (16) 14. a) Illustrate Booth Algorithm with an example.E.E.PART B . (16) Or (b) How does a virtual address gets translated into a physical address. (16) Or b) Design a 4-bit Carry-Look ahead Adder. Draw the structure of alternative two . (16) Or (b) Explain Microprogrammed Control Unit. (a) Explain the use of DMA Controllers in a computer system with a neat diagram. PART A . Draw the structure of 4-bit MSI ALU circuit block. (16) B.COMPUTER ARCHITECTURE (Common to B.(5 x 16 = 80 marks) 11. (a) Explain in detail the different Instruction types and Instruction Sequencing. NOVEMBER/DECEMBER 2007.(16) Or b) Explain the different types of Addressing modes with suitable examples.bus structure. respectively. (16) 13 a) Write a Microroutine for the instruction Add (Rsrc) + Rdst where the source and destination operands are specified in indexed and register addressing modes.

point numbers are represented and used in digital arithmetic operations. 8. What are the necessary operations needed to start an I/O operation using DMA. (a) Explain in detail about interrupt handling. 10. Write the two advantages of MOS devices. (16) Or b) Describe in detail about the memory mapping between virtua1 and main memory with an example. (a) Explain in detail about instruction execution characteristics. (16) Or b) With a block diagram. 5. (16) . Define IEEE floating point Single and Double precision standard. (16) 14 a) Give the structure of semiconductor RAM memories. 6. Explain in detail about logic design for fast address. (a) With a neat sketch. Explain the Read and Write operations in detail. (16) 12. Explain in detail about micro programmed control and explain its operations. (16) 13. 9.(5 x 16 =80 marks) 11. (16) Or (b) Describe how the floating . Draw the structure of two stage instruction pipe line. Give an example. What are the limitations on super scalar device? 7. Draw the connection between main memory and CPU. What are the three types of channels are usually found in large computers? PART B . (a) Explain in detail about functional unit and Bus structures of computer (16) Or (b) Describe various addressing modes with suitable examples. (16) Or (b) Explain in details about standard I/O interfaces.4. (16) 15.

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