Check_library

Information: List of cells missing in logic library (LIBCHK-210)

Cell name Cell type Physical library
GDCAP4_NL Core tcbn65lp_c060217
GDCAP_NL Core tcbn65lp_c060217
GDCAP10_NL Core tcbn65lp_c060217
GDCAP2_NL Core tcbn65lp_c060217
GDCAP3_NL Core tcbn65lp_c060217
GDCAP_NLHVT Core tcbn65lphvt_c060217
GDCAP10_NLHVT Core tcbn65lphvt_c060217
GDCAP2_NLHVT Core tcbn65lphvt_c060217
GDCAP3_NLHVT Core tcbn65lphvt_c060217
GDCAP4_NLHVT Core tcbn65lphvt_c060217

Check_tlu_plus_files

The design passed all sanity checks.

Report_timing_requirements
________________________________________________________________________
Description Setup Hold
TIMING EXCEPTION FALSE FALSE
-from rst_chip
TIMING EXCEPTION FALSE FALSE
-from ckyidb\
-to ck_fir
TIMING EXCEPTION FALSE FALSE
-from tap_en\
-to ck_fir
TIMING EXCEPTION FALSE FALSE
-from ckyidb\
-to ck_fir_e
TIMING EXCEPTION FALSE FALSE
-from tap_en\
-to ck_fir_e
TIMING EXCEPTION FALSE FALSE
-from ckyidb\
-to ck_br_e
TIMING EXCEPTION FALSE FALSE
-from ckyidb\
-to ck_br
TIMING EXCEPTION FALSE FALSE
-from tap_en\
-to ck_br
TIMING EXCEPTION FALSE FALSE
 -from ckyidb\
-to ck_st
TIMING EXCEPTION FALSE FALSE
-from tap_en\
-to ck_st

Report_disable_timing

There are no disabled timing arcs in the design.

Report_case_analysis

No constant value pins/ports.

Report_clock

Attributes:
d - dont_touch_network
f - fix_hold
p - propagated_clock
G - generated_clock
g - lib_generated_clock

Clock Period Waveform Attrs Sources

ck_br 2.98 {0 1.49} {ck_br}
ck_br_e 2.98 {0 1.49} {ck_br_e}
ck_fir 2.98 {0 1.49} {ck_fir}
ck_fir_e 2.98 {0 1.49} {ck_fir_e}
ck_st 2.98 {0 1.49} {ck_st}
ckyidb 2.98 {0 1.49} {ckyidb}
tap_en 2.98 {0 1.49} {tap_en}

report_clock –skew

Rise Fall Min Rise Min fall Uncertainty

Object Delay Delay Delay Delay Plus Minus
ckyidb 0.34 0.34 0.34 0.34 0.15 0.15
ck_fir 0.49 0.49 0.49 0.49 0.15 0.15
tap_en 0.40 0.40 0.40 0.40 0.15 0.15
ck_fir_e 0.13 0.13 0.13 0.13 0.15 0.15
ck_br_e 0.69 0.69 0.69 0.69 0.15 0.15
ck_br 0.75 0.75 0.75 0.75 0.15 0.15
ck_st 1.01 1.01 1.01 1.01 0.15 0.15
report_clock –groups

There are no mutually exclusive or asynchronous clock groups.

Report_timing (in zero-interconnect delay mode)

All path groups have slightly positive slack.

Report_ideal_network

No ideal networks present in the design.

Report_fp_placement_strategy

All are default settings.