Professional Documents
Culture Documents
August 1999
1
c
2000 by Mohammad Sharawi and Husam Abu-Ajwah All rights Reserved.
No part of this report is to be copied, reproduced, or distributed in anyway, without
written consent of the Author.
Contact: msharawi@go.com.jo or husamsamir@hotmail.com
1
1 Introduction 5
2 Background 7
2.1 FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 PSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 QPSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Circuit Design 18
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Universal Clock and Word Generator . . . . . . . . . . . . . . . . 18
3.2.1 The Universal Clock . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 The Word Generator . . . . . . . . . . . . . . . . . . . . . 18
3.3 FSK System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1 FSK Transmitter . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2 FSK Receiver . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 The PSK Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.1 The PSK Transmitter . . . . . . . . . . . . . . . . . . . . 24
3.4.2 The PSK Receiver . . . . . . . . . . . . . . . . . . . . . . 25
3.4.3 Balanced Modulator (MC1496 IC) . . . . . . . . . . . . . 30
3.5 The QPSK System . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.1 The Phase Shifter . . . . . . . . . . . . . . . . . . . . . . 34
3.5.2 The Demultiplexer and Multiplexer circuits . . . . . . . . 34
3.5.3 The QPSK Transmitter . . . . . . . . . . . . . . . . . . 37
3.5.4 The QPSK Receiver . . . . . . . . . . . . . . . . . . . . 38
3.5.5 PCB Design and Final Circuit Schematic . . . . . . . . . 40
4 Results 46
2
List of Figures
3
LIST OF FIGURES 4
Introduction
T hrough ages, man always tried to find a way for long distance commu-
nication. Man used pigeons, and men riding horses to deliver mail. These two
methods were inefficient; the first was limited to certain directions that the pi-
geons were trained to go to, and the latter took longer time for further distances.
These methods were used till the 19th century, when Alexander Graham Bell
succeeded in performing the first wired telephone call (transmitting and electri-
cal signal) in 1875. This invention revolutionized world communication.
Right after World War II, the idea of having Global Wireless informa-
tion transmission arose. The developed countries started their rally of launching
satellites to ease global communications, by covering larger areas that receive
satellite transmission. Also the Digital Modulation technology started to de-
velop.
5
CHAPTER 1. INTRODUCTION 6
There are several factors that influence the choice of a digital mod-
ulation scheme. The desired scheme is the one that provides lowest bit error
rates, performs well in multipath and fading conditions, occupies a minimum
bandwidth, and is coast effective. In reality there are trade-offs when selecting
a digital modulation scheme depending on the application. The two measures
that determine the performance of the modulation scheme are Power efficiency
and Bandwidth efficiency. Power efficiency describes the ability of a modula-
tion technique to preserve the fidelity of the digital massage at low power levels.
The power efficiency ηP is often expressed as the ratio of the signal energy per
Eb
bit to noise power spectral density N 0
required at the receiver input to have a
certain probability of error (say 107 ) [Rap96].
Background
7
CHAPTER 2. BACKGROUND 8
BT = 2(∆f + R) (2.5)
Eb
were N 0
is the signal energy per to noise power spectral density.
An M-ary FSK signal consist of a set of Orthogonal3 set of M-frequency shifted
signals. When these signals are detected coherently, the adjacent signals need
1
to be separated by a frequency of 2T so as to maintain orthogonality. Hence we
can define the bandwidth of an M-FSK by:
M
B= (2.7)
2T
For M-ary signals, the symbol duration is given by:
T = Tb log2 M (2.8)
R∞ 2
2 Erfc is the complementary error function, were erfc(u) = √2 e(−z) dz. Usually we
π u
use tables to find its value. [Hay94]
3 Two
RT
signals s1 , s2 are orthogonal if: s1 ∗ s2 = 0. [Skl88]
0
CHAPTER 2. BACKGROUND 9
M 2 4 8 16 32 64
ηB bits/Hz 1 1 0.75 0.5 0.3125 0.1875
Eb
N0 for a BER of (10−6 ) 13.5 10.8 9.3 8.2 7.5 6.9
Table 2.1: The bandwidth efficiency and the power efficiency of the M-levels
FSK.
The tables tell us that the Bandwidth efficiency decreases with the increase in
the number of levels.
A typical coherent FSK demodulator is shown in Fig.(2.3). Here the input FSK
signal is applied to two multipliers, one has the frequency of a the transmitted
one, the other has the frequency of a zero. These frequencies should be as the
ones used in the modulator circuit. The multiplier is followed by an integrator,
then the output is summed, and applied to the decision device to determine if
a zero or a one has been transmitted.
In our design we built a non-coherent FSK system. We used a PLL to lock
on the incoming frequency, and from the phase detector’s output we took our
final output. This gave us a digital stream as the one being transmitted by the
VCO, but this output needed some filtration to get a clear digital output. The
block diagram in Fig.(2.4)demonstrates the way we built the FSK system.
CHAPTER 2. BACKGROUND 10
Eb
Here the N 0
is double the one in its FSK counterpart, which means that we
Eb
have to double the N 0
for the FSK signal in order to have the same average error
rate as the BPSK one. This is obvious when looking at the signal constellation
of the BPSK and the BFSK. The distance between the two binary points in
the FSK constellation is almost half the distance in the BPSK constellation,
which means that the probability of false decision in the FSK is double its PSK
Eb
counterpart. That’s why we need to double the N 0
for the FSK to compensate
for and have the same average error probability of its PSK counterpart.
BPSK is considered bandwidth efficient and its bandwidth efficiency in-
creases with the increase of the number of bits per symbol, this will affect
its power efficiency. This is best illustrated in Table(2.1) [Rap96]. The channel
bandwidth required to pass M-ary PSK signals is given by:
2
B= (2.14)
T
Where T is the symbol duration, which is related to bit duration by Eq.(2.8).
Also using Rb = T1b , Eq.(2.14) becomes:
2Rb
B= (2.15)
log2 M
Equivalently we can use Eq.(1.1) to obtain the PSK bandwidth efficiency for-
mula:
log2 M
ηB = (2.16)
2
M 2 4 8 16 32 64
ηB bits/Hz 0.5 1 1.5 2 2.5 3
Eb
N0 for a BER of (10−6 ) 10.5 10.5 14 18.5 23.4 28.5
Table 2.2: The bandwidth efficiency and the power efficiency of the M-levels for
PSK Modulation.
Comparing this table with Table(2.1), we notice that the BPSK is more
bandwidth efficient than its FSK counterpart, but there is a trade off in its
Power efficiency.
CHAPTER 2. BACKGROUND 13
As for the Demodulation process, For coherent detection, the basic demod-
ulation scheme is shown in Fig.(2.7):
Here we have the incoming signal multiplied with a synchronized oscillator
that has the same frequency of the modulation frequency. These two are multi-
plied together, and the output is applied to a LPF (Low Pass Filter) to remove
noise and to perform integration on the incoming signal. The decision device
follows giving the Binary output.
In our design, we followed this basic modulator demodulator concept. The
circuit design is shown in the coming chapter.
The signal Constellation of this equation is shown in fig (2.8a). Another way
of having a QPSK modulation is by using the phase shifts π4 , 3π 5π 7π
4 , 4 , 4 . This
method yields the signal constellation as the shown in Fig.(2.8b). Also a table
that shows the signal space characterization of the QPSK signaling is shown in
Table (2.3).
As for the QPSK modulator (transmitter), the basic block diagram of such
a system is shown in Fig.(2.10):
In Fig.(2.10), the QPSK modulator consists of two streams of PSK mod-
ulators, one is fed with the Odd data sequence, and the other with the even
CHAPTER 2. BACKGROUND 14
Figure 2.9: QPSK signal constellation with its decision regions. [Hay94]
CHAPTER 2. BACKGROUND 15
sequence. Also one stream is modulated with a cos wave and the other with a
sine wave to have a π2 phase difference.
As for the bandwidth and power efficiency measures, please refer to Table(2.2).
The bandwidth efficiency of QPSK is twice that of PSK since we are transmit-
ting two bits per signal. The Average probability of bit error of the QPSK
signaling is: [Hay94] r !
1 Eb
Pe = erf c (2.18)
2 N0
Surprisingly, the average probability of bit error of the QPSK is the same
as that of the PSK in AWGN channel4 , while as much data can be sent in the
same bandwidth. Thus compared to PSK, QPSK provides twice the spectral
efficiency with exactly the same energy efficiency.
4 Refer to Communication Systems by Haykin for proof of P of both the PSK, and QPSK.
e
[Hay94]
CHAPTER 2. BACKGROUND 16
Circuit Design
3.1 Introduction
Our project is composed of five major circuits which are : FSK ,PSK ,Q-PSK
modulators/demodulators, the Clock, and the Word generator. All mentioned
circuits were simulated by the Electronic Work Bench (EWB) simulation soft-
ware. This chapter will illustrate each circuit with further information needed
to show how these circuits were designed and why. Also we needed additional
circuits such as, Attenuators, Filters, Comparators, Amplifiers, Phase shifter,
Summer, Multiplexer and Demultiplexer were designed according to the appli-
cation requirements.
The last part of this chapter shows the whole schematic of this project that
helps the student to find the places of the components for designed circuits in this
chapter(every component is labeled so anyone can trace the circuit easily).Also
the PCB design is shown in this part of the chapter. Limitations, requirements
and educational purposes of this design will be discussed to justify the reason
for PCB board to appear the way it is.
18
CHAPTER 3. CIRCUIT DESIGN 19
able to construct this logic circuit in order to have a controllable 8-bits repetitive
stream of data (by 8-dip switches),with a controllable data rate obtained by
changing the clocks feeding the two ICs.
These clocks are 8 KHz for the FSK system, 64 KHz for the PSK system and
128 KHz for the Q-PSK system. As we said the input to the register that can
be controlled in our module is by the dip switches, here the stream is 11011010
set in parallel by our dip switches and the same stream was obtained at the
output but in a serial form, with a data rate specified according to the clock of
the system we are operating as shown in Fig.(3.3)
to obtain the desired free running frequency must be designed according to the
following relationship and the former variables (input level and the DC offset)
which are: +
V − V5
fo = 2.4 (3.2)
RCV +
Our Free running frequency is = 1.024 MHz, V + is our supply which is =
12 V dc, V5 is 34 Vcc which is almost = 9 V dc, but it turned out that this
formula does not apply for specific ranges such as the case here, so this formula
must be verified. The values of R & C can be calculated and by assuming the
value of C = 50 pF, R was found to be = 11.72KΩ which is wrong because
when implemented results obtained were not accurate. By methodical tests and
measurements, a resistor of 3.3KΩ(R16 ) in series with a pot of 1KΩ(P ot1 ) were
put instead as shown in the Fig.(3.6). This leads us to verify this equation
according to the frequency we are working at as in formula 3.2b:
+
V −V5
fo = 0.82 (3.3)
RCV +
Note: The output of this IC which is an FSK output was DC blocked in
our design by a small capacitor of 0.1µF (C2 ) as shown in the schematic for the
transmitter and the receiver together fig (3.9). As mentioned before the output
of this IC is an FSK output as shown in Fig.(3.7).
We can notice from the FSK signal that the low frequency (0.905 MHz)
represents the logic high while the high frequency (1.06 MHz) represents the
logic low. The FSK amplitude is 6Vp−p .
In our FSK system we know that the free running frequency is = 1.024 MHz,
and by assuming Co = 50pF we got a value of Ro = 6.3KΩ which also turned to
be not true when implemented, and by referring to the data sheets related to this
IC especially to a figure entitled VCO frequency, we can see that this formula
does not apply for frequencies that exceed 1 MHz. Again by methodical tests
and measurements, a value of 1.1KΩ(R2 2 + P ot2 ) was put instead to obtain
the lock range1 of the FSK frequencies we are working at as can be seen in
Fig.(3.8).The formula can be verified as in the following relationship:
0.056
fo = (3.5)
Ro Co
Notice that the output of this circuit is applied to a high pass filter (composed
of the capacitor 0.22µF (C4 ) and the resistor 100KΩ(R23 )), and by applying
1
the relation f = 2πRC for passive filters) which also acts as a differentiator
with a cutoff frequency of almost 8 KHz (in our design about 7.2 KHz), this
would output a remarkable inverted signal that detects the input signal, and
by applying this output to a level detector(comparator U6/2 ) this gave us a
signal identical to the one at the input of the modulator but inverted. This
output is then applied to a low pass filter (R24 &C6 ) to get rid of high frequency
components. In order to reconstruct a digital output the same as the one at the
input with the same data rate and also for protection purposes, this signal is
applied to a digital inverter (U9/4 ) . The whole circuit for the receiver and the
transmitter is shown in Fig.(3.9):
the filters that worked with this IC were all passive, while in our simulations
Sallen-Key active filters were essential to get an acceptable output at the re-
ceiver as shown in Fig.(3.12). In this section calculations, simulations, and the
implementation will be discussed each in a separate part.
input word signal (assumed here 11001010) and the PSK signal output from the
multiplier are shown in Fig.(3.11):
We can clearly see from Fig(3.11) the phase transitions (The PSK signal in
the bottom) when the logic level goes either from high to low or from low to
high. Note: In simulation, ideal components were used, and this would result in
having ideal outputs which are not the case in practice, so extra circuits such as
filters would be needed. Also the signals may have DC offset at the ICs’ outputs
so coupling capacitors were added. Added to that, some ICs turned out to be
current driven, which means that we have to add extra capacitors and resistors
connected to them. That’s why the practical schematic is a little bit different
than the simulated one as will be seen later.
Gain 1 2 4 6 8 10
R1 1.422 1.126 0.824 0.617 0.521 0.462
R2 5.399 2.250 1.537 2.051 2.429 2.742
R3 Open 6.752 3.148 3.203 3.372 3.560
R4 0 6.752 9.444 16.012 23.602 32.038
C1 0.33C C 2C 2C 2C 2C
Table 3.1: Second order Low Pass Batterworth Filter design values (All resistor
values are in KΩ ).
works as a level detector to give a digital wave which is applied to digital gates
as in the procedure done for the FSK system in order to obtain a digital level
and for protection purposes. As we said before the carrier for our PSK system
is 512 KHz and the data output from the demodulator should have the same
data rate as the one at the input of the modulator (which is 64 KBPS), so the
low pass filter at the output of this demodulator was designed as follows:
Because the data rate for this system is 64 KBPS we chose 70 KHz to be
the cutoff frequency. For this low pass filter to operate at this frequency, we
selected a value for the capacitor of 1 nF in our design. Then, we chose the
gain of the filter which is in our design a gain of 2. We applied the relationship
[EM88]:
10−4
K=
f Ca1
in order to calculate K. With the K constant calculated, and by referring to
Table(3.1) we can calculate the values of the resistors of the filter.
So by applying the above relationship K was found to be 1.428 so the values
of the
resistors was found as follows:
CHAPTER 3. CIRCUIT DESIGN 28
Vs ≤ I 5 R e (3.7)
V−−φ
R5 = − 500 , where φ = 0.75V at 25◦ C (3.8)
I5
We will use V − as -8.2V, which is taken from the 7908 Regulator output.
The input current is assumed to be 1.22 mA(since at least 1 mA should flow in
the divider). Plugging these values in Eq.(3.8) yields:
8.2 − 0.75
R5 = − 500 = 5.6KΩ
1.22m
⇒ V5 = −6.8V = VBQ7 = VBQ8
⇒ IQ7 = IQ8 = IQ9
here V6 ≈ V12 , V7 ≈ V8 , V1 ≈ V4 .
If we use 2.7kΩ Load resistors at pins 6 and 12, then
Using a divider network between VCC Pin 8 and the Ground, the voltage at pin
8 will be:
V8 = 12 × 0.5 = 6V
Since pin 8 and pin 10 are connected together via a 51Ω resistor, then V 8 ≈ V 10.
By this we satisfy the first equation in Eq.(3.9).
To satisfy the second equation in Eq.(3.9), we have V8 ≈ V10 = 6V
51
V1 = V4 = −8.2 × 25k = −0.017V
⇒ second equation is satisfied.
Finally to satisfy the third equation in Eq.(3.9), we have
V5 = −1.22m × 5.6k = −6.8V
Substituting in the third equation ⇒ 30V > [3 − −6.8] > 2.7V .
Now as for C1 and C2 , their reactance should be no more than 5Ω at 1.024
MHz.
1
Zc1 = Zc2 = (3.10)
2πf C
1
⇒ C1 = C2 =
2π × 5 × 1024
here we chose C2 = C1 = 47nF .
RL 25m
Going back to Eq.(3.6), we have 1 = RE +2re , re = I5 = 20.5Ω.
.
By this we come to the end of the design of the MC1496 Balanced Modulator.
Now we can add these components to the IC to obtain the modulator we are
looking for. See Fig.(3.17) for a complete circuit schematic. One more thing to
mention is that the capacitor values were designed for a carrier of 1.024 MHz,
but after we implemented and tested the performance of the circuit for the Q-
PSK system, it turned out that a frequency of 512 KHz for the carrier will have
a much better performance than the 1.024 MHz, so we fixed our carrier at 512
KHz, and the capacitor values were not changed. The circuit actually worked
well.
This transfer function has two poles, the first one occurs at R551C12 and the other
at R561C13 . A Bode Plot of a low pass filter illustrates a 45◦ phase shift between
the input and the output at the pole. Since we have two consecutive low pass
filters, this means that the output signal of such a combination will be 90◦
phase shifted from the input signal. We chose R55 = R56 = 680Ω, and C12 =
C13 = 1nF , this gave us a double pole at 1.4 MHz. A remarkably attenuated
sine wave of 2.1Vp−p with almost 90◦ phase shift was obtained. The output of
this phase shifter was connected to one stream as is (the even stream), while
the other carrier input was attenuated to a level (by the divider R57 = 1.5kΩ
and R58 = 330Ω as shown on the schematic) almost 15 of the one from the
function generator to get a carrier equal to the one at the output of this phase
shifter, which would be then applied to the other stream (the odd stream). The
carrier applied from the function generator was 12Vp − p, and the output was
2.1Vp−p after the phase shifter (when measured it was found 1.2V dc because of
loading effect when connected to the multiplier). This was proved by the former
simulation for the phase shifter, at 512 KHz the attenuation was almost 15 dB
on the bode plotter while in calculations was as follows:
Vi 12
dB = 20Log( ) = 20Log( ) = 15.1dB
Vo 2.1
so the voltage divider must output a signal almost identical to the one at the
output of this phase shifter. In the Q-PSK simulation, there was no need to
simulate phase shifting because we were able to apply two cosine waves with
phase shift of 90◦ at the multiplier as can be shown in Figures (3.24) and (3.26).
parallel to serial conversion at the receiver .This can be illustrated from the
demultiplexer circuit in Fig.(3.19) and the multiplexer circuit in Fig.(3.22) As
we said before data for the Q-PSK system needs to be demultiplexed at the
input of the transmitter. The input data rate is 128 KBPS for a word 01101000
assumed for simulation. The thing needed here is to have two streams even and
odd one each of 64 KBPS as follows :
The even stream is 1000 and the odd one is 0110. We can notice that the clock
for the upper flip flop which is 64 KHz is the inverted clock of the lower one,
this caused the input word to be separated into two different streams each of
64 KBPS. Simulated output proved that the even stream lags the odd one with
a bit duration of 7.8µs (half a bit), and to have the first bit of the even stream
arrive to the upper multiplier at the same instant the first bit of the odd one
does, an additional flip flop with a clock of 128 KHz was added to the lower
stream to correct this delay other wise incorrect results would be obtained at
the output of the Q-PSK transmitter as can be seen in Fig.(3.19). Another
thing, in our board the last flip flop’s clock was of 64 KHz added to the upper
stream not to the lower one, this is because in practice the delay was found to
be of bigger duration than simulation (delay of 1 bit) in the odd stream not in
the even one(so the even stream should be delayed) as can be seen in Fig.(3.20)
which might be caused by the components in the circuit which would never work
ideally as in simulation.
Notice from Fig.(3.21):
1. The first two outputs which are the clocks, each of 64 KHz with inverted
CHAPTER 3. CIRCUIT DESIGN 36
wave forms.
2. The third output which is the input word 01101000 of 128 KHz.
3. Also we can notice from the last two outputs that they both begin at
the same instant of time (at the first positive edge of the inverted clock
). Before the addition of the delay flip flop to the lower stream, the
flipflop2’s output (the fifth wave form) appeared half a bit earlier, (at the
first positive edge of the clock) this is why this flip flop of clock 128 KHz
was added to the lower one. The even stream output 1000 and the odd
stream output 0110 each of 64 KBPS both begins now at the first positive
edge of the inverted clock as desired to be transmitted by the transmitter.
Now, these even and odd streams must be reconstructed again at the receiver
after the demodulators as can be seen later in the receiver part, but let’s assume
for the while that the same streams were obtained at these specific outputs
(which are1000 for even and 0110 for odd) for illustration purposes, a circuit
called multiplexer was used to mix these two streams into one (parallel to serial
conversion) to obtain the original input serial word from the word generator
which is 01101000 as can be seen in Fig.(3.22). We can notice from Fig.(3.23)
Figure 3.23: Word in to demultiplexer, odd, even, word out from multiplexer
streams
CHAPTER 3. CIRCUIT DESIGN 37
that the input word at the input of the demultiplexer was reconstructed again
at the output of the multiplexer. This proves the efficiency of the demultiplexer
and multiplexer circuits. Also from Fig.(3.22) notice that a flip flop U22/1 with
a clock of 128 KHz was added at the output of the demultiplexer, this was
needed here to correct the bit duration and the wave form at the output. Also
two additional flip flops U19/1 and U19/2 with clocks of 64 KHz were added at
the output of each stream’s level detector before being multiplexed for the same
purpose, this will be shown later in the Q-PSK receiver schematic Fig.(3.26).
used for the Q-PSK system after the demultiplexer are the same ones used for
the PSK system, so there is no need to discuss them again. To be mentioned
here is the difference in leveling circuits, in PSK simulations we amplified the
signal coming out from the word generator (TTL word) to get a level of 10 V
data word because in implementation the word level is also of CMOS level, here
in the Q-PSK system the flip flops used (in simulation) for the demultiplexer are
TTL flip flops so the output level is a TTL level which is 5 V, leveling should be
made according to this output which is not the case in implementation where
the output level of the flip flops used are of CMOS level . In other words in
our implementation the DC level was -5 V dc needed after the CMOS flip flops
which is the same in PSK circuits while in simulation for the Q-PSK system the
level is -2.5 V dc needed after the TTL flip flops .
By referring to the data sheets of the IC LM359 ,it was found that capaci-
tors of 1 nF each should be connected at the inputs of the summer (C16 , C17 ),
and during implementation a small capacitor of 100 pF (C18 ) was connected
to ground at the output in order to voltage drive this output (current driven
output) and not enough to drive the following buffer (U11/2 ).
• Up, Down, Down, Down : This would enable the FSK system and discon-
nects the PSK input streams.
• Down, Down, Down, Up : This would enable the PSK system (only the
odd stream) and disconnects the FSK and the even input streams.
3
c Protel PCB and Schematic are registered programs for Protel Technologies.
CHAPTER 3. CIRCUIT DESIGN 41
• Down, Up, Up, Down : This would enable the Q-PSK system (odd and
even streams) and disconnects the FSK input stream.
CHAPTER 3. CIRCUIT DESIGN 42
Results
This chapter will demonstrate the final results and output waveforms obtained
from the system we designed. This chapter will be divided into three sections,
one will illustrate the output signals obtained from the FSK system, the other
for the PSK, and the final one will demonstrate the QPSK waveforms. These
graphs were taken using a Tektronix Digital Oscilloscope.
46
Chapter 5
5.1 Conclusion
Our project was successfully completed with all the circuits functioning prop-
erly. The design demonstrated three of the most common digital modulation
techniques used these days in communications. The circuits were first built and
tested on a breadboard, then we designed a PCB and attached the components
to it. It worked successfully.
Our main aim was to demonstrate these techniques for educational purposes.
We think that our design is reliable, and is intended to be used in the digital
communication Lab for Educational purposes. That is based on the fact the
circuits were built from commercial ICs that are familiar to all students. Also
the PCB was designed in a way to be placed on an existing Power Supply base
in the lab that is used for other modules, which mean that such a board will be
easily set up in the lab.
The PCB was designed with great care in order to have the least chance of
having routing errors that might affect the system performance. Circuit design
with the least amount of components was utilized.
Designing this system involved many thoughts. These included researching
ideas, and components, considering simplicity, efficiency, reliability, coast, and
size. We think that the system as a whole was a total success!
47
CHAPTER 5. CONCLUSION AND FURTHER ENHANCEMENTS 48
[Hay88] Simon Haykin. Digital Communications. John Wiley and Sons, second
edition, 1988.
[Hay94] Simon Haykin. Communication Systems. John Wiley and Sons, third
edition, 1994.
49