Four independent DMA channels, each with separate registers for Mode Control, Current Address, Base Address, Current Word Count and Base Word Count. Designed to improve system performance by allowing external devices to directly transfer information to or from the system memory. Each channel has a full 64K address and word count capability. An external EOP signal can terminate a DMA or memory-to-memory transfer.
Four independent DMA channels, each with separate registers for Mode Control, Current Address, Base Address, Current Word Count and Base Word Count. Designed to improve system performance by allowing external devices to directly transfer information to or from the system memory. Each channel has a full 64K address and word count capability. An external EOP signal can terminate a DMA or memory-to-memory transfer.
Four independent DMA channels, each with separate registers for Mode Control, Current Address, Base Address, Current Word Count and Base Word Count. Designed to improve system performance by allowing external devices to directly transfer information to or from the system memory. Each channel has a full 64K address and word count capability. An external EOP signal can terminate a DMA or memory-to-memory transfer.