Counter Tutorials QU. Design a synchronous mod-6 counter using D-type flip-flops to count through the sequence 0, 2, 3, 6, 5, 1,0, (@) Determine the minimal SOP expressions for a synchronous mod-6 counter, (6) Deduce if the counter is selfstarting, should it fall into an unused state when switched on, . (©) Implemenc the mod-6 counter on the PALIGRG6 device. Q2._ Design a synchronous mod-5 counter using JK flip-flops that counts the sequence 0,1, 5,2, 6,0, (a) Determine the minimal SOP expres ns for asynchronous mod-6 counter. () Deduce if the counter is self-starting, should it fall into an unused stare when first switched on, Q3. Design a synchronous sequential generator, using the 74LS112A negative-edge-tiggered J-K flip flops and any necessary logic gates, to count the sequence 0, 1, 3, 4, 5, 7 and 7, 5, 4, 3,1, 0 controlled by an inpue D. The circuit is to be designed to count up when D = 0 and count down when D = 1. To prevent it from “hanging up” in one of the unused states, the circuit should return to the 0 state, should it happen to power on in an unused state,Solution Q3. State Diagram State Transition Table Excitation Inputs Present State Tiare Sequence ip Ke Jy Ky Jy Ko & Q BonvSeHvoHvoH use a BUH we eH UHH Sn von tH ton sow UT wuvoonvoScH UU UHH conve snvyySCOcUT A ORM OM HOH HO COCS lop SHH Onn HS eSDSCCS oan en Henson cccs loo mS on SoH OOH OHHH econ nA SHH Ho co OKK BBEEFEGEAABGEREER Rott tT Ta tt tte tt GAEASHRASAEFEAES JK FF Excitation Table elo wo)JK Excitation Inputs = QOD + -Q)eD K,=0D+Q-D = Q-D+ OD =0,®D K=1 K,=Q*D+Q-D=9,8Da. State diagram of the mod-6 counter: State Transition Table: State Assignment: Qe Qn Qa ‘State | Present State | Next State | Flip-flop Inputs Sequence [Oc Qn Qa| QO; @;|Dc De Da S75,[0 0 Ofo 1 Ofo0 1 0 $78] 1 of o*1 tlo 41 4 Sos] 1 1f1r 1 of1 1 0 S7S]}1 1 0/1 0 1f1 0 1 S7s,{1 0 1/0 0 1fo0 01 Sos [9 0 1]0 0 o|o 0 0 K-maps: m 4 GON 01 OeON 40 4 1 O0N 0Unused states are: S, and S,, ‘State | Present State Counter Stage Inputs ‘Next State a D. 2, 2, 2 a ao - 22,420, 9.0,+9,0, 9. +2,0, a a) 0 wt 1 a [,0me lee gs [iia 1 1 0 1 tou ‘The circuit is self starting as it returns from an unused stare to a valid stave after one dock cycle For the PALIGR6 implementation: Place x's at the following intersections: Columns Zu 11, 15 1,14 Place X's within AND gates in rows 10 — 15; 18 ~ 23; 26-31. Remaining Input, 1/O and output pins ate NC (no gonnection) Rows 8 16 7 24 25 ‘Comments QQs 2,0, 22, 2,0, 20,