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PIC16C84: 8-Bit CMOS EEPROM Microcontroller
PIC16C84: 8-Bit CMOS EEPROM Microcontroller
PIC16C84
• 14-bit wide instructions RA4/T0CKI 3 16 OSC1/CLKIN
1K x 14 RAM EEPROM
8 Level Stack File Registers EEDATA Data Memory
(13-bit) 36 x 8 64 x 8
Program
Bus 14 7 RAM Addr EEADR
Addr Mux
Instruction reg
MUX
Power-up
Timer I/O Ports
Instruction Oscillator
Decode & Start-up Timer
Control ALU
Power-on RA3:RA0
Reset
Timing Watchdog RB7:RB1
Timer W reg
Generation
RB0/INT
MCLR 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an
active low reset to the device.
PORTA is a bi-directional I/O port.
RA0 17 17 I/O TTL
RA1 18 18 I/O TTL
RA2 1 1 I/O TTL
RA3 2 2 I/O TTL
RA4/T0CKI 3 3 I/O ST Can also be selected to be the clock input to the TMR0 timer/
counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software pro-
grammed for internal weak pull-up on all inputs.
RB0/INT 6 6 I/O TTL RB0/INT can also be selected as an external interrupt pin.
RB1 7 7 I/O TTL
RB2 8 8 I/O TTL
RB3 9 9 I/O TTL
RB4 10 10 I/O TTL Interrupt on change pin.
RB5 11 11 I/O TTL Interrupt on change pin.
RB6 12 12 I/O TTL/ST (2) Interrupt on change pin. Serial programming clock.
RB7 13 13 I/O TTL/ST (2) Interrupt on change pin. Serial programming data.
VSS 5 5 P — Ground reference for logic and I/O pins.
VDD 14 14 P — Positive supply for logic and I/O pins.
Legend: I= input O = output I/O = Input/Output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
User Memory
an indirect address pointer specifies the address of the
Space
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
Bank 0
00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu
02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000
03h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
05h PORTA — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
07h Unimplemented location, read as '0' ---- ---- ---- ----
08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu
09h EEADR EEPROM address register xxxx xxxx uuuu uuuu
0Ah PCLATH — — — Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Bank 1
80h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ----
0Ah PCLATH — — — Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred
to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
PC GOTO, CALL The stack operates as a circular buffer. That is, after the
PCLATH<4:3> 11 stack has been pushed eight times, the ninth push over-
2 Opcode <10:0> writes the value that was stored from the first push. The
tenth push overwrites the second push (and so on).
PCLATH
If the stack is effectively popped nine times, the PC
value is the same as the value from the first pop.
4.3.1 COMPUTED GOTO Note: There are no status bits to indicate stack
A computed GOTO is accomplished by adding an offset overflow or stack underflow conditions.
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 word block). Refer to the
application note “Implementing a Table Read” (AN556).
The INDF register is not a physical register. Address- EXAMPLE 4-2: HOW TO CLEAR RAM
ing INDF actually addresses the register whose USING INDIRECT
address is contained in the FSR register (FSR is a
ADDRESSING
pointer). This is indirect addressing.
movlw 0x20 ;initialize pointer
EXAMPLE 4-1: INDIRECT ADDRESSING movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
• Register file 05 contains the value 10h
incf FSR ;inc pointer
• Register file 06 contains the value 0Ah btfss FSR,4 ;all done?
• Load the value 05 into the FSR register goto NEXT ;NO, clear next
• A read of the INDF register will return the value of CONTINUE
10h : ;YES, continue
• Increment the value of the FSR register by one
An effective 9-bit address is obtained by concatenating
(FSR = 06)
the 8-bit FSR register and the IRP bit (STATUS<7>), as
• A read of the INDF register now will return the
shown in Figure 4-7. However, IRP is not used in the
value of 0Ah.
PIC16C84.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
00 01 10 11
00h 00h
not used not used
0Bh
0Ch
Addresses
Data map back
Memory to Bank 0
2Fh
30h
7Fh 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
EN
RD PORT
05h PORTA — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
RD Port
EN RD Port EN
Set RBIF
RB0/INT
From other Q D
RB7:RB4 pins
RD Port
EN
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
RD Port 2: I/O pins have diode protection to VDD and VSS.
RB0/INT bit0 TTL Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up.
RB6 bit6 TTL/ST(1) Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(1) Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when used in serial programming mode.
Value on
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on
other resets
Reset
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
OPTION_ 1111 1111 1111 1111
81h RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
REG
5.3.1 BI-DIRECTIONAL I/O PORTS The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
Any instruction which writes, operates internally as a valid at the beginning of the instruction cycle (Figure 5-
read followed by a write operation. The BCF and BSF 5). Therefore, care must be exercised if a write followed
instructions, for example, read the register into the by a read operation is carried out on the same I/O port.
CPU, execute the bit operation and write the result back The sequence of instructions should be such that the
to the register. Caution must be used when these pin voltage stabilizes (load dependent) before the next
instructions are applied to a port with both inputs and instruction which causes that file to be read into the
outputs defined. For example, a BSF operation on bit5 CPU is executed. Otherwise, the previous state of that
of PORTB will cause all eight bits of PORTB to be read pin may be read into the CPU rather than the new state.
into the CPU. Then the BSF operation takes place on When in doubt, it is better to separate these instruc-
bit5 and PORTB is written to the output latches. If tions with a NOP or another instruction not accessing
another bit of PORTB is used as a bi-directional I/O pin this I/O port.
(i.e., bit0) and it is defined as an input at this time, the
Example 5-1 shows the effect of two sequential read-
input signal present on the pin itself would be read into
modify-write instructions (e.g., BCF, BSF, etc.) on an
the CPU and rewritten to the data latch of this particular
I/O port.
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the content EXAMPLE 5-1: READ-MODIFY-WRITE
of the data latch is unknown. INSTRUCTIONS ON AN
I/O PORT
Reading the port register, reads the values of the port
;Initial PORT settings: PORTB<7:4> Inputs
pins. Writing to the port register writes the value to the ; PORTB<3:0> Outputs
port latch. When using read-modify-write instructions ;PORTB<7:6> have external pull-ups and are
(i.e., BCF, BSF, etc.) on a port, the value of the port pins ;not connected to other circuitry
is read, the desired operation is done to this value, and ;
this value is then written to the port latch. ; PORT latch PORT pins
; ---------- ---------
A pin actively outputting a Low or High should not be
BCF PORTB, 7 ; 01pp ppp 11pp ppp
driven from external devices at the same time in order BCF PORTB, 6 ; 10pp ppp 11pp ppp
to change the level on this pin (“wired-or”, “wired-and”). BSF STATUS, RP0 ;
The resulting high output current may damage the chip. BCF TRISB, 7 ; 10pp ppp 11pp ppp
BCF TRISB, 6 ; 10pp ppp 10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note:
PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB
Instruction followed by a read from PORTB.
fetched MOVWF PORTB MOVF PORTB,W
write to NOP NOP
PORTB Note that:
RB7:RB0 data setup time = (0.25TCY - TPD)
where TCY = instruction cycle
Port pin
sampled here TPD = propagation delay
TPD Therefore, at higher clock frequencies,
Instruction
executed NOP
a write followed by a read may be
MOVWF PORTB MOVF PORTB,W
write to problematic.
PORTB
Data bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0 register
RA4/T0CKI clocks
Programmable 0 PSout
pin Prescaler
T0SE (2 cycle delay)
3
Set bit T0IF
PS2, PS1, PS0 PSA on Overflow
T0CS
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
GIE bit
(INTCON<7>)
PC PC PC +1 PC +1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h)
Instruction Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h)
executed
When an external clock input is used for TMR0, it must Since the prescaler output is synchronized with the
meet certain requirements. The external clock internal clocks, there is a small delay from the time the
requirement is due to internal phase clock (TOSC) external clock edge occurs to the time the Timer0
synchronization. Also, there is a delay in the actual Module is actually incremented. Figure 6-5 shows the
incrementing of the TMR0 register after delay from the external clock edge to the timer
synchronization. incrementing.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Ext. Clock Input or
Prescaler Out (Note 2)
(Note 3)
Ext. Clock/Prescaler
Output After Sampling
TMR0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows ↑ indicate where sampling occurs. A small clock pulse may be missed by sampling.
M 8
0 1
RA4/T0CKI U M
X SYNC
pin U 2 TMR0 register
1 0
X Cycles
T0SE
T0CS
PSA Set bit T0IF
on overflow
0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS2:PS0
PSA
0 1
WDT Enable bit
MUX PSA
WDT
time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
Value on
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on
other resets
Reset
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged. - = unimplemented read as '0'. Shaded cells are not associated with Timer0.
Sequence
MOVLW AAh ;
Required
set when a write operation is interrupted by a MCLR MOVWF EECON2 ; Write AAh
reset or a WDT time-out reset during normal operation. BSF EECON1,WR ; Set WR bit
In these situations, following reset, the user can check ; begin write
the WRERR bit and rewrite the location. The data and BSF INTCON, GIE ; Enable INTs.
address will be unchanged in the EEDATA and
The write will not initiate if the above sequence is not
EEADR registers.
exactly followed (write 55h to EECON2, write AAh to
Interrupt flag bit EEIF is set when write is complete. It EECON2, then set WR bit) for each byte. We strongly
must be cleared in software. recommend that interrupts be disabled during this
EECON2 is not a physical register. Reading EECON2 code segment.
will read all '0's. The EECON2 register is used Additionally, the WREN bit in EECON1 must be set to
exclusively in the Data EEPROM write sequence. enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
7.3 Reading the EEPROM Data Memory code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
To read a data memory location, the user must write
updating EEPROM. The WREN bit is not cleared
the address to the EEADR register and then set control
by hardware
bit RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be After a write sequence has been initiated, clearing the
read in the next instruction. EEDATA will hold this value WREN bit will not affect this write cycle. The WR bit will
until another read or until it is written to by the user be inhibited from being set unless the WREN bit is set.
(during a write operation). At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
EXAMPLE 7-1: DATA EEPROM READ Interrupt Flag bit (EEIF) is set. The user can either
BCF STATUS, RP0 ; Bank 0
enable this interrupt or poll this bit. EEIF must be
MOVLW CONFIG_ADDR ; cleared by software.
MOVWF EEADR ; Address to read Note: The data EEPROM memory E/W cycle
BSF STATUS, RP0 ; Bank 1
time may occasionally exceed the 10 ms
BSF EECON1, RD ; EE Read
BCF STATUS, RP0 ; Bank 0
specification (typical). To ensure that the
MOVF EEDATA, W ; W = EEDATA write cycle is complete, use the EE
interrupt or poll the WR bit (EECON1<1>).
Both these events signify the completion of
the write cycle.
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not
used by Data EEPROM.
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-u R/P-u R/P-u R/P-u R/P-u
— — — — — — — — — CP PWRTE WDTE FOSC1 FOSC0
bit13 bit0
R = Readable bit
P = Programmable bit
U = Unimplemented bit,
read as ‘1’
- n = Value at POR reset
u = unchanged
bit 13:5 Unimplemented: Read as '1'
bit 4 CP: Code Protection bit
1 = Code protection off
0 = All memory is code protected
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up timer is enabled
0 = Power-up timer is disabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 =RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
External
Reset
MCLR
SLEEP
WDT WDT
Module Time_Out
Reset
VDD rise
detect S
Power_on_Reset
VDD
OST/PWRT
OST
Chip_Reset
10-bit Ripple counter R Q
OSC1/
CLKIN
PWRT
On-chip
RC OSC(1) 10-bit Ripple counter
Enable PWRT
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
R1
VDD • = 0.7V
R1 + R2
Wake-up
T0IF (If in SLEEP mode)
T0IE
INTF
INTE
Interrupt to CPU
RBIF
RBIE
EEIF
EEIE
GIE
CLKOUT 3
4
INT pin
1
1
INTF flag 5 Interrupt Latency 2
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h)
0
M Postscaler
WDT Timer 1 U
• X 8
8 - to -1 MUX PS2:PS0
PSA
WDT
Enable Bit
• To TMR0 (Figure 6-6)
0 1
MUX PSA
WDT
Time-out
A device may be powered down (SLEEP) and later The device can wake-up from SLEEP through one of
powered up (Wake-up from SLEEP). the following events:
1. External reset input on MCLR pin.
8.12.1 SLEEP
2. WDT Wake-up (if WDT was enabled).
The Power-down mode is entered by executing the 3. Interrupt from RB0/INT pin, RB port change, or
SLEEP instruction. data EEPROM write complete.
If enabled, the Watchdog Timer is cleared (but keeps Peripherals cannot generate interrupts during SLEEP,
running), the PD bit (STATUS<3>) is cleared, the TO bit since no on-chip Q clocks are present.
(STATUS<4>) is set, and the oscillator driver is turned
The first event (MCLR reset) will cause a device reset.
off. The I/O ports maintain the status they had before
The two latter events are considered a continuation of
the SLEEP instruction was executed (driving high, low,
program execution. The TO and PD bits can be used to
or hi-impedance).
determine the cause of a device reset. The PD bit,
For the lowest current consumption in SLEEP mode, which is set on power-up, is cleared when SLEEP is
place all I/O pins at either at VDD or VSS, with no invoked. The TO bit is cleared if a WDT time-out
external circuitry drawing current from the I/O pins, and occurred (and caused wake-up).
disable external clocks. I/O pins that are hi-impedance
While the SLEEP instruction is being executed, the next
inputs should be pulled high or low externally to avoid
instruction (PC + 1) is pre-fetched. For the device to
switching currents caused by floating inputs. The
wake-up through an interrupt event, the corresponding
T0CKI input should also be at VDD or VSS. The
interrupt enable bit must be set (enabled). Wake-up
contribution from on-chip pull-ups on PORTB should be
occurs regardless of the state of the GIE bit. If the GIE
considered.
bit is clear (disabled), the device continues execution at
The MCLR pin must be at a logic high level (VIHMC). the instruction after the SLEEP instruction. If the GIE bit
It should be noted that a RESET generated by a WDT is set (enabled), the device executes the instruction
time-out does not drive the MCLR pin low. after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
FIGURE 8-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit Processor in
(INTCON<7>)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction
fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
VDD
To Normal
Connections
Description: The contents of the W register are Description: The contents of W register are
added to the eight bit literal 'k' and the AND’ed with the eight bit literal 'k'. The
result is placed in the W register. result is placed in the W register.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
literal 'k' data W literal "k" data W
Example CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT prescaler= 0
TO = 1
PD = 1
Description: GOTO is an unconditional branch. The Description: The contents of register 'f' are incre-
eleven bit immediate value is loaded mented. If 'd' is 0 the result is placed in
into PC bits <10:0>. The upper bits of the W register. If 'd' is 1 the result is
PC are loaded from PCLATH<4:3>. placed back in register 'f'.
GOTO is a two cycle instruction.
Words: 1 Words: 1
Cycles: 2 Cycles: 1
Cycles: 1(2)
Example IORLW 0x35
Q Cycle Activity: Q1 Q2 Q3 Q4
Before Instruction
Decode Read Process Write to
W = 0x9A
register 'f' data destination
After Instruction
If Skip: (2nd Cycle) W = 0xBF
Z = 1
Q1 Q2 Q3 Q4
No-Opera No-Opera No-Operati
No-Operat tion tion on
ion
MOVWF Move W to f
MOVF Move f
Syntax: [ label ] MOVWF f
Syntax: [ label ] MOVF f,d
Operands: 0 ≤ f ≤ 127
Operands: 0 ≤ f ≤ 127
d ∈ [0,1] Operation: (W) → (f)
Operation: (f) → (destination) Status Affected: None
Status Affected: Z Encoding: 00 0000 1fff ffff
Encoding: 00 1000 dfff ffff Description: Move data from W register to register
'f'.
Description: The contents of register f is moved to a
destination dependant upon the status Words: 1
of d. If d = 0, destination is W register. If
Cycles: 1
d = 1, the destination is file register f
itself. d = 1 is useful to test a file regis- Q Cycle Activity: Q1 Q2 Q3 Q4
ter since status flag Z is affected. Decode Read Process Write
Words: 1 register data register 'f'
'f'
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Example MOVWF OPTION_REG
Decode Read Process Write to Before Instruction
register data destination
OPTION = 0xFF
'f'
W = 0x4F
After Instruction
Example MOVF FSR, 0 OPTION = 0x4F
After Instruction W = 0x4F
W = value in FSR register
Z =1
Example RETFIE
After Interrupt
PC = TOS
GIE = 1
OPTION Load Option Register
Syntax: [ label ] OPTION
Operands: None
Operation: (W) → OPTION
Status Affected: None
Encoding: 00 0000 0110 0010
Description: The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Words: 1
Cycles: 1
Example
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
1st Cycle Decode Read No-Opera Write to W, 2nd Cycle No-Opera No-Opera No-Opera
literal 'k' tion Pop from No-Operat tion tion tion
the Stack ion
Before Instruction
W = 0x07
After Instruction
W = value of k8
RLF Rotate Left f through Carry RRF Rotate Right f through Carry
Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] d ∈ [0,1]
Operation: See description below Operation: See description below
Status Affected: C Status Affected: C
Encoding: 00 1101 dfff ffff Encoding: 00 1100 dfff ffff
Description: The contents of register 'f' are rotated Description: The contents of register 'f' are rotated
one bit to the left through the Carry one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored W register. If 'd' is 1 the result is placed
back in register 'f'. back in register 'f'.
C Register f C Register f
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
register data destination register data destination
'f' 'f'
DS30445A - page 70
ICEPIC Low-Cost
In-Circuit Emulator
PIC16C84
✔ ✔ ✔ ✔ ✔ ✔
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MPLAB
Integrated
Development
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Programmers
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KEELOQ
✔
All timings are measured between high and low measurement points as indicated in the figure.
VDD/2
RL Pin CL
CL VSS
Pin
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2.
15 pF for OSC2 output.
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3 4 4
CLKOUT
OSC1
10 11
22
CLKOUT 23
13 12
14 19 18
16
I/O Pin
(input)
17 15
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O Pins
TABLE 11-5 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
RA4/T0CKI
40 41
42
1.10
Rext ≥ 10 kΩ
1.08 Cext = 100 pF
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0 10 20 25 30 40 50 60 70
T(°C)
Average
Cext Rext
Fosc @ 5V, 25°C
20 pF 3.3k 4.68 MHz ± 27%
5.1k 3.94 MHz ± 25%
10k 2.34 MHz ± 29%
100k 250.16 kHz ± 33%
100 pF 3.3k 1.49 MHz ± 25%
5.1k 1.12 MHz ± 25%
10k 620.31 kHz ± 30%
100k 90.25 kHz ± 26%
300 pF 3.3k 524.24 kHz ± 28%
5.1k 415.52 kHz ± 30%
10k 270.33 kHz ± 26%
100k 25.37 kHz ± 25%
*Measured in PDIP Packages.The percentage variation indicated here is part to part variation due to normal process
distribution. The variation indicated is ±3 standard deviation from average value.
5.0
Rext = 3.3k
4.5
4.0
Rext = 5k
3.5
FOSC (MHz)
3.0
T = 25°C
2.5
2.0
Rext = 10k
1.5
1.0
Rext = 100k
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
2.0
1.8
Rext = 3.3k
1.6
1.4
FOSC (MHz)
Rext = 5k
1.2
1.0
0.8
Rext = 10k
0.6
T = 25°C
0.4
Rext = 100k
0.2
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 12-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD (Cext = 300 pF)
1.1
1.0
0.9
0.8
T = 25°C
0.7
Rext = 3.3k
FOSC (MHz)
0.6
0.5
Rext = 5k
0.4
0.3
Rext = 10k
0.2
0.1
Rext = 100k
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
60
50
40
IPD (µA)
30
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
60
50
40
IPD(µA)
30
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
120
100
85°C
e mp. =
80 Max. T
25°C
IPD(µA)
emp. =
Typ. T
60
-40°C
emp. =
40 Min. T
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
120
100
85°C
emp. =
80 Max. T
25°C
mp. =
IPD(µA)
e
Typ. T
60
0°C
40
. Te m p. = -4
Min
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
* IPD, with Watchdog Timer enabled, has two components: The leakage current which increases with higher temperature
and the operating current of the Watchdog Timer logic which increases with lower temperature. At -40°C, the latter
dominates explaining the apparently anomalous behavior.
2.0
1.8
Max (-40°C to +85°C)
1.6
Typ @ 25°C
VTH(Volts)
1.4
1.2
0.8
0.6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 12-10: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
vs. VDD
3.4
3.2
3.0
C)
85°
2.8
o+
2.6 0° Ct
VTH (Volts)
x (-4 5°C
)
Ma (2
2.4 Typ
C)
85°
o+
2.2
° Ct
(-40
2.0 Min
1.8
1.6
1.4
1.2
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
1.5
1.0
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
1,000
IDD (µA)
100 6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
10k 100k 1M 10M 100M
FIGURE 12-13: MAXIMUM IDD vs. FREQ (EXT CLOCK, -40˚ TO +85˚C)
10,000
1,000
IDD (µA)
6.0V
5.5V
5.0V
4.5V
100 4.0V
3.5V
3.0V
2.5V
2.0V
10
10k 100k 1M 10M 100M
70
60
Max. 85°C
WDT Time-out Period (ms)
50
Max. 70°C
40
Typ. 25°C
30
Min. 0°C
20
Min. -40°C
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
10000
9000
8000
7000
6000
gm(µA/V)
5000
Max @ -40°C
4000
Typ @ 25°C
3000
Min @ 85°C
2000
1000
0
2.0 3.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)
250
225
200
175
Max @ -40°C Typ @ 25°C
150
gm(µA/V)
125
Min @ 85°C
100
75
50
25
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)
2000
1800
1600
Max @ -40°C
1400
Typ @ 25°C
1200
gm(µA/V)
1000
600
400
200
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)
-2
-4
-6
IOH (mA)
-8 Min @ 85°C
-10
-14
-16 Max @ -40°C
-18
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
-5
-10
Min @ 85°C
-15
-20
Max @ -40°C
IOH (mA)
-25
-35
-40
-45
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts)
35
Max. -40°C
30
Typ. 25°C
25
IOL (mA)
20
Min. +85°C
15
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
90
80
Max @ -40°C
70
60
IOL (mA)
Typ @ 25°C
50
40
Min @ +85°C
30
20
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
18
16
14
DMEM Max. E/W Cycle Time (ms)
12
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
n 1 α
E1
A1
A
R
c L
A2
B1
β
B p
eB
E1
p
E
2
B n 1
X
α
45 °
L
R2
c
A
A1
R1
φ
β L1 A2
The MCLR pin now has an on-chip MCLR pulse width (low) MCLR pulse width (low)
filter. The input signal on the MCLR = 350ns; 2.0V ≤ VDD ≤ 3.0V = 1000ns; 2.0V ≤ VDD ≤ 6.0V
pin will require a longer low pulse to = 150ns; 3.0V ≤ VDD ≤ 6.0V
generate an interrupt.
Some electrical specifications have IPD (typ @ 2V) = 26µA IPD (typ @ 2V) < 1µA
been improved (see IPD example).
Compare the electrical specifica- IPD (max @ 4V, WDT disabled) IPD (max @ 4V, WDT disabled)
tions of the two devices to ensure =100µA (PIC16C84) =14µA (PIC16F84)
that this will not cause a compatibil- =100µA (PIC16LC84) =7µA (PIC16LF84)
ity issue.
PORTA and crystal oscillator values For crystal oscillator configurations N/A
less than 500kHz operating below 500kHz, the device
may generate a spurious internal Q-
clock when PORTA<0> switches
state.
Recommended value of REXT for REXT = 3kΩ - 100kΩ REXT = 5kΩ - 100kΩ
RC oscillator circuits
GIE bit unintentional enable If an interrupt occurs while the Glo- N/A
bal Interrupt Enable (GIE) bit is
being cleared, the GIE bit may unin-
tentionally be re-enabled by the
user’s Interrupt Service Routine (the
RETFIE instruction).
R
RBIF bit ........................................................................ 21, 46
RC Oscillator ...................................................................... 43
Read-Modify-Write ............................................................. 23
Register File ....................................................................... 12
Reset ............................................................................ 35, 38
Reset on Brown-Out ........................................................... 43
S
Saving W Register and STATUS in RAM .......................... 46
SEEVAL Evaluation and Programming System .............. 69
SLEEP .................................................................... 35, 38, 48
Software Simulator (MPLAB-SIM) ...................................... 69
Special Features of the CPU .............................................. 35
Special Function Registers ................................................ 12
Stack .................................................................................. 17
Overflows ................................................................... 17
Underflows ................................................................. 17
STATUS ................................................................... 7, 14, 39
T
time-out .............................................................................. 39
Timer0
Switching Prescaler Assignment ................................ 29
T0IF ............................................................................ 46
Timer0 Module ........................................................... 25
TMR0 Interrupt ........................................................... 46
TMR0 with External Clock .......................................... 27
Timing Diagrams
Time-out Sequence .................................................... 41
Timing Diagrams and Specifications .................................. 78
TRISA ................................................................................. 19
TRISB ........................................................................... 21, 39
W
W ........................................................................................ 39
Wake-up from SLEEP .................................................. 39, 48
Watchdog Timer (WDT) ................................... 35, 38, 39, 47
WDT ................................................................................... 39
Period ......................................................................... 47
Programming Considerations .................................... 47
Time-out ..................................................................... 39
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