1] `include "power.

v"
module hardmul_tb();
reg clkin,resetin;
reg [3:0] datain;
wire [31:0] dataout;
power p0(.clk(clkin),.reset(resetin),.M(datain),.out(dataout));
initial
begin
#0 resetin=1'b1;
#10 datain=4'b0100;
end

always
begin
#0 clkin=1'b0;
#100 clkin=1'b1;
#100;
end

endmodule

2]`include "hardmul.v"
module power(M,clk,reset,out);
input [3:0] M;
input clk,reset;

reg [31:0] temp1=32'b00000000000000000000000000000001;

wire [31:0] temp2;
output reg [31:0] out;

hardmul H1(.A(M),.B(temp1),.clk(clk),.reset(reset),.C(temp2));
always@(posedge clk)
begin
#20 temp1=temp2;
#20 out=temp2;
end

endmodule

3]module hardmul(A,B,C,clk,reset);
input [3:0] A;
input [31:0] B;
output [31:0] C;
input clk,reset;
reg [31:0] temp;
reg [31:0] rslt;
reg [31:0] dummy;
reg i;
reg temp1;
reg temp2;

initial
begin
rslt=32'b00000000000000000000000000000000;
temp=32'b00000000000000000000000000000000;
dummy=32'b00000000000000000000000000000000;
i=4'd0;
end
always@(posedge clk)
begin
temp=32'b00000000000000000000000000000000;
if(reset)
begin
if(A[0])
begin
rslt={4'b0000,B};
rslt={rslt[31:0]};
temp=temp+rslt;
end

if(A[3])
begin
rslt={4'b0000,B};
rslt={rslt[28:0],dummy[2:0]};
temp=temp+rslt;
end

if(A[2])
begin
rslt={4'b0000,B};
rslt={rslt[29:0],dummy[1:0]};
temp=temp+rslt;
end

if(A[1])
begin
rslt={4'b0000,B};
rslt={rslt[30:0],dummy[0:0]};
temp=temp+rslt;
end
end
end
assign C=temp;
endmodule