RTL Design,Verification, DFT, Validation

Engineer for Product based company

We have RTL Design, Verification, DFT, Validation Engineer opening with top Product
based company, Noida India for 3 -10 yrs of exp. All these positions are based in Noida.
Please find below the job description

Position Title: Design Engineer/Lead

• Would be responsible for designing various functional blocks from initial

specification till tapeout and beyond.
• Would be responsible for all aspect of design activities including design
specification, logic design, design flow development, synthesis, behavioral and
gate level simulations and timing closure
• Should have excellent debugging capability
• Senior ASIC designers with experiences in all aspects of RTL design flow from
specification/architecture definition to design and verification
• Strong domain knowledge of Serial Interfaces, Multimedia, External Bus
Interfaces or Storage is preferred.
• Experience 3-10 Years in IP/SOC design with successful delivery of production
quality chips
• Familiarity with Computer architecture: knowledge of microprocessors, DSP,
Caches, bus protocols preferre

Position Title:Verification Engineer/Lead

Job Opportunity: Seeking highly motivated, energetic, team-oriented Engineer/Lead

willing to take the challenge of delivering the first pass success of complex
microcontroller based SoCs and IPs using the latest advanced verification languages and
methodology.

The Verification Engineer/Lead would be working with experienced and motivated team
of Systems, Physical design, DFT, Mixed Signal and other local/remote teams to address
the verification challenges in the context of the block, chip, and overall system, through
the use of simulation, hardware modeling, formal verification and active participation in
pre/post silicon validation.

Key Responsibilities

• Evaluate and deploy the evolving verification methodologies to handle

increasingly complex SoC/IP designs within aggressive, market-driven schedules.
• Ensure quality adherence during all stages of the project life cycle. Also carry out
a thorough analysis of existing processes and recommend and implement the
process improvements to ensure ‘Zero Defect’ chips
 • Encouraging and influencing technological innovations in the team
• Effectively manage highly energetic and intellectual team members through
coaching and mentoring, provide technical direction to team members on project
issues, and provide guidance and career planning to team members.
• Ensure that SMART metrics are established to measure the Design Verification
processes and goals.
• Ability to work well as part of a team both locally, and also with remote or multi-
site teams

Key Skills

• Self starter with 3-10 years of experience on SOC/Chip level/Cluster/IP

verification on multimillion Gate and complex Design with multiple clocks and
power domains with minimal supervision
• Testbench and Testplan development to address Analog/Mixed signal and
Testability aspects of the chip along with functional requirements
• Experience in microcontroller architecture, Cache, protocols like
AHB/AMBA,AXI, Memory(Flash, SRAM,DDR) and memory controllers
• Experience in automotive protocols like LIN, CAN,
Flex, Graphics/Multimedia/Networking protocols like Ethernet, USB, ITU T.656
would be an advantage
• Experience and working knowledge of HVLs (SV/C++/SC/e/VERA), HDLs
(Verilog/VHDL),PLI/DPI, simulators (NCSim/ModelSim/Questa/VCS)
• Exposure to formal verification methodology, assertions/SVA, functional
coverage, gate level simulations, verification planner and regression management
• Experience in Low power verification using CPF/UPF would be a big plus
• Exposure to pre silicon validation/emulation is an added advantage
• Leadership experience in quality management and quality improvement.

Position Title: Sr DFT Engineer

Key Responsibilities:

• Will be responsible for Designing & Implementing DFT techniques (Memory

BIST/Scan /On-Chip Compression/At-speed Scan/Boundary Scan/LBIST) on
Complex SOCs with Analog IPs to improve testability.
• Test Modes implementation & verification. Scan insertion including on-chip
compression.
• Test vector (Stuck-at/at-speed/path delay/IDDQ/Bridging fault) generation with
highest possible test coverage with lowest overhead & gate level simulation with
timing (SDF).
• Implementing memory BIST and Boundary scan & verification
• Aligning with Test Engineer/Product Engineer to understand testability
requirement for Zero Defect.
• Post-silicon bring-up support.
• Basic understanding of complete SOC flow.
 • Cross functional teams interaction for issue resolution.
• Participate in driving new DFT methodology and solutions to improve quality,
reliability and in system test and debug capability.
• Mentoring to new team members.

Key Skills:

• Master/Bachelor’s Degree in Electrical/Electronic Engineering

• 3-10 year(s) of working experience in DFT
• Must possess a strong knowledge of DFT including scan, BIST, on-chip scan
compression, fault models, ATPG, and fault simulation.
• Must have a firm understanding and hands-on experience on industry
standard DFT techniques: Memory BIST-Repair/ Scan/ On-Chip
Compression/At-speed Scan/Boundary Scan/LBIST in one or more complex
SOCs
• Strong Knowledge/Understanding of Synthesis & STA.
• Experience with Mentor’s DFT EDA tools is a plus.
• Programming in Perl, tcl and c++ is a plus
• Should be a team player and willing to work with cross functional teams in issues
resolution.
• Creative problem-solving skills and the ability to logically break complex
problems down to manageable components
• self-motivated
• Good written and verbal communication skill.
• Applicants must be willing to work in Noida.

Position Title: Sr. Functional Validation Engineer(Digital)

Key Responsibilities

• Development & bring-up of Pre Silicon Validation platforms like Palladium or

FPGA for the IP/SOC
• Development & bring-up of Silicon Validation platforms like Validation Board &
Silicon (EVB, ATE etc) for new IP/SOC design
• Development of validation plans, Coding and Debug of scenarios on Pre and Post
Silicon platform
• Creating and performing system use scenarios
• Methodology development for quality and execution efficiency
• Ability to work well as part of a team both locally, and also with remote or multi-
site teams.

Specific Knowledge/Skills

• 3-10 years of experience in validating IPs/SOC of multimillion Gate and complex

design with multiple clocks and power domains
 • Test plan and test code development to address functional and integration
requirements of the IP/SOC.
• Experience and working knowledge of verilog and C/C++ is must.
• Expertise of using compiler & debugging tools like CodeWarrior, GHS,
Lauterbach
• Good Software Architecture knowledge.
• Working knowledge of Palladium & FPGA platform
• Multilayer Board design, testing, integration capabilities
• Expertise of High Speed Industry protocol Validation like USB, SATA,
ETHERNET, DDR
• Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,
AXI, Memory (Flash, SRAM, DDR) and memory controllers
• Knowledge of Multimedia applications, embedded programming
• Expertise in using test equipments used in validation (Logic Analyzers, High
Speed Oscilloscope, Protocol Analyzers, Spectrum Analyzer, Network Analyzer)
• Experience in working on ColdFire, PowerPC, ARM core architectures would be
an advantage

If you are interested, Kindly forward your resume at spog-info@utkrist.com /

singh.sunistha@gmail.com

You can also refer your friends for these openings and get referral bonus of up to 70,000
Rs.

Regards,
Sunistha
http://spog.utkrist.com
91-9972936982