`timescale 10ns/1ns

//testbench module
module t;
//inputs to DUT as reg
//output as wires
wire cout,sum;//1-bit output
reg a,b,cin; //1-bit input
reg clk;
//instantiate top module to test
eor m(sum,cout,a,b,cin);
//initialize inputs & set simulation end time
initial begin
clk=1'b1;
#70 $finish; end
parameter clk_high=1;
//clock generator
always #clk_high clk=~clk;
//input signals generation
reg [2:0] cnt;//2-bit counter
initial cnt=0;
always @(posedge clk)
begin
cnt<=cnt+1;
a<=cnt[2];
b<=cnt[1];
cin<=cnt[0];
end
endmodule