31 LECTURE 7: FLIP FLOPS, COUNTING CIRCUITS AND SHIFT REGISTERS In the previous chapter we introduced the R-$ flip-flop. In this section we will start building on that basis, and will introduce several multistate devices whose outputs depend on past history. We start with the R-S flip-flop. . Q R The bars over the R and S indicate an “active low" device. If the § and R inputs are high either the state Q = 1, Q 0 or the state Q=0, Q = 1 is stable. If the R input is high and 5 is low, Q is "set" to 1; S is active low. If the § input is high and R is low, Q is "reset" to 0; R is active low. There are many situations in which we want any changes of states to be synchronized by a "clock" signal. The term “clock signal" suggests an evenly spaced set of timing Pulses, but the device terminal to which these pulses are directed (typically labeled CLK) will also work with any set of pulses, equally spaced or not. A simple example of "clocked" logic is the simple clocked R$ flip-flop. 5 ———_J ‘S Gated CLK As long as CLK is high the device works like an ordinary RS flip-flop. If CLK is low, R and § are high and the Q and Q outputs are held steady. Alternately we can say that if either R or S$ goes high it will have no effect on Q until CLK goes high.Another simple clocked logic circuit is a simplified D-type flip-flop. It is made from the circuit just described plus an inverter. D s Q CLK CLK R Q When the clock goes high Q will go to the state of D (data). When the clock goes low the D state is held, “latched,” in Q. The circuits we have been discussing still are not adequate for some applications, in particular the applications where the outputs help determine the state of the inputs. For example, suppose we connect a D-type flip-flop as given above to put out one pulse for every two clock pulses in; a divide frequency by 2 circuit. Ideally we would like this connection. CLK ak = Since Q goes to the state of D when the clock is high, and, since is opposite to Q, each time the clock rises the output state will change. The hope then is that each two clock cycles will result in one up-down cycle of Q. The problem is that while the clock is high when Q changes Q changes so D changes so Q changes and Q changes and D changes and ... We have a “race” condition. The solutions are more complicated circuits called "Master-Slave" and "Edged Triggered” flip-flops. In either of these configurations the output changes only at an edge of the clock pulse; it may be either the rising edge or the falling edge depending on the particular circuit. The master-slave configuration has some tricky aspects. Read pages 119 and 120 of “Electronics with Digital and Analog Integrated Circuits" by Higgins before using master-slave units. With these more complicated circuits the inputs before the clock edge determine the state of the outputs after the clock edge. No race condition can result. We do not build these fancy circuits with basic gates, but rather use already complete IC versions.Counting (or Scaling) Circuits One of the logic devices we will often use will be the 4027 Dual J-K Flip-Flop. Each Flip-Flop (or F/F) has 5 inputs: get, Reset, J, K and Clock. There are two ouputs, gq and 0, which are always, as the notation suggests, in complementary states. There are two modes of operation called clocked and direct. In clocked operation the outputs of logic blocks don't change immediately after their inputs change. Instead, the logic block waits until the rising edge on the clock input. Only then are output changes allowed. There are two essential steps to the logic process. In the setup step, inputs decide what the logic is going to do. In the clocking step, the logic block does what it was told to do during setup, and provides an output. For the 4027, in the clocked mode the Set and Reset should be grounded. Inputs on y and K provide the information for the setup, and the action occurs on the positive edge transition of the clock input. Below is a table illustrating the effects of y and K on the outputs Q and Q. s, is the state before clocking and s,,; is the state after clocking. Smt 1k Qe" 8 Tx 10 o x oo } a x 1 1 0 1 0 zx eee Oeerecee@geecag tee } oe x means it doesn't matter In the direct mode a "1" on Set forces q high and Q low. A "1" on the Reset forces Q low and Q high. A "1" on both g and g is disallowed. when either R or g is at a "1" it overrides any effect of I,K or the clock. Applications Voo - I = Qa Ss oR 10k jt | £] ie ln Co Ke 4 t InputScalar Let us see how to scale (count). First we connect several J-K E/E's together with the Q output of one connected to the clock input of the next. Such a clock connection configuration is called a ripple" configuration since there is time delay between flip-flops. The first must change causing the second to change which causes the third to change and so on. The propagation delay in each flip-flop leads to brief unintended outputs from the gis. in some applications this can lead to problems. Let g and g be at "0", and y and K at "1". Suppose initially all Q's are in the "0" state. Then during each positive going transition of the input signal, q, changes state Similarly each time Qy, goes from 1 to 0, Qy changes state. Each time Q) Joes from 1 to 0, Q3 changes state. We have the following results: time Q Qe to 0 0 count £ ede arr ocodep etc. etc. Thus, if we assign the first flip-flop the value 2°, the second the value 2', the third 2?,..., the n value 2", the system is counting in the binary number system. The particular circuit here counts from 0 to 7 then starts over. Thus it can be called an octal counter. Note also that Qj, Qy and Q, divide the input frequency by 2, 4 and 8, respectively. You Can see this by examining the truth table and/or the graphs below. Clock. Q Q Le jggieeteenasosuneetessseeteteesieateas! | Thus, this circuit can also be called a “divide by" counter, where division of the frequencies 2, 4 and @ are available.(a) Determine the counting sequence starting from Qi = Q2=Q3=0 if the flipflops "clock" on the falling edge as is the case for TTL logic ns.07776757%47%37%27170) (b) How would one reconnect the circuit so that it would count "up"? (ans. Connect the clock to Q's instead of Q's.) Shift Register This is a device for shifting data from one counter to the next each time a clock pulse occurs. Suppose we connect a series of J-K flip-flops together as follows (we assume that R and § are at “O"). This clock connection configuration is called a "synchronous" configuration since all chips are "clocked" together. uy a J Q SG Daw Is R Is R Is OR Input) CF] | fl fy ra : KG oF Ks GG, [= Ks Cs Suppose that at time to (before the first clock 0 * 1 transition) all Qs are in the "o" state, and Jj=1,K,=0. Then at time t) (after the first clock 0 % 1 transition) Q)=1, and Q=Q3=0. Now suppose Jj, goes to 0 and Kj goes to 1 and they stay there indefinitely. Now with Jo =1,K2=0, after the second clock transition, Q2 goes to 1 and all others are zero. The following sequence of events occurs: time J) Qi=J2 Q=33 Q3=Iq ete. pa 0 0 0 fia 1 0 0 % 0 0 1 0 ete, Thus during any transition the value on the Jj input is entered into the first flip-flop and the value contained in, say, the n™ flip-flop is transferred to the (n + 1)" flip-flop. In general, the data input changes will be synchronized with the clock.Modulo "m" Counter Suppose we want a counter which has only m states and goes through the states cyclicly. If m = 2° (n_an integer), there is no problem; we just use n flip-flops with Q, connected to Cj+j. But suppose we want something else with a minimum of flip-flops. We will need n flip-flops, where 2" 2 m, to have enough distinct Q combinations. Let us consider the simplest example, m = 3, Let us construct a suitable table of states: time QQ, Dy count @ 0 1 eee yo 1 30 T ete If we can construct such a system, we will have the desired counter Now we know toggling (connecting Q; to Cj+}) won't work, so let us connect the input to all clock inputs. Now let us see what states J|K) and J9K2 should be in. We will get the right transition at the first clock pulse if at time to we have JjKj = Ix and JpKj Ox. (Verify this with the truth table.) Let us now expand our table of states to include possible JK values. fm 9 @ OQ @ ioeae ae aig Oe te 0 1 oat Ix beeen ox xt ieraeeo ae T iz & Now examining the JjK, column, we see that we will get the correct J)Ky input if we connect K, permanently to the 1 state and I] to Q;. Similarly, everything is satisfied if we connect Jz to Q and Kj to Q Thus the following circuit is a modulo 3 counter. There are clearly other correct connection sets.OR Qa i, oR Q s Ss v. 7 i 7 WIR OO boG & Input Note also that this counter is a divide by 3 counter. Looking at Q) and recalling that there is one clock pulse for each state change, we see that for every 3 clock pulses, there is one Q) pulse. The pulse is, as shown below, not symmetric, being low twice as much time as it is high. Qa t—> Clock Exercise 2 Design a modulo 5 counter. Note: It might be necessary to "AND" two flip-flop outputs to get a J or K input. (Ans: One combination involves setting J3=Q)-Qg- Thus you would need one AND gate in addition to the J-K flip-flops. [Some integrated J-K flip-flops have built-in AND inputs to J and K. Ours do not.] The other inputs could be Jy = G, Jo = Q), Ki = 1, Kz = Qi and K3 = 1. Many other combinations also work.) For modulo m with m even but not equal to 2", you have a fairly simple problem. For instance, for modulo 6, use a toggled stage 1 and Jet Q| go to Cz and C3 where the second and third J-K flip-flops form a modulo 3 counter.Specialized Counters There are a number of specialized counters of various types. one of these is the 4029 Presettable Up-Down Binary-Decade Counter. This means that: a) the device is a counter that can be set to be a + 16 binary counter or a + 10 decade counter b} it can be set to count up or down c) the first number it counts from can be preset. com A BCD DSTO HOH eo HHO) 14 0 0 0 BED He ieee OTTO 3001 TeeHieO nae 0) 4 0b oO an) when set as See lOseseaigeeeectO decade counter 6 oO 1 1 0 when set asa 7 4 1 1 Oo binary counter TSG pastete reser steat | 59 1 0 0 4 pO datae( Soeeeeey (estas toeeeeet moot HEH OraEHEEL 2 0 0 4 1 aoe eee te 1 rn 1 1 Bd 1 1 1 Note that the outputs from A,B,C, and D are simply counting in binary. Thus each decimal number is "coded" as a binary number. This is called a Binary Coded Decimal (BCD) counter. The BCD output can be given to a BCD decoder-driver that will run a seven segment display (see later in this chapter). Note that, if used as a binary counter, some BCD decoders will not recognize the Binary Code for the numbers 10 > 15, others such as our NC14495 decode these as the hexadecimal numbers ATF, In normal operation, the Preset Enable and Carry In are held at ". If pin 9 is low, decade counting results; if pin 9 is high, binary counting is performed. If pin 10 is tied to a "1" the package counts up; if tied to a "0", it counts down. One count occurs on each positive edge of the clock. By bringing the Preset Enable high, the counter can be preset to whatever number is present at the "Jam" inputs. The Carry Out pin can be used to cascade counters.+N Counter The 4018 is a divide by N counter, where N can be 10, 9, 8, 7, 6, 5, 4, 3, or 2. It does not have a coded output count, however. Divide by 10, 8, 6, 4 or 2 is available by simply connecting 3, Qu, Ox, © or Q, to the Data Input. The output is taken from the Q which is fed back to the Data Input. Division by 8, 7, 5 or 3 is available by feeding Qe°Qs, Qa Qu, Q2° Qs or Qi+Q, to the Data Input. D Type FIF The 4013 is a dual D type flip-flop. Basically it is the same as a J-K F/E except that K is eliminated and I becomes D (for Data). Thus, instead of 4, there are only two ways the F/F can be clocked. If the D input is high, the F/F goes to or stays in the state with Q low and Q high, In the direct mode, R and § function as they do on the 4027. D types are useful in making shift registers, among other things. Displays The question of how to display the output of digital electronics is an important one. One good display is to turn a light on for a "1" and turn it off for a "0." The light could be a small light bulb or a small neon bulb. A method of growing popularity is to use a light-emitting diode (LED). The specification sheet for a popular LED is found in the appendix. The curves on the specification sheet show the light output to be about proportional to the current when the current flows from anode to cathode (i.e., when the anode is more positive than the cathode). The current grows exponentially with the voltage. For reasonable light levels, the current will be about 10 mA and the voltage across the LED 1.6 volts. The LED could be connected between a CMOS output and ground. The LgD will be on when the CMOS output is in the "1" state and off for the "0" state. However, when in the "1" state, the output won't rise much above 1.6 volts because of the loading of the LED. Since 1.6 volts is not a well defined "1" (on the contrary, it is a well defined zero), no other CMOS input may be driven in parallel with the LED. If you need to drive some CMOS inputs and the LED, then you can put a current limiting resistor between the CMOS output and the anode of the LED. For example, with Vpp = § volts and a current limiting resistor of 680%, the output is nominally 3.5 volts. This is 0.7 Vpp and thus Will be a "1" to other inputs. The diode current will only be about 2.7 mA. The LED won't be very bright. CMOS just does not have a large current source or sink capability. These data come from p. 43 of the “The CMOS Cookbook" by Don Lancaster.7-10 7-Segment Display In the appendix you will find the specifications for the MC14495 BCD to Seven Segment Decoder/Driver. This device has seven outputs and four inputs. The outputs are normally in the "0" state but rise to the "1" state for the proper segments of a seven-segment display corres~ ponding to the binary-coded decimal input: Decimal: 0 1 2 4 5 6 1 8 Binary: 0000 0001 0010 0011 0100 0101 0110 0111 1000 Segments at one (Hexa~ ee ' ' ' decimal) iz Decima 8 20 @ 12 43 ta 48 Binary: 1001 1010 1011 1100 1101 1110 1111 Segments at one: (eatise eg eee H rod I! (Hexa- eee IES: eee (yee ' decimal) In the "1" state, the MC14495 can source up to 11.5 mA per seg- ment. For convenience the segments are labeled as follow: There are a variety of devices available for seven-segment display, utilizing gas discharge, light-emitting diode arrays and various other gadgets. For display in the lab sessions, we will use a seven-segment display using LEDs. Any source of current for LEDs must have current limiting resistors. With many seven-segment display drivers these resistors are connected between the driver and the LEDs. The MC14495 is unusual in that it has the current limiting resistors included in the driver chip.