NMOS Fabrication

1
 Fabrication
The process used that creates the devices/wires.
• Look at how to create:
– Working transistors
• ndiff, pdiff, wells, poly, transistors, threshold adjust
implants
– Wires
• contacts, metal1, via, metal2

Fabrication is pretty complex.

• Give a brief overview of the process, for
background.
• Want to understand origin of layout rules / process
parameters
– The abstractions of the process for the designers (us). 2
 Semiconductor Review
• Create by doping a pure silicon crystal
– Diffuse impurity into crystal lattice
– Changes the concentration of carriers
• Electrons
• Holes
– More doping -> more carriers available
• n-type semiconductor (n or n+)
n+
n
– Majority carrier: electrons
– Typical impurity: Arsenic (Column V)
• p-type semiconductor (p or p+)
p+
– Majority carrier: holes
– Typical impurity: Boron (Column III)
3
 Other key working materials
• Insulator - Silicon Dioxide (SiO2)
– Used to insulate transistor gates (thin oxide)
– Used to insulate layers of wires (field oxide)
– Can be grown on Silicon or Chemically Deposited
• Polysilicon - polycrystalline silicon
– Key material for transistor gates
– Also used for short wires
– Added by chemical deposition
• Metal - Aluminum (…and more recently Copper)
– Used for wires
– Multiple layers common
– Added by vapor deposition or “sputtering”
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When a Transistor Gate is formed?
A transistor gate is formed wherever polysilicon crosses
diffusion (semiconductor) with oxide between these layers.

Buried contact
When there is no oxide between polysilicon and diffusion.
Here two conducting materials contact one another.
No transistor is formed

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Power Line
The 5v and 0v power line are implemented by in
metal because of its very low resistance.

Contact Cut

In order to allow metal and diffusion to contact,

metal is holed downed to the diffusion level and is
called contact cut.

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 NMOS Processing (Fabrication) 5V

Dep

NMOS Inverter with Vout

depletion load transistor
Vin
Enh
Our objective is to fabricate this Inverter

0V
7
 NMOS Processing (Fabrication) [Cont] 5V

Diffusion regions surrounding Dep

the gate areas are doped with n+
impurity and [Source and drain]
Vout
… Transistor is formed
Vin
Enh

0V
8
 NMOS Processing (Fabrication) [Cont] 5V

Dep

What should we do?

Vout

Vin
We need to alter threshold voltage……
Enh
Method used depletion implant

0V
9
 NMOS Processing (Fabrication) [Cont] 5V

PolySi cross Diffusion YES Dep

Buried contact
NO Vout

Vin
Enh
YES

Transistor Formed 0V
10
 NMOS Processing (Fabrication) [Cont]
5V

Dep

Contact cut Vout

Vin
Enh

0V 11
 NMOS Processing (Fabrication) [Cont]
5V

Starting Material:
Lightly doped p-type Si substrate Dep

Mask-1: defines all diffusion regions (active areas)

- drain
Vout
- source
- gate
- any diffusion lines used to interconnect ckts.
Vin
Areas external to the active are covered with isolating oxide Enh

P-type
0V
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NMOS Processing (Fabrication) [Cont] 5V

Dep
P-type

Vout
Mask-2:defines depletion implant regions
Vin
here n-type implantation used
Enh

P-type 0V
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 NMOS Processing (Fabrication) [Cont]
5V

P-type
Dep
Entire wafer is covered with a thin layer of Oxide

Vout
P-type
Vin
Enh
Mask-3: Define where Oxide is to be removed

P-type 0V
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NMOS Processing (Fabrication) [Cont]
5V

P-type
Dep

Vout

Covered with PolySi Vin

Enh

P-type
0V
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NMOS Processing (Fabrication) [Cont]
5V

P-type Dep

Mask-4 Defines area where PolySi is to be remain Vout

 all gate areas
 all PolySi to diffusion connection Vin
 all PolySi interconnection Enh

P-type
0V
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NMOS Processing (Fabrication) [Cont] 5V

P-type Dep

An unmask n+ diffusion now defines all Vout

source and drain regions
Vin
Enh

P-type

0V
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 NMOS Processing (Fabrication) [Cont] 5V

Dep
P-type

Wafer is covered with insulating Oxide which Vout

will insulate PolySi and diffusion from metal
Vin
Enh

P-type
0V
Wafer is heated to provide smooth surface and to drive-in the n+ region
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 NMOS Processing (Fabrication) [Cont]
5V

Dep
P-type

Mask-5 define contact cut where Oxide is to be removed Vout

Vin
Enh

P-type
0V
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NMOS Processing (Fabrication) [Cont]
5V

Dep
P-type

Vout
Covered with Al
Vin
Enh

P-type
0V
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 NMOS Processing (Fabrication) [Cont]
5V

Dep
P-type

Mask-6 specifies regions where Al is to be remain Vout

Vin
Enh

P-type
0V
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 NMOS Processing (Fabrication) [Cont]
5V

Dep
P-type

An Oxide overlay is grown to protect the surface Vout

Vin
Enh

P-type
0V
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NMOS Processing (Fabrication) [Cont]
5V

Dep

P-type
Vout

Vin
Mask-7 defines the area where Enh
overlay is etched away to allow the
contact between Al of the input and
output pads of the Chip and external
circuitry.
0V
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 Scaling

Book: Linda’s Book

Page: 56-57

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 Objectives
• Evolution of smaller line widths, feature size and
higher packing density.
• So need to understand the effects of scaling.
• Characteristics of Micro-electronic technology
– Minimum feature size.
– Number of gates on a chip.
– Power dissipation.
– Maximum Operational frequency
– Die size
– Production cost.

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• Improved by shrinking the dimensions of
transistors, interconnections and separation
between features
• And by adjusting the doping levels and power
voltages.
• In practice all dimensions are expressed in terms
of λ.
• A value is assigned prior to manufacture.
• Advantage of this approach: design rules not
become out dated.
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 Scaling
•The effects of scaling are most easily
considered by assuming that all geometric
dimensions (horizontal and Vertical) and
voltages are reduced by a constant factor
“a”.

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 old_width W
new width W   
scale_factor a

D
new thickness D 
a
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 L
new length L 
a

Vp
new supply voltage V p 
a

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 Vte
new enhancement device threshold Vte 
a

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 Saturation Current

 nW  I
I  (V gs  Vt) 
2

2 LD a

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• Current per transistor decreases by a
factor “a”.
• a factor “a2” more scaled devices can be
placed on a similar sized chip.
• The current drawn from the supply
decreases by a factor “a”.
• The power supplied to a similar sized chip
is unaltered by scaling
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Capacitor C 

Circuit capacitances are reduced by

factor a

LW  C
C  
D a

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 Gate delay

C ' out
• gate delay ' 
W' '
L

• The gate delay is decreased by a factor a.

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 Gate Power
Vp  I
• gate power ' = Vp   I  = 2
a

• Gate power is reduced by a factor a2.

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 Speed Power Product
• Speed power product ' = gate _ delay 'Vp' I '
speed _ power _ product
=
3
a

Speed power product reduces by a factor a3.

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• Apart from the increase in current density on the
chip, the other effects of reducing features and
voltages are advantageous.

• However, another unwanted effect arises when

considering the delay down lines interconnecting
gates. Here, the length does not scale as the
chip is assumed to be of similar area. Hence, the
line length is constant.

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 Line Capacitance

• C i'=
LW '
= Ci
D'

• Capacitance remains same.

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 Line Resistance
L
• Ri 
W 'T '
• T ' new conductor depth.

• Ri = a2 Ri

• Line resistance scale up by a factor a2

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The delay down an interconnection line is
proportional to Ri ' C ' i and thus scale up by a
factor a2.

Delays in polysilicon and diffusion becomes

unacceptably large and delay down metal lines is
no longer negligible. This suggest that it will not
be sensible to scale all the features an identical
factor.
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