Pipelining / Pipelining is an implementation. pechnique tn which multiple cnstructions are over lapped cn execution. Pipedining is key +o making processors very fast. The MIPS pipeline we explore here has 5 seages: \) Fetch cnstvuction from memory, 2 Read veqisters while decoding the cnstyuction. 3) Execute the opevation ov calculate am address. 4) Auwess am operamd in data memory, 5) Write the result into a vegister. We vill turn to pipeline speed up. Tf the stages ane perfectly balanced, then the time between cuctructions on the pipelined machine is equal to Time betaeen instructions Pipelined = Time between cnstructions onpipe lined Number of pipe es To checkehis, consider 1003 instructions. Without pipelining seach instruction takes gus so total time veqwred is 1003xe = g024 nS. With pipe Liming each instruction takes only ams but after 3 tnstrun ctions have been executed with a time of lms (Fig: 63) when Pipelining becomes operational. The time neqpived is 1000x2414 = 2Oly ns: The vatio 24 =3-4RBS- Ie = “That is, he vatio of total execution times for veal, Programs on mon pipetined +o Pipelined machines is close to the vakio of times between tnstructions. This finding {5 wt tenable with tht above-formula-a Pipekining improves perform ance by tnereasing aan through put ) aS opposed to decreasing the execution time for am individual struction. Designing Instruction sets for pipelinng A. All MIPS Custructions are the same length. This vestriction makes it much easier to feech cnseru- ctions in the fixe pipeline stage amd to decode them in the second stage. 2 mips has only a fes instruction formats, with the Source vegister fields being located in the same place tn each tnetruction . This symmetry means that the second Stage cam begin veading the vegister file at the same time that the harduare ‘s determining what type of instruction was fetched. 3 Memory operands only appear on loads or stoves in MIPS. This restriction means wecam use the execute stage to calculate the memory address and then access memory cn the Followeny Stage. 4 Operands must be aligned in memory. Hence we need mor eerey shout & single Zata transfey nStrwct jon Yeytiuing eu0 data memory accesses; the nepquested data Cam be transfered between processoy amd memory cn a Single pipeline stage. Pipeline Hazards There ave Situations in Pipelining When the next insevuction can'€ execute in the Filloweng ryele,The fol. on just as example, to eight t (Sub), leimple- ‘ipetined tin this Ins for glecycle cle must gure 6.2. 8 Figure ilarly to ution of 4d fourth Ae must single- ghsome te must ‘ke only he time a. Ifthe ve pipe: G1 An Overview of Pipelining. Bre Tae Gas. Se 208 2 ne 208 2 1A in ne as 208 2s 208 2 Load word (Iv) ‘Store word (6) format (206, sub, ad, oF S18) Branch (bea) [FOURE 6.2 Total time for eight Inetructions eatoulated from the time for sach component. This clcula- tion assumes tht the muliplexrs, contol unt, PC acceses, and sign extension unit have no delay Crecton 2 4 6 8 0 2 4 6 eect ag {rn instvetons | 8, s0080 Pls [es [st — eo | 32 amo re = ea | st soa mer, ee te ‘order {ininsteevers) $1, 100160 1 $2, 200180 [m tw $3, 900480) aeeies | Poe ne 28 FIGURE 63 Singlecyclo, conpipelined execution in top vs. pipelined execution in bottom. Both use the same hardware components, whose time fs listed in Figure 62. In this case we see a fourfold speedup on average time between instructions, from 8 ne down tons. Compare this igure to Figure 6.1, For the laundry, we assumed al tages were equal. le the dryer were lowest, then the dryer stage would set the stage time. The computer pipeline stage times are limited by the slowest resource, either the ALU operation or the memory access. We assume the write tothe register file occurs in the fist half ofthe clock cycle and the red from the register le occurs in the second half. We use this assumption throughout this chapter,3 These events ave called hasards, which ave of BY pes. Structural Hazards Structural hazard arises Uf the hardware can't support the combination of instructions that we Want to execute inthe same code ycle. Suppose thar we hada single wer ory instead of two memories. Tf the pipeline in Fig: 6-3) had a fourth eustruction, we would see that SS in 1 clock cycle that the first cnstruction & accessing data from memory while the fourth (struction is Feeching om instruction from that same. memory. Wrehout wo memorces , our pipeline could have a Atructural harard. Contvol Haravds Control hazard arises from the need to make a decision based on the results of one instruction while others ore executing The decision task in a computer is the branch instruction. Theye ave 3 solutions +o this control harard : 1) To tnvoke a pipetine stall, micknamed as bubble. That &, cf the bramch-facds the mext tnstruction is stalled extra ons clock cycle before starting. 2) Ts predict dy narccally each branch token or untaken keeping the past history. When the guess & Wrong, the pipe dime control must ensure that the enstruction following the wnongly guessed branch have wo effect amd must vectart the pipe Ane. from the proper brimch addvess. 3) To mate delayed deciston on the branch. The delayed branch aluiays executes st 4the mext sequential custruction, with the byamch taking place after that one onstruction delay . Data Hazards Data harvard arises tf om Unstruction depends on he xesults of a previous instyuction seill mw he pipeline. Suppose we have Zadd tostruction followed by a Subtyack instruction. The add instruction doesn't write tes vesule until the fifth stage, meaning that we vould have to add thee bubles to the pipeline The solution to thio problem is getting the wissing (tem early frow the internal vesources instead of wating for the add instruction to complete. This is called forwarding oy by passing. A pipe lined Datapath A five -stage pipeline for the single - ycle datapath is shou tm Fig. 6-10. This means that up 0 five castru- ctions will be in execution ducting any single clock eycle- Thus we wust sepavate the datapath into 5 stages : 4) IF : Iwstruction Fetch 2) ED + Instruction Decode amd register file read 3 EX: Execution ov addyess calwlation MEM: Data memory access 5) WB: Wyte Back “there ave ‘tuo exceptions to the eft -ts- xeght Lhw of instructions ythe write back tage, which places the wesult back into the register file jn the middle of theFIGURE 6.10 The singlo-yelo datapath from Chapter (teller to Figure 6.27 on page 860), Esch sep of he instruction rich nd cra em log. The ony exception arte upc ot he Pere ane ee Seema Sea eal aor be taney ean eee ‘ner fle (Normally we use clans fr contol, but theese sh 1. I: Instruction fetch. 2. ID: Instruction decode and register file read 3. EX: Execution or address calculation 4. MEM: Data memory access 5. WB: Write back Ie O8H clothes get cleaner, drier, and more organized! they move through the line, and they never move backwards. ‘There are, however, two exceptions to ths left-to-right flow of instructions: ‘= The write-back stage, which places the result back into the register file in the middle of the datapath | See Prograr execut order (ininst w ‘exch portion sponding fo fetch stage, 1 ‘on Tomaints datapath . 2) The selection of the next value of the Pe; that is choosing between the incremented PC and the bramch addyess from the MEM stage. Data Flousng trom wright to Jett does not affect the current instructions , only Jatey instructions in the pipeline are influenced by these reverse dota movements: Fig. G.N shows the execution of the cnstru~ ctions in Fig 6-3 by displaying theiy private dataparhs on a common timeline - Fiq.6-12 shows the pipe fined datapath with pipeline veqiseers highlighted. ll insbructdons advance ducing each clock cycle from one pipe Line +e ister to the mext. The pipeline register in between +wo stages TF UID is called IF/ID. Theve is no pipeline veqister ok the end F4the rite ~back stage. We Vill now see what values ave written into a pipeline vegister commecting two stages. 1 Imstruction read from memory using the addvess EF/EDlin PC, the Uncvemented PC (ik) Pc+y). This P-%29 | is vovitten into Pe to be veady for the next clockeyele. 2. Sign- extended C32 bits) 16-bit crmomediote 1D/ex feeld from the instruction of the IF/ID vegister, preg [ ~vegister numbers to read the two registers 3. For load instruction 5 the content of register 1 exnerl added using the ALU to the sigu-extended immediate from ID/EX pipetine veqister ond the sum is placed on EX/MEM pipeline sagister.way the to right laundry ‘uctions: ister file ae cc1 } coe order (in instvetions) wee.ronse, [ite ay ‘w $2, 200460) sresution, Siar to Figures 67 through 69, this gure roe ction has its own datapath, and shades ponding corns 10 we Ue thse figure, cach ge labeled by the physiol eee ‘stag, corre. Menage: ane Remiensot the datapath in Figure 610M xpress tiation see ane instruction oe Tomah and for the eps fie and sign eter m te insracon eee eee stage (ID), and 50 reir och eee ae hs syed datapath teak the rgir de mo tee er registers ren during Fall ree rio) and esters writen during write back (WThis den see roprecnees by drawing the unshaded left ihe clck hs WB age, when tot being read As Iatore, we asume Re vepece me en a first haf of ‘te clock cycle and the register les read ding the second hl '& The selection of the next value of the PC, choosing between the incre: mented PC and the branch address from the MEM stage ats flowing from right to let does not affect the current instruction; only later instructions in the pipeline are influenced by these reverse date aon, ments. Note that the first right-to-left arrow can lead to data hazards and the second leads to control hazards. Ore vay to show what happens in pipelined execution is to pretend that Each instruction has its own datapath, and then to place these datapaths ona Siructions in Figure 6.3 by displaying their private datapaths on a common tuneline: We use a stylized version of the datapath in Figure 6.10 to show the relationships in Figure 6.11 Figure 6.11 seems to suggest that thre instructions need three datapaths. In Chapter 5, we added registers to hold data so that portions ofthe datapath