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  • Operator

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    The document describes different types of operators in Verilog including bitwise, logical, reduction, arithmetic, relational, shift, concatenation, replication, and conditional operators. It provides examples of common operators like & for bitwise AND, || for logical OR, + for addition, > for greater than, and ?: for conditional operations.

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    The document describes different types of operators in Verilog including bitwise, logical, reduction, arithmetic, relational, shift, concatenation, replication, and conditional operators. It provides examples of common operators like & for bitwise AND, || for logical OR, + for addition, > for greater than, and ?: for conditional operations.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    14 views2 pages

    Operator

    Uploaded by

    vineeth_vs_4
    The document describes different types of operators in Verilog including bitwise, logical, reduction, arithmetic, relational, shift, concatenation, replication, and conditional operators. It provides examples of common operators like & for bitwise AND, || for logical OR, + for addition, > for greater than, and ?: for conditional operations.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    of 2

    Operators

    Note: these operators are NOT shown in order of precedence.

    Operator type Operator symbols Operation performed


    ~ 1's complement
    & Bitwise AND
    Bitwise | Bitwise OR
    ^ Bitwise XOR
    ~^ or ^~ Bitwise XNOR
    ! NOT
    Logical && AND
    || OR
    & Reduction AND
    ~& Reduction NAND
    | Reduction OR
    Reduction
    ~| Reduction NOR
    ^ Reduction XOR
    ~^ or ^~ Reduction XNOR
    + Addition
    - Subtraction
    - 2's complement
    Arithmetic
    * Multiplication
    / Division
    ** exponent (*Verilog-2001)
    > Greater than
    < Less than
    >= Greater than or equal to
    <= Less than or equal to
    Relational == logical equality (bit-value 1'bX is removed from comparison)
    Logical inequality (bit-value 1'bX is removed from
    !=
    comparison)
    === 4-state logical equality (bit-value 1'bX is taken as literal)
    !== 4-state Logical inequality (bit-value 1'bX is taken as literal)
    >> Logical Right shift
    << Logical Left shift
    Shift
    >>> Arithmetic Right shift (*Verilog-2001)
    <<< Arithmetic Left shift (*Verilog-2001)
    Concatenation { , } Concatenation
    Replication {n{m}} Replicate value m for n times
    Conditional ?: Conditional

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