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Chapter 3 Boolean Algebra and Logic Gates: Algebraic Properties
Chapter 3 Boolean Algebra and Logic Gates: Algebraic Properties
Algebraic Properties
✩ The binary operations are defined as the logical AND () and OR (+).
For convenience, a unary operation NOT (complement) is also included
when we define the basic operations.
✩ The Huntington postulates can be shown valid (read pp. 66-68).
✩ Unless otherwise noted, we will use the term Boolean algebra for 2-
valued Boolean algebra.
Theorem 5 (Associativity)
(a) x + (y + z ) = (x + y ) + z ; (b) x(yz ) = (xy )z .
(x1 + x2 + + x
0
n) =
0
x1 x2
0
x
0
n
(x1x2 x n) =
0 0
x1 + x2
0
+ + x
0
n
Boolean Functions
A boolean function is an algebraic expression formed with boolean variables, the
operators OR, AND, and NOT, parentheses, and an equal sign.
0 0
F1 = xy + xy z + x yz
0
Row number x y z F1 F1
0 0 0 0 0 1
1 0 0 1 0 1
2 0 1 0 0 1
3 0 1 1 1 0
4 1 0 0 0 1
5 1 0 1 1 0
6 1 1 0 1 0
7 1 1 1 1 0
2
☞ A literal is a variable or its complement in a boolean expression, e.g., F1 has
8 literals, 1 OR term (sum term), and 3 AND terms (product terms).
☞ The complement of any function F is F , which can be obtained by De Mor- 0
0 0 0 0 0 0 0 0 0 0
F1 = (xy + xy z + x yz ) = (x + y )(x + y + z )(x + y + z )
2
x y z x y z
F
F
(a) AND−OR expression (b) OR−AND expression
Algebraic Manipulation
☞ Minimization of the number of literals and the number of terms usually re-
sults in a simpler circuit (less expensive).
☞ The number of literals can be minimized by algebraic manipulation. Unfor-
tunately, there are no specific rules to follow that will guarantee the optimal
result.
☞ CAD tools for logic minimization are commonly used today.
① x + x0 y = x +y
② x(x
0
+ y) = xy
Example 3
0 0 0 0
xy + xy z + x yz = x(y + y z ) + x yz
0
= x(y + z ) + x yz
0
= xy + xz + x yz
0
= y (x + x z ) + xz
= y (x + z ) + xz
= xy + xz + yz
Canonical Forms
2 0 1 0 0
x yz
0
m2 x +y +z
0
M2
3 0 1 1 x yz
0
m3 x +y +z
0 0
M3
4 1 0 0 xy z
0 0
m4 x
0
+y+z M4
5 1 0 1 xy z
0
m5 x
0
+y+z 0
M5
0 0 0
6 1 1 0 xyz m6 x +y +z M6
7 1 1 1 xyz m7 x
0
+y +z
0 0
M7
Example 4
Consider the two functions F2 and F1 as shown in the following table.
0 0
x y z F2 F2 F1 F1
0 0 0 0 0 1 0 1
1 0 0 1 1 0 0 1
2 0 1 0 0 1 0 1
3 0 1 1 0 1 1 0
4 1 0 0 1 0 0 1
5 1 0 1 0 1 1 0
6 1 1 0 0 1 1 0
7 1 1 1 1 0 1 0
Sum-of-minterms:
F2 =
0
x y z
0
+ xy
0
z
0
+ xyz = m1 + m4 + m7 X(1 4 7) X
; ;
F1 =
0
x yz + xy
0
z
0
+ xyz + xyz = m3 + m5 + +m6 (3 5 6 7)
m7 ; ; ;
Product-of-maxterms:
0 0 0 0 0 0 0
= (x + y + z )(x + y + z )(x + y + z )(x + y + z )(x + y + z )
Y(0 2 3 5 6)
F2
= M0 M2 M3 M5 M6 ; ; ; ;
0 0 0
= (x + y + z )(x + y + z )(x + y + z )(x + y + z )
Y(0 1 2 4)
F1
= M0 M1 M2 M4 ; ; ;
Exercise 4
Convert F = x y 0 0
+ xz to its canonical (som & pom) forms. 2
Standard Forms
☞ Standard forms:
✩ Sum-of-products (sop)
✩ Product-of-sums (pos)
☞ Product terms (or implicants) are the AND terms, which can have fewer lit-
erals than the minterms.
☞ Sum terms are the OR terms, which can have fewer literals than the max-
terms.
☞ Standard forms are not unique!
☞ Standard forms can be derived from canonical forms by combining terms that
differ in one variable, i.e., terms with distance 1.
☞ Each product term in the reduced sop form (i.e., no more reduction is possi-
ble) is called a prime implicant (PI).
✏ Each prime implicant represents 1 or more 1-minterms.
✏ Each 1-minterm can be included in several prime implicants.
✏ If there is a 1-minterm included in only 1 prime implicant, then the prime
implicant is an essential prime implicant (EPI).
☞ Each sum term in the reduced pos form is called a prime implicate.
Example 5
0 0 0
(a) F1 = xy + xy z + x yz is in sop form, and F1 = (x0 + y 0 )(x0 + y + z 0 )(x + y 0 + z 0 )
is in pos form.
(b) Consider the boolean function F = (wx + yz )(w x
0 0
+ 0
y z
0
) in nonstandard
form.
✯ Sop form: F = 0
w x yz
0
+ wxy 0 z 0 .
(b) F1 = xy + xz + yz = xy + (x + y )z = x(y + z ) + yz = xz + y (x + z ) 2
n
☞ There are 22 different boolean functions for n binary variables.
☞ There are 16 different boolean functions if n = 2.
☞ There are 2 functions that generate constants, i.e., the Zero and One functions.
☞ There are 4 functions of one variable which indicate Complement and Trans-
fer operations.
☞ There are 10 functions that define 8 specific binary operations: AND, Inhibi-
tion, XOR (exclusive-OR), OR, NOR, Equivalence, Implication and NAND.
☞ Apart from AND, OR, and NOT (complement), the following functions also
are frequently used: NAND, NOR, XOR, XNOR (exclusive-NOR, or equiv-
alence), & Transfer.
x i y i c i c +1 i s i
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
We first derive expressions for the two output functions that contain a minimum
number of operators.
0 0 0
i
c +1 = i i i + xiyi ci + xi yici + xiyi ci
x y c
0 0
= x y i i + ci (xiyi + xiyi )
= x y i i + ci (xi y i)
0 0 0 0 0 0
si = i i i + xiyi ci + xi yici + xiyi ci
x y c
0 0 0 0 0
= (xi yi + xi yi )ci + (xi yi + xi yi )ci
= (xi y i) ci
Note that the carry function ci+1 could be reduced to xiyi + ci (xi + yi ).
i
c +1 = i i + ci (xi + yi )
x y
0 0 0
= ((xiyi ) (ci (xi + yi )) )
0 0
= ((xi yi ) (xi + yi ))
The gate-level implementations for the full adder are shown in Fig. 2. 2
x y
i i
2.4 4.2
c i to c i+1 4.8 ns
c 2.4 2.4 c
i+1 i c to s 4.2 ns
i i
4.2 x ,y to c 9.0 ns
i i i+1
x ,y to si 8.4 ns
i i
si
x y
i i
1.4 2.4
c 1.4 1.4 c
i+1 i
1.4
c i to s i 3.8 ns
xi
yi
c i to c i+1 3.2 ns
c
i
1.4 1.4 1.4 1.8 1.8 1.8 1.8 c i to si 5.0 ns
x i , yi to c 3.2 ns
i+1
1.8 2.2 x i , yi to si 5.0 ns
c i+1 si
(a) Design with multiple−input gates (b) Input−output delays
for the design in (a)
xi
yi
c
i c i to c i+1 3.4 ns
c i to si 4.4 ns
2.0 2.0
2.4
x i , y to ci+1 3.4 ns
i
1.4 x i , y to si 4.4 ns
c i+1 i
si
(a) Design with multiple−operator gates (b) Input−output delays
for the design in (a)
Figure 3: Full adder design using multiple-input and multiple-operator gates [Gajski].
Gate Implementations
+5V
Vi (S closed) ) Vo = 0V
= 5V
Vo
S Vi = 0V (S open) ) Vo = 5V
(Vi )
A A
B .. OR 0 1 A B Y V(1)
Y
N 0 0 1 0 0 0 t
V(0)
1 1 1 0 1 1
Y = A+B ++N B
1 0 1
A
Y 1 1 1 t
B Y
V
Figure 5: OR gate.
A Y
A Y
0 1
Y = A 0
1 0
A
A XOR 0 1 A B Y V(1)
Y
B 0 0 1 0 0 0 t
V(0)
1 1 0 0 1 1
Y = AB B
1 0 1
1 1 0 t
Y
A A B Y A A B Y
Y Y
B 0 0 1 B 0 0 1
0 1 0 0 1 1
Y = (A + B )0 Y = (AB )0
1 0 0 1 0 1
1 1 0 1 1 0
Figure 6: (a) AND gate; (b) NOT gate (Inverter); (c) XOR gate; (d) NOR and NAND gates.
4.0
3.5
3.0
Ouput voltage VO
2.5
2.0
1.5
1.0
0.5
VOH (2.4)
High noise
margin VIH (2.0)
✯ Fan-out (standard load): the number of gates that each gate can drive, while
providing voltage levels in the guaranteed range.
✯ The fan-out depends on the amount of current a gate can source or sink while
driving other gates.
IIH IIL
IOH IOL
IIH IIL
IIH IIL
☞ The average power dissipation is the product of average current and power
supply voltage (P = I V ).
✏ In standard CMOS technology, the power dissipation increases linearly
with respect to the input transition rate.
✏ Heat removal is the major issue for high power dissipation.
☞ Rise time: delay for a signal to switch from 10% to 90% of its nominal value.
☞ Fall time: delay for a signal to switch from 90% to 10% of its nominal value.
✏ Rise time and fall time may not be equal.
☞ tP HL (tP LH ): delay for the output signal to reach 50% of its nominal value
on the H-to-L (L-to-H) transition after the input signal reached 50% of its
nominal value.
☞ Propagation delay: tP = (tP HL + tP LH )=2 .
Rise Fall
time time
90%
Input
50%
10%
90%
Output
50%
10%
tPHL tPLH
Exercise 6
What are the popular digital logic families commonly used today? 2