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Blocks
MEM ORY
INPUT-OUTPUT
CONTROL
DATAPATH
Arithmetic unit
- Bit-sliced datapath (adder , multiplier,
shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
Bit 3
Data-Out
Multiplexer
Bit 2
Data-In
Register
Adder
Shifter
Bit 1
Bit 0
Sum
Sum
S = A B Ci
A0 B0 A1 B1 A2 B2 A3 B3
S0 S1 S2 S3
Co B
28 Transistors
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
Inversion Property
A B A B
Ci FA Co Ci FA Co
S S
S A B C i = S A B Ci
C o A B C i = Co A B Ci
A1 B1 A3 B3
A0 B0 A2 B2
S0 S2
S1 S3
VDD VDD A
A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A
24 transistors
Ci
B P
P
P S
A A Ci Ci
Co
VDD
P P
B
V DD
A
P P
A
B
A
B
C A
C
A
VD D
VDD
VDD
Ci1 B0
A0
A0 B0 Ci0 A0
A0 B0 B0
Ci0
S0
Ci0
Carry Path
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
NP-CMOS Adder
Co1
S1
A1
B1
S0
A0
B0
Ci0
P0 P1 P2 P3 P4
Ci,0
G0 G1 G2 G3 G4
N
i
tp = 0.69 Ci R j
i = 1 j = 1
25 400
20 300
Speed
Area
15 200
10 100
P0 G1 P0 G1 P2 G2 P3 G3
P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA
Multiplexer
Co,3
P0 P1 P2 P3 BP
Ci,0 Co,3
G0 G1 G2 G3
BP
tp
ripple adder
bypass adder
4..8
N
Setup
P,G
Carry Vector
Sum Generation
(1)
ripple adder
40.0
30.0
tp
linear select
20.0
0.0
0.0 20.0 40.0 60.0
N
A0 ,B 0 A1 ,B 1 AN-1 ,BN-1
...
Ci,0 P0 Ci,1 P1
Ci,N-1 PN-1
...
G3
G2
G1
G0
Ci,0
Co,3
P0
P1
P2
P3
A0 F
A1 A2 A3 A4 A5 A6 A7
A0
tp N
A1
A2
A3
F
A4
A5
A6 tp log2(N)
A7
Co,3
(G2,P2 ) Co,5
(G3,P3 )
(G4,P4 ) Co,6
(G5,P5 )
(G6,P6 ) Co,7
(G7,P7 )
tadd log2(N)
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
The Binary Multiplication
M+ N– 1
Z ·· Y
X Zk 2
k
= =
k=0
M – 1 N – 1
i j
= Xi 2 Yj 2
i=0 j = 0
M – 1 N – 1
i + j
=
Xi Yj 2
i =0 j= 0
with
M –1
i
X =
Xi 2
i=0
N– 1
j
Y =
Y j2
j= 0
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
The Binary Multiplication
1 0 1 0 1 0
1 0 1 1
AND operation
1 0 1 0 1 0
1 0 1 0 1 0 Partial Products
0 0 0 0 0 0
+ 1 0 1 0 1 0
1 1 1 0 0 1 1 1 0
Z0
X3 X2 X1 X0 Y1
HA FA FA HA
X3 X2 X1 X0 Y2 Z1
FA FA FA HA
X3 X2 X1 X0 Y3 Z2
FA FA FA HA
Z7 Z6 Z5 Z4 Z3
HA FA FA HA
FA FA FA HA Critical Path 1
Critical Path 2
Critical Path 1 & 2
FA FA FA HA
HA HA HA HA
HA FA FA FA
HA FA FA FA
HA FA FA HA
A A P S
P
Ci
A
B B P
VDD
V DD
P A
P Co
Ci Ci
Ci
A
Y0
Y1 HA Multiplier Cell
C S C S C S C S
Z0
FA Multiplier Cell
Y2
C S C S C S C S
Z1 Vector Merging Cell
Y3
C S C S C S C S X and Y signals are broadcasted
Z2 through the complete array.
( )
C C C C
S S S S
Z7 Z6 Z5 Z4 Z3
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
Wallace-Tree Multiplier
y0 y1
y2
y0 y1 y2 y3 y4 y5
Ci-1
FA
y3 FA FA
Ci Ci Ci-1
Ci-1
FA Ci Ci-1
y4
FA
Ci Ci-1 Ci Ci-1
FA
y5
Ci FA
FA
C S
C S
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
Multipliers —Summary
• Optimization Goals Different Vs Binary Adder
Area (mm2 )
static
t p (nsec)
40.0
select
bypass
0.2 mirror
look-ahead
20.0
manchester
0.0 0.0
0 10 20
N 0 10 20
N
GND
Well
VDD
Well
GND
GND VDD GND
Approach I — Approach II —
Signal and power lines parallel Signal and power lines perpendicular
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
Layout of Bit-sliced Datapaths