library ieee;

use ieee.std_logic_1164.all;
entity tff_bd is
port(t,clk: in std_logic;
q,qb: out std_logic);
end tff_bd;
architecture tff of tff_bd is
begin
process(clk)
variable temp1:std_logic :='0';
variable temp2:std_logic;
begin
if rising_edge(clk) then
case t is
when'0'=> temp1:=temp1;
when'1'=> temp1:= not temp1;
when others=> null;
end case;

q<=temp1;
temp2:=not temp1;
qb<= temp2;
end if;
end process;

verilog

module tff_bd(t,clk,q,qb);
input t,clk;
output q,qb;
reg q,qb;
initial
begin
q= 1'b0;
end
always @(posedge clk)
begin
case (t)
1'b0: q=q;
1'b1: q=~q;
endcase
qb=~q;
end
endmodule