ECE 366: Computer Architecture Lecture Notes # 4

Shantanu Dutt
Department of Electrical and Computer Engineering University of Illinois, Chicago Phone: (312) 355-1314 e-mail: dutt@ece.uic.edu URL: http://www.ece.uic.edu/~dutt

Basic Components and Connections in the Datapath

Shantanu Dutt

UIC

I_0

I_1

I_(2^n) -1

addr n

sel

2^n:1 Mux

enb n:2^n DCD

o/p

sel0

sel1

sel_(2^n)-1

(a) 2^n:1 Mux: sel=j ==> o/p = I_j

(b) n:2^n DCD: addr=j & enb=1 ==> selj=1 & seli=0, i != j. enb=0 ==> selj=0, for all j

I enb o/p enb0

I_0 enb1

I _1 enb2

I _2 enb3

I _3

Bus (1-bit)

(c) Tri-state buffer: (d) Bus connection via tri-state buffers: exactly one enbj=1 ==> Bus = I_j; enb=1 ==> o/p=I; enbj=0, for all j, ==> Bus = Z enb=0 ==> o/p=Z (high impedance, not connected to any signal)

CLK D

CLK

write_ff CLK

(a) +ve edge-trigg. D-FF

(b) Timing diagram of Q triggering due to D and CLK

(c) D-FF with write control

D0

D1

D2

D3

write_reg CLK Q0 Q1 Q2 Q3

(d) 4-bit register with write control; the o/p is always available, the input is loaded only when CLK +ve edge arrives AND write_reg=1

Write Bus
01^r0write 01^r1write 01^r2write

8
01^r3write 01^r4write 01^r5write 01^r6write 01^r7write

r0
02 02

r1
02

r2
02

r3
02

r4
02

r5
02

r6
02

r7

asel 8 bsel

8:1 MUX (8-bit) Read Bus A

8:1 MUX (8-bit) Read Bus B

Register File Bus Conections Using Multiplexers

r0write r1write 01^r0write

Write Bus
01^r1write 01^r2write

8
01^r3write 01^r4write 01^r5write 01^r6write 01^r7write

3:8 writesel DCD

r7wrute 02 r0reada r1reada

r0
02

r1
02

r2
02

r3
02

r4
02

r5
02

r6
02

r7

3
asel

3:8 DCD

Tristate Logic
r7reada r0readb r1readB

r0reada

r1reada

r2reada

r3reada

r4reada

r5reada

r6reada

r7reada

8 Read Bus A

r0readb

r1readb

r2readb

r3readb

r4readb

r5readb

r6readb

r7readb

3
bsel

3:8 DCD
r2readB

8 Read Bus B

Register File Bus Conections Using Tri-State Logic and Decoders