SIC Programming Example (Fig 1.

2a)


SIC Programming Example (Fig 1.3a)



Data movement
LDA STA LDCH STCH . . . RESW WORD BYTE RESB FIVE ALPHA CHARZ C1 load 5 into A store in ALPHA load Z into A store in C1

Arithmetic operations: BETA = ALPHA+INCR-1

LDA ADD SUB STA LDA ADD SUB STA ... WORD RESW RESW RESW RESW RESW ALPHA INCR ONE BETA GAMMA INCR ONE DELTA 1 1 1 1 1 1 one-word constant one-word variables

ALPHA FIVE CHARZ C1

1 5 CZ 1

reserve one word space one word holding 5 one-byte constant one-byte variable

ONE ALPHA BETA GAMMA DELTA INCR

SIC Programming Example (Fig 1.4a)



SIC Programming Example (Fig 1.5a)

ADDLP LDA STA LDX LDA ADD STA LDA ADD STA COMP JLT ... ... RESW RESW RESW RESW WORD WORD WORD ZERO INDEX INDEX ALPHA,X BETA,X GAMMA,X INDEX THREE INDEX K300 ADDLP 1 100 100 100 0 3 300 initialize index value to 0 load index value to reg X load word from ALPHA into reg A store the result in a word in GAMMA add 3 to index value compare new index value to 300 loop if less than 300

Looping and indexing: copy one string to another

ZERO STR1,X STR2,X ELEVEN MOVECH initialize index register to 0 load char from STR1 to reg A add 1 to index, compare to 11 loop if less than

LDX MOVECH LDCH STCH TIX JLT . . . STR1 BYTE STR2 RESB ZERO WORD ELEVEN WORD

CTEST STRING 11 0 11

INDEX ALPHA BETA GAMMA ZERO THREE K300

2

array variables100 words each one-word constants

SIC Programming Example (Fig 1.6)



SIC/XE Machine Architecture (5/11)



Input and output

INDEV INLOOP INDEV DATA OUTDEV OUTLP DATA OUTDEV XF1 X05 1 test input device loop until device is ready read one byte into register A

Base Relative Addressing Mode

n i opcode x b p e 1 0 disp

INLOOP TD JEQ RD STCH . . OUTLP TD JEQ LDCH WD . . INDEV BYTE OUTDEV BYTE DATA RESB

b=1, p=0, TA=(B)+disp

(0edisp e4095)

test output device loop until device is ready write one byte to output device

Program-Counter Relative Addressing Mode

n i x b p e opcode 0 1 disp

input device number output device number

4

b=0, p=1, TA=(PC)+disp

(-2048edisp e2047)
5

SIC/XE Machine Architecture (6/11)



SIC/XE Machine Architecture (7/11)



Direct Addressing Mode

n i opcode x b p e 0 0 disp

Immediate Addressing Mode

n i opcode x b p e disp 0 1 0

b=0, p=0, TA=disp

(0edisp e4095)


n=0, i=1, x=0, operand=disp

Indirect Addressing Mode

n i x b p e

n i x b p e opcode 1 0 0 disp opcode

1 0 0

disp

b=0, p=0, TA=(X)+disp (with index addressing mode)

6

n=1, i=0, x=0, TA=(disp)

7

SIC/XE Machine Architecture (8/11)



SIC/XE Machine Architecture (9/11)



Addressing Modes Summary (p.499)

Assembler decides which format to use

Simple Addressing Mode

n i opcode 0 0 x b p e disp

i=0, n=0, TA=bpe+disp (SIC standard) opcode+n+i = SIC standard opcode (8-bit)
n i x b p e opcode 1 1 disp

i=1, n=1, TA=disp (SIC/XE standard)

SIC/XE Machine Architecture (10/11)

Example Instruction Format (PC) + disp (B) + disp + (X) ((PC) + disp) disp b/p/e + disp addr

SIC/XE Machine Architecture (11/11)



Instruction set:
 

load and store the new registers: LDB, STB, etc. Floating-point arithmetic operations
ADDF, SUBF, MULF, DIVF

 

Register move: RMO Register-to-register arithmetic operations

ADDR, SUBR, MULR, DIVR




Supervisor call: SVC I/O channels to perform I/O while CPU is executing other instructions: SIO, TIO, HIO

Input and output:



10

11

SIC/XE Programming Example

SIC version LDA STA LDCH STCH . . . RESW WORD BYTE RESB FIVE ALPHA CHARZ C1

(Fig 1.2b)

SIC/XE Programming Example

LDS LDA ADDR SUB STA LDA ADDR SUB STA ... ... RESW RESW RESW RESW RESW INCR ALPHA S,A #1 BETA GAMMA S,A #1 DELTA 1 1 1 1 1

(Fig 1.3b)

ALPHA FIVE CHARZ C1

1 5 CZ 1

SIC/XE version LDA #5 STA ALPHA LDCH #90 STCH C1 . . . ALPHA RESW 1 C1 RESB 1

BETA=ALPHA+INCR-1

DELTA=GAMMA+INCR-1

ALPHA BETA GAMMA DELTA INCR

one-word variables

12

13

SIC/XE Programming Example



(Fig 1.4b)

SIC/XE Programming Example

LDS LDT LDX LDA ADD STA ADDR COMPR JLT ... ... RESW RESW RESW #3 #300 #0 ALPHA,X BETA,X GAMMA,X S,X X,T ADDLP 100 100 100

(Fig 1.5b)

Looping and indexing: copy one string to another

#11 #0 STR1,X STR2,X T MOVECH initialize register T to 11 initialize index register to 0 load char from STR1 to reg A store char into STR2 add 1 to index, compare to 11 loop if less than 11 ADDLP

LDT LDX MOVECH LDCH STCH TIXR JLT . . . STR1 BYTE STR2 RESB

load from ALPHA to reg A store in a word in GAMMA add 3 to index value compare to 300 loop if less than 300 array variables100 words each

CTEST STRING 11

ALPHA BETA GAMMA

14

15

SIC/XE Programming Example

(Fig 1.7b)

16