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Đề thi kỹ thuật Vi xử lý ĐT 1,2,3,4,5,6,7,8 - K48 Thời gian: 90 phút
Đề thi kỹ thuật Vi xử lý ĐT 1,2,3,4,5,6,7,8 - K48 Thời gian: 90 phút
T 1,2,3,4,5,6,7,8 K48
Thi gian : 90 pht
Cu 1 ( 3 im )
Trnh by cc khi nim sau :
Qun l b nh theo ch thc
X l pipelining
Little endian b big endian
Ch a ch gin tip qua thanh ghi
Vo ra theo kiu hi vng
DSP
Cu 2 ( 2 im )
Mt h vi x l bao gm vxl 8086 ghp ni vi 48 KB EPROM s dng EPROM 2764
(8K*8)
v 128 KB SRAM s dng cc IC SRAM ging ht nhau vi 8 bit d liu . Gii m a
ch cho EPROM c thc hin bi 74LS139 v gii m a ch cho SRAM c thc
hin bi 74LS138
Cho gi tr hin ti ca cc thanh ghi : CS = 0600H , IP = 2000H , DS = 1000H ,BX =
8000H
Gi thit rng chng trnh v d liu c lu trong RAM v ln tip theo s c thc
hin l lnh MOV AL,[BX+1] , lnh ny c lu tr ti cc byte nh u tin ca IC
th 2 thuc bank thp .Khi thc hin lnh MOV ny , byte nh u tin ca IC th 4
thuc bank cao s c truy cp
Hy v s ghp ni 8086 vi b nh EPROM v SRAM trong h vxl c miu t
trn
Cu 3 . (2 im)
a.Hy vit chng trnh assembly cho 8086 thc hin
1.Nhp s N ( N<9 , nguyn dng) t bn phm
2.Tnh S = 1^2 + .. + N^2
3. Kim tra tnh chn l ca S
b.Hy ti u chng trnh va vit ( nu c th ) theo kch thc ca chng trnh trong
b nh
II
Cu1:
Trnh by cc khi nim:
- ghp ni bng ngt
- Vi iu khin
- DMA
- Hyperthearding v dual core
- Lm ti Dram
Cu 2:
Mt h VXL bao gm VXL 8086 ghp ni voi 24KB EPROM s dng 2732 (4K*8) v
64KB SRAM s dng cc IC SRAM ging ht nhau vi 8 bit d liu. Gii m a ch
cho EPROM c thc hin bi 74LS138 v gii m a ch cho SRAM c thc hin
bi 74LS139.
Cho gi tr hin ti ca cc thanh ghi: CS = 0300H, IP = 1000H, DS = 0BFFH, BX =
000EH
Gi thit rng chng trnh v d liu c lu tr trong RAM v lnh ADD AL, [BX +
3] , lnh ny c lu tr ti cc byte nh u tin ca IC th 2 thuc bank thp. Khi
thc hin lnh ADD ny, byte nh u tin ca IC th 4 thuc bank cao s c truy
cp.
Hy v s ghp ni 8086 vi b nh EPROM v SRAM trong h VXL c miu t
trn
Cu 3:
a). Hy vit chng trnh assembly cho 8086 thc hin
1. Nhp vo 1 s nguyn N (<=9)
2. Nhp N s nguyn (<10) v tnh tng S ca cc s
3. In S ra mn hnh
b).Hy ti u chng trnh va vit ( nu c th ) theo kch thc ca chng trnh trong
b nh
Hng dn gii vi x l
DS = 0BFFH, BX = 000EH
Gi thit rng chng trnh v d liu c lu tr trong RAM v lnh
ADD AL, [BX + 3] , lnh ny c lu tr ti cc byte nh u tin ca IC th 2 thuc
bank thp. Khi thc hin lnh ADD ny, byte nh u tin ca IC th 4 thuc bank cao
s c truy cp.
Hy v s ghp ni 8086 vi b nh EPROM v SRAM trong h VXL c miu t
trn.
Gii :
* ROM :
Do ROM phi cha a ch khi ng ca CPU l : FFFF0 H nn ta chn a ch
kt thc ca ROM l FFFFF H.
M 24KB = 0000 0110 0000 0000 0000 = 06000 H
a ch u = a ch cui Dung lng + 1
= FFFFF 06000 + 1
= FA000 H
- Ta c : 4K = 22 x 210 = 212
a ch thay i : A1 A12
A15A14A1 A12A11
.A1
3
A0
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
101
101
110
110
111
111
101
101
110
110
111
111
0
0
0
0
0
0
1
1
1
1
1
1
a ch ca cc IC :
IC 1 : FA000 H FBFFE H
IC 2 : FC000 H FDFFE H
IC 3 : FE000 H FFFFE H
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
IC 4 : FA001 H FBFFF H
IC 5 : FC001 H FDFFF H
IC 6 : FE001 H FFFFF H
Hnh v :
* RAM :
- a ch ca IC 4 thuc bank cao = DS*16 H + [BX + 3]
= OBFFO H + 0011 H = 0C001 H
a ch cui ca IC 4 l : 0FFFF H
- Do bit A16, A17. A18, A19 = 0 (ko thay i) nn ko th dng bit ny chn IC
LS139
--> mi bank ch c ti a 4 IC. Tng cng cn dng 8 IC
64K : 8 IC = 8K --> loi SRAM l : 8K x 8 bit.
- Ta c : 8K = 23 x 210 = 213
Bit d liu : A1 A13
A15A1
4
A13A12A11
. A1
A0
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00
00
01
01
10
10
11
11
00
00
01
01
10
10
11
0 0 0 .. 0
1 1 1 .. 1
0 0 0 .. 0
1 1 1 .. 1
0 0 0 .. 0
1 1 1 .. 1
0 0 0 .. 0
1 1 1 .. 1
0 0 0 .. 0
1 1 1 ... 1
0 0 0 .. 0
1 1 1 .. 1
0 0 0 .. 0
1 1 1 .. 1
0 0 0 .. 0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0000
11
1 1 1 .. 1
a ch ca cc IC :
IC 1 : 00000 H 03FFE H
IC 2 : 04000 H 07FFE H
IC 3 : 08000 H 0BFFE H
IC 4 : 0C000 H 0FFFE H
IC 5 : 00001 H 03FFF H
IC 6 : 04001 H 07FFF H
IC 7 : 08001 H 0BFFF H
IC 8 : 0C001 H 0FFFF H
Hnh :
;Allright reserve DTBK group ....thank you for viewing this text
.model small
.stack 100h
.data
msg1 db 'nhap so N : $'
msg2 db 13,10,'Tong S la : $'
msg3 db 13,10,'S la le $'
msg4 db 13,10,'S la chan $'
N db ?
;on ny 13,10 l s th t ca CR( carrier return: v u dng ) LF (line feed :
xung dng ) trong bng ASCII
.code
main proc
mov ax,@data
mov ds,ax
mov ah,9 ; ngt 9 ca 21h
lea dx,msg1; ch con tr ti chui msg1
int 21h ; lc ny my s in ra chui msg1
mov ah,1
int 21h
sub al,30h ; i al sang s !! (2)
xor bx,bx ; bx =0
lap:
xor ah,ah
push ax ; ct ax t nh ngn xp
mul al
add bx,ax ; bx = bx + ax
pop ax ; ly li ax t nh ngn xp
dec al
cmp al,0 ; so snh al v 0
jne lap ; nu al ko bng 0 s nhy v lap:
mov ah,9
lea dx,msg2
int 21h ; In chui msg2 ra mn hnh
; nh vy ta thc hin xong vic tnh tng S , S c lu trong thanh ghi BX
; dng hexa . By gi ta s tin hnh chuyn S sang h thp phn v in ra mn
xor ax,ax ; ax = 0
mov ax,bx ; chuyn gi tr S vo ax
push ax ; cat ax vao dinh ngan xep
mov bx,100 ; dung 100 lam so bi chia
mov cx,1 ;
mov dx,0
begin_print:
cmp bx,0
jz end_print ; Nu bx = 0 s nhy n end_print:
cmp cx,0
je calc ; nu cx=0 s nhy n calc
cmp ax,bx ; so snh ax v bx
jb giulai ; nu ax < bx s nhy n gi li
; nhn ny s in ra mn hnh tng s 1 ca kt qu
calc:
mov cx,0
mov dx,0
div bx
push dx
add al,30h
xor dx,dx
mov dl,al
mov ah,2
int 21h
pop dx
mov ax,dx
; nhn ny s thc hin nhim v gim bt bx i 10 ln v bx>ax nn ko chia c