Notes on Intel(R) Pentium(TM) Processor (c) Copyright Microsoft Corp.

1993 This file contains the following information: - Implementation of the .586 and .586P directives - New instructions for the Intel(R) Pentium(TM) processor - Pentium clock cycles for all instructions ============================================================================= .586 and .586P Directives ------------------------The .586 directive enables assembly of non-privileged instructions available for the Pentium processor. The .586P directive enables privileged instructions in addition to the non-privileged instructions for the Pentium. The following example demonstrates implementation of the .586 directive. .model small, C .586 .data ; .586 gives 110100111111y = 0D3Fh ; .586p gives 110110111111y = 0DBFh var1 dw @cpu IF @Cpu AND 0100000y %echo Pentium instructions enabled. ELSE %echo Pentium instructions Not enabled. ENDIF end ============================================================================= New Pentium Instructions -----------------------The new Pentium instructions are extensions to the Intel486 instruction set; for information on instructions for the 8086, 8088, 80286, 80386, and 80486 processors, see Chapter 4, "Processor," in the Microsoft MASM Reference. For additional information on the new Pentium instructions, refer to you Intel documentation. CMPXCHG8B Compare and Exchange 8 Bytes

Compares the 64-bit value in EDX:EAX with a 64-bit value in memory. If they are equal, the 64-bit value in memory is replaced by the value in ECX:EBX. Otherwise, the value in memory is loaded into EDX:EAX. Flags: The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are unaffected. Encoding: 00001111 11000111 mod 001 r/m

Syntax -----CMPXCHG8B mem64

Example ------cmpxchg8b [bx]

Clock Cycles ----------10

----------------------------------------------------------------------------CPUID CPU Identification Syntax: CPUID Provides information to the software about the model of microprocessor on which it is executing. An input value loaded into the EAX register for this instruction indicates what information should be returned by the CPUID instruction. Following execution of the CPUID instruction with zero in EAX, the EAX register contains the highest input value understood by the CPUID instruction. For the Pentium, the value in EAX will be 1. Also included in this output is a vendor identification string contained in EBX, EDX, and ECX. EBX contains the first four characters, EDX the next four, and ECX the last four. For Intel processors, the vendor identification string is "GenuineIntel". Following execution of the CPUID instruction with input value 1 in EAX, EAX[3:0] contains the stepping ID of the microprocessor, EAX[7:4] contains the model (the first model will be indicated by 0001B) and EAX[11:8] contains the family (5 for the Pentium). EAX[31:12], EBX, and ECX are reserved. The Pentium processor sets the feature register, EDX, to 1BFH, indicating which features the Pentium supports. A feature flag set to 1 indicates that the corresponding feature is supported. Flags: No flags affected. Encoding: 00001111 10100010 Syntax -----CPUID Example ------cpuid Clock Cycles ----------14

----------------------------------------------------------------------------MOV Move to/from Control Registers Store or load the Control Registers (CR0, CR2, CR3, CR4) to or from a general purpose register. Flags: The OF, SF, ZF, AF, PF, and CF flags are undefined. Encoding: 00001111 00100010 11 eee reg (Move to Control Register) Syntax -----MOV reg32,controlreg Example ------mov cr0,eax mov cr2,eax mov cr3,eax mov cr4,eax Clock Cycles ----------22 12 21,46 14

Encoding: 00001111 00100000 11 eee reg (Move from Control Register)

Syntax -----MOV controlreg,reg32

Example ------mov eax,cr0

Clock Cycles ----------4

----------------------------------------------------------------------------RDMSR Read from Model-Specific Register The value in ECX specifies one of the 64-bit Model-Specific Registers of the Pentium processor. The content of that Model-Specific Register is copied into EDX:EAX. EDX is loaded with the high-order 32 bits, and EAX is loaded with the low-order 32 bits. Flags: No flags affected. Encoding: 00001111 00110010 Syntax -----RDMSR Example ------rdmsr Clock Cycles ----------20-24

----------------------------------------------------------------------------RDTSC Read from Time Stamp Counter Copies the contents of the Time Stamp Counter (TSC) into EDX EAX. (The Pentium maintains a 64-bit Time Stamp Counter (TSC) that is incremented every clock cycle.) When the Current Privilege Level is 0, the state of the TSD bit in CR4 does not affect the operation of this instruction. When the CPL is equal to 1, 2, or 3, the TSC may be read only if the TSD bit in CR4 is 0. Only a supervisor level program may modify the value of the TSC. Flags: No flags affected. Encoding: 00001111 00110001 Syntax -----RDTSC Example ------rdtsc Clock Cycles ----------6, 11

----------------------------------------------------------------------------RSM Resume from System Management Mode The processor state is restored from the dump created upon entrance to System Management Mode. However, the contents of the model-specific registers are not affected. The processor leaves SMM and returns control to the interrupted application or operating system. If the processor detects any invalid state information, it enters the shutdown state. Flags: All flags are affected. Encoding: 00001111 10101010 Syntax -----RSM Example ------rsm Clock Cycles ----------83

----------------------------------------------------------------------------WRMSR Write to Model-Specific Register The value in ECX specifies one of the 64-bit Model-Specific Registers of the Pentium processor. The content of EDX:EAX is copied to that ModelSpecific Register. The high-order 32 bits are copied from EDX, and the low-order 32 bits are copied from EAX. Flags: No flags affected. Encoding: 00001111 00110000 Syntax -----WRMSR Example ------wrmsr Clock Cycles ----------30-45

============================================================================= Pentium Clock Cycles -------------------The following table contains clock cycles information for all Intel Pentium processor instructions. For more detailed information on clock cycles for these instructions, see your Intel documentation. For more general information on these instructions, see Chapter 4, "Processor," and Chapter 5, "Coprocessor," in the Microsoft MASM Reference. Instruction Syntax -----------------AAA AAD AAM AAS ADC reg,reg ADC mem,reg ADC reg,mem ADD ADD ADD ADD ADD ADD AND AND AND AND AND AND reg,reg mem,reg reg,mem reg,immed mem,immed accum,immed reg,reg mem,reg reg,mem reg,immed mem,immed accum,immed Example ------aaa aad aam aas adc dx,cx adc WORD PTR m16[2],dx adc dx,DWORD PTR m32[2] add add add add add add and and and and and and ax,bx total, cx cx,incr bx,6 pointers[bx][si],6 ax,10 dx,bx bitmask,bx bx,masker dx,0F7h masker,100lb ax,0B6h Clock Cycles -----------3 10 18 3 1 3 2 1 3 2 1 3 1 1 3 2 1 3 1 pm=7 pm=7

ARPL reg,reg ARPL mem,reg

arpl ax,cx arpl selector,dx

BOUND reg16,mem32 BOUND reg32,mem64 BSF BSF BSF BSF BSR BSR BSR BSR reg16,reg16 reg32,reg32 reg16,mem16 reg32,mem32 reg16,reg16 reg32,reg32 reg16,mem16 reg32,mem32

bound di,base-4 bound di,base-4 bsf bsf bsf bsf bsr bsr bsr bsr cx,bx cx,bx ecx,bitmask ecx,bitmask cx,dx cx,dx eax,bitmask eax,bitmask

8 (within bounds); int+32 (out of bounds) 8 (within bounds); int+32 (out of bounds) 6-34 6-42 6-35 6-43 7-39 7-71 7-40 7-72 1 4 4 4 9 7 8 7 13

BSWAP reg32 BT reg16,immed8* BT mem16,immed8* BT reg16,reg16* BT mem16,reg16* * Operands can also be BTC reg16,immed8* BTC mem16,immed8* BTC reg16,reg16* BTC mem16,reg16* * Operands can also be BTR reg16,immed8* BTR mem16,immed8* BTR reg16,reg16* BTR mem16,reg16* * Operands can also be BTS reg16,immed8* BTS mem16,immed8* BTS reg16,reg16* BTS mem16,reg16* * Operands can also be CALL label CALL reg CALL mem32 CALL mem32 CBW CDQ CLC CLD CLI CLTS

bswap ebx bt ax,4 bt [bx],4 bt ax,bx bt [bx],dx 32 bits btc edi,4 btc color[di],4 btc eax,ebx btc [bp+8],si 32 bits btr bx,17 btr [bx],27 btr cx,di btr rotate,cx 32 bits bts ax,4 bts maskit,4 bts bx,ax bts flags[bx],cx 32 bits call call call call call cbw cdq clc cld cli clts upcase distant ax [bx] DWORD PTR [bx]

7 8 7 13 7 8 7 13 1 4 2 2 5 3 2 2 2 7 10

CMC CMP CMP CMP CMP CMP CMP reg,reg mem,reg reg,mem reg,immed mem,immed accum,immed

cmc cmp cmp cmp cmp cmp cmp dl,cl array[si],bl bh,array[si] bx,24 tester,4000 ax,1000

2 1 2 2 1 2 1 5 5 5 5 6 6 10 14 2 3 3 3 1 3 byte=17, word=25, dword=41 11 15 15+2imm8 13-57 1 3, 3, 3, 7, 1 1 1 4

CMPS [segreg:] src, [ES:] dest CMPSB [[segreg:[src,] ES:] dest] CMPSW [[segreg:[src,] ES:] dest] CMPSD [[segreg:[src,] ES:] dest] CMPXCHG mem,reg CMPXCHG reg,reg CMPXCHG8B reg,mem64 CPUID CWD CWDE DAA DAS DEC reg DEC mem DIV reg DIV mem ENTER immed16,0 ENTER immed16,1 ENTER immed16,immed8 F2XM1 FABS FADD [reg,reg] FADD memreal FADDP reg,ST FIADD memint FBLD membcd FBSTP membcd FCHS

cmps source,es:dest cmpsb cmpsw cmpsd cmpxchg string,bl cmpxchg bx,cx cmpxchg8b ax,[bx] cpuid cwd cwde daa das dec ax dec counter div cx div [bx] enter 4,0 enter 0,1 enter 6,4 fm2xi fabs fadd fadd shortreal faddp st(6),st fiadd int16 fbld packbck fbstp bcds[bx] fchs

48-58 148-154 1

FCLEX FNCLEX FCOM FCOMP FCOMPP FICOM memint FICOMP memint FCOS FDECSTP FDIV [reg,reg] FDIV memreal FDIVP reg,ST FIDIV memint FDIVR [reg,reg] FDIVR memreal FDIVRP reg,ST FIDIVR memint FFREE ST(i) FILD memint FINCSTP FINIT FNINIT FIST memint FISTP memint FLD FLD FLD FLD reg mem32real mem64real mem80real

fclex fnclex fcom fcomp fcompp ficom double ficomp darray[di] fcos fdecstp fdiv st(5),st fdiv longreal fdivp st(6),st didiv warray[di] fdivr st(5),st fdivr longreal fdivrp st(6),st didivr warray[di] ffree st(3) fild quads[si] fincstp finit fninit fist doubles[8] fistp longint fld st(3) fld longreal

9+ 9 4, 4, 4, 8, 8, 1 1 1 4 4

18-124 1 39 39 39 42 39 39 39 42 1 3, 1 1 16 12 6 6 1 1 1 3 2 2 5, 5, 5, 5, 5, 7 37, 16-bit pm=32, 32-bit pm=33

FLD1 FLDZ FLDPI FLDL2E FLDL2T FLDLG2 FLDLN2 FLDCW mem16 FLDENV mem

fld1 fldz fldpi fldl2e fldl2t fldlg2 fldln2 fldcw ctrlword fldenv [bp+10]

3 3 3 3 3

FMUL [reg,reg] FMULP reg,ST FIMUL memint

fmul st(5),st fmulp st(6),st fimul warray[di]

3, 1 3, 1 7, 4

FNOP FPATAN FPREM FPREM1 FPTAN FRNDINT FRSTOR mem

fnop fpatan fprem fprem1 fptan frndint frstor [bp-94]

1 17-173 16-64 20-70 17-173 9-20 16-bit rm or vm=75; 32-bit rm or vm=95; pm=70 16-bit rm or vm=127+; 32-bit rm or vm=151+; pm=124+ 16-bit rm or vm=127; 32-bit rm or vm=151; pm=124 20-31 16-126 17-137 70 1 2 1 2 2 3 2+ 2 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 2+ 2+ 2 2 3, 3, 3, 7, 1 1 1 4 rm or vm=50+; rm or vm=48+; pm=49+; pm=50+ rm or vm=50; rm or vm=48; pm=49; pm=50

FSAVE mem

fsave [bp-94]

FNSAVE mem

fnsave [bp-94]

FSCALE FSIN FSINCOS FSQRT FST reg FST memreal FSTP reg FSTP mem32real FSTP mem64real FSTP mem80real FSTCW mem16 FNSTCW mem16 FSTENV mem

fscale fsin fsincos fsqrt fst st fst longs[bx] fstp st(3) fstp longreal

fstcw ctrlword fnstcw ctrlword fstenv [bp-14]

FNSTENV mem

fnstenv [bp-14]

FSTSW mem16 FSTSW AX FNSTSW mem16 FNSTSW AX FSUB [reg,reg] FSUB memreal FSUBP reg,ST FISUB memint

fstsw statword fstsw ax fnstsw statword fnstsw ax fsub st,st(2) fsub longreal fsubp st(6),st fisub double

FSUBR [reg,reg] FSUBR memreal FSUBRP reg,ST FISUBR memint FTST FUCOM [reg] FUCOMP [reg] FUCOMPP FWAIT FXAM FXCH [reg] FXTRACT FYL2X FYL2XP1 HLT IDIV reg IDIV mem IMUL IMUL IMUL IMUL IMUL IMUL IMUL reg mem reg,immed reg,reg,immed reg,mem,immed reg,reg reg,mem

fsubr st,st(2) fsubr longreal fsubrp st(6),st fisubr double ftst fucom st(2) fucomp st(7) fucompp fwait fxam fxchg st(3) fxtract fyl2x fyl2xp1 hlt idiv dl idiv itemp imul imul imul imul imul imul imul dx factor cx,25 dx,ax,18 bx,[si],60 cx,ax dx,[si]

3, 3, 3, 7,

1 1 1 4

4, 1 4, 1 4, 1 4, 1 1-3 21 1 13 22-111 22-103 12 8-bit=22; 16-bit=30; 32-bit=46 11 11 10 10 10 10 10

IN accum,immed in ax,60h 7, pm=4,21*, vm=19 IN accum,DX in ax,dx 7, pm=4,21*, vm=19 (*First protected mode timing: CPL < or = IOPL. Second timing: CPL > IOPL.) INC reg INC mem INS [ES:]dest, DX INSB INSW INSD (*First protected mode inc bx inc vpage ins es:instr,dx insb insw insd timing: CPL < or = IOPL. Second 1 3 9, pm=6,24*, 9, pm=6,24*, 9, pm=6,24*, 9, pm=6,24*, timing: CPL > vm=22 vm=22 vm=22 vm=22 IOPL.)

INT immed8 int 25h 16, pm=31,48* INT 3 int 3 13, pm=27,44* INTO into 13, pm=27,44* (*First protected mode timing is for interrupts to the same privilege level. The second is for interrupts to a higher privilege level.) INVD INVLPG invd invlpg es:entry 15 25

IRET IRETD IRETF IRETDF (* Real or V86 mode.) Jcondition label JCXZ label JECXZ label JMP label JMP JMP JMP JMP JMP LAHF LAR reg,reg LAR reg,mem LDS LES LFS LGS LSS reg,mem reg,mem reg,mem reg,mem reg,mem reg16 mem16 reg32 mem32 mem48

iret iretd iretf iretdf je next jcxz not found jmp jmp jmp jmp jmp jmp jmp lahf lar ax,bx lar cx,selector lds les lfs lgs lss si,fpointer di,fpointer edi,fpointer bx,fpointer bp, fpointer NEAR PTR distant distant ax table[di] eax fpointer[si] FWORD PTR [di]

8*,10, pm=27 10, pm=27

1 6,5 6,5 1 3 2 2 3 2 4 2 8 8 4 4 4 4 4, pm=8 1 3

LEA reg,mem LEAVE LGDT LIDT LLDT LLDT mem48 mem48 reg16 mem16

lea bx,npointer leave lgdt lidt lldt lldt descriptor descriptor ax selector

6 6 9 9 8 8 1 2 2 2 2 5, 7, 7, 7, 7, 8 8 10 6 8 8 8 8

LMSW reg16 LMSW mem16 LOCK LODS [segreg:]src LODSB [[segreg:]src] LODSW [[segreg:]src] LODSD [[segreg:]src] LOOP label LOOPE label LOOPZ label LOOPNE label LOOPNZ label LSL reg,reg LSL reg,mem LTR reg16

lmsw ax lmsw machine lock lods es:source lodsb lodsw lodsd loop wend loope again loopz again loopne for_next loopnz for_next lsl ax,bx lsl cx,seg_lim ltr ax

LTR mem16 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV reg,reg mem,reg reg,mem mem,immed reg,immed mem,accum accum,mem segreg,reg16 segreg,mem16 reg16,segreg mem16,segreg reg32,controlreg

ltr task mov mov mov mov mov mov mov mov mov mov mov mov mov mov mov mov mov bp,sp array[di],bx bx,pointer [bx],15 cx,256 total,ax al,string ds,ax es,psp ax,ds stack_save,ss eax,cr0 eax,cr2 eax,cr3 eax,cr4 cr0,eax edx,dr0

10 1 1 1 1 1 1 1 2, 3 2, 3 1 1 22 12 21, 46 14 4 DR0-DR3,DR6,DR7=11; DR4,DR5=12 DR0-DR3,DR6,DR7=11; DR4,DR5=12 4 4 4 4 3 3 3 3 8,16-bit=11; 32-bit=10 1 3 1 1 3 1 3 2 1 3 1 12, pm=9,26, VM=24 12, pm=9,25 VM=24 13, pm=10,27, VM=24

MOV controlreg,reg32 MOV reg32,debugreg MOV debugreg,reg32 MOVS [ES:]dest, [segreg:]src MOVSB [[ES:]dest, [segreg:]src] MOVSW [[ES:]dest, [segreg:]src] MOVSD [[ES:]dest, [segreg:]src] MOVSX reg,reg MOVSX reg,mem MOVZX reg,reg MOVZX reg,mem MUL reg MUL mem NEG reg NEG mem NOP NOT reg NOT mem OR OR OR OR OR OR reg,reg mem,reg reg,mem reg,immed mem,immed accum,immed

mov dr0,ecx

movs dest,es:source movsb movsw movsd movsx bx,al movsx eax,bsign movzx bx,al movzx eax,bunsign mul bx mul WORD PTR [bx] neg ax neg balance nop not ax not masker or or or or or or ax,dx bits,dx dx,color[di] dx,110110b flag_rec,8 ax,40h

OUT immed8,accum OUT DX,accum OUTS DX,[segreg:]src

out 60h,al out dx,ax outs dx,buffer

OUTSB [DX,[segreg:]src] outsb OUTSW [DX,[segreg:]src] outsw OUTSD [DX,[segreg:]src] outsd POP reg POP mem POP segreg POPA POPAD POPF POPFD PUSH PUSH PUSH PUSH reg mem segreg immed pop cx pop param pop es popa popad popf popfd push push push push dx [di] es 15000

13, pm=10,27, VM=24 13, pm=10,27, VM=24 13, pm=10,27, VM=24 1 3 3 5 5 6, pm=4 6, pm=4 1 2 1 1 5 5 4, pm=3 4, pm=3 1 3 7-24 9-26 8-25 10-27 1 3 7-24 9-26 8-25 10-27 1 3 4 4 1 3 1 3 4 4 1 3 20-24 11+3n, pm=(8,25)+3n* 6, 13n 13+4n, pm=(10,27)+4n* 7, 7+3n 6, 9+3n timing: CPL > IOPL.) 7, 9+4n

PUSHA PUSHAD PUSHF PUSHFD RCL RCL RCL RCL RCL RCL RCR RCR RCR RCR RCR RCR ROL ROL ROL ROL ROL ROL ROR ROR ROR ROR ROR ROR reg,1 mem,1 reg,CL mem,CL reg,immed8 mem,immed8 reg,1 mem,1 reg,CL mem,CL reg,immed8 mem,immed8 reg,1 mem,1 reg,CL mem,CL reg,immed8 mem,immed8 reg,1 mem,1 reg,CL mem,CL reg,immed8 mem,immed8

pusha pushad pushf pushfd rcl rcl rcl rcl rcl rcl rcr rcr rcr rcl rcr rcr rol rol rol rol rol rol ror ror ror ror ror ror dx,1 WORD PTR [si],1 dx,cl masker,cl bx,5 WORD PTR [bp+8],3 bl,1 WORD PTR m32[0],1 bl,cl WORD PTR [bx=di],cl si,9 masker,3 ax,1 bits,1 ax,cl color,cl ax,13 BYTE PTR [bx],10 ax,1 WORD PTR [bx],1 dx,cl color,cl bl,3 bits,6

RDMSR REP INS dest,DX REP MOVS dest,src REP OUTS DX,src REP LODS dest REP STOS dest (*First protected mode REPE CMPS src,dest

rdmsr rep ins dest,dx rep movs dest,source rep outs dx,source rep lods dest rep stos dest timing: CPL < or = IOPL. Second repe cmps src,dest

REPE SCAS dest REPNE CMPS src,dest REPNE SCAS dest RETN RETN immed16 RETF RETF immed16 RSM SAHF SAL SAL SAL SAL SAL SAL SAR SAR SAR SAR SAR SAR SHL SHL SHL SHL SHL SHL SHR SHR SHR SHR SHR SHR SBB SBB SBB SBB SBB SBB reg,1 mem,1 reg,CL mem,CL reg,immed mem,immed reg,1 mem,1 reg,CL mem,CL reg,immed mem,immed reg,1 mem,1 reg,CL mem,CL reg,immed mem,immed reg,1 mem,1 reg,CL mem,CL reg,immed mem,immed accum,immed reg,immed mem,immed reg,reg mem,reg reg,mem

repe scas dest repne cmps src,dest repne scas dest retn retn 8 retf retf 32 rsm sahf sal sal sal sal sal sal sar sar sar sar sar sar shl shl shl shl shl shl shr shr shr shr shr shr sbb sbb sbb sbb sbb sbb bx,1 WORD PTR m32[0],1 ah,cl BYTE PTR [di],cl cx,6 array[bx+di],14 di,1 count,1 bx,cl sign,cl bx,5 sign_count,3 si,1 index,1 di,cl index,cl di,2 unsign,4 dh,1 unsign[di],1 dx,cl WORD PTR m32[2],cl bx,8 mem16,11 ax,320 dx,45 WORD PTR m32[2],40 dx,cx WORD PTR m32[2],dx dx,WORD PTR m32[2]

7, 9+4n 7, 8+4n 7, 9+4n 2 3 4, 23 4, 23 83 2 1 3 4 4 1 3 1 3 4 4 1 3 1 3 4 4 1 3 1 3 4 4 1 3 1 1 3 1 3 2 4 4 4 4 1 2 4 4 4 4

SCAS [ES]dest SCASB SCASW SCASD SETcondition reg8 SETcondition mem8 SGDT mem48 SIDT mem48

scas es:destin scasb scasw scasd setc dh setle flag sgdt descriptor sidt descriptor

SHLD reg16,reg16,immed8 shld ax,dx,10 SHLD reg32,reg32,immed8 SHLD mem16,reg16,immed8 shld bits,cx,5

SHLD SHLD SHLD SHLD SHLD SHRD SHRD SHRD SHRD SHRD SHRD SHRD SHRD

mem32,reg32,immed8 reg16,reg16,CL shld ax,dx,cl reg32,reg32,CL mem16,reg16,CL shld masker,ax,cl mem32,reg32,CL reg16,reg16,immed8 reg32,reg32,immed8 mem16,reg16,immed8 mem32,reg32,immed8 reg16,reg16,CL reg32,reg32,CL mem16,reg16,CL mem32,reg32,CL shrd cx,si,3 shrd [di],dx,5 shrd ax,dx,cl shrd [bx],ax,cl sldt ax sldt selector smsw ax smsw machine stc std sti stor es:dstring stosb stosw stosd str cx str taskreg sub sub sub sub sub sub test test test test test verr verr verw verw wait wbinvd wrmsr xadd dl,al ax,bx array[di],bi al,[bx] bl,7 total,4000 ax,32000 dx,bx flags,dx cx,30h masker,1 ax,90h ax selector cx selector

4 5 4 4 4 5 2 2 4 4 2 2 7 3 3 3 3 2 2 1 3 2 1 3 1 1 2 1 2 1 7 7 7 7 1 2000+ 30-45 3

SLDT reg16 SLDT mem16 SMSW reg16 SMSW mem16 STC STD STI STOS [ES:]dest STOSB [[ES:]dest] STOSW [[ES:]dest] STOSD [[ES:]dest] STR reg16 STR mem16 SUB SUB SUB SUB SUB SUB TEST TEST TEST TEST TEST VERR VERR VERW VERW WAIT WBINVD WRMSR XADD reg,reg reg,reg mem,reg reg,mem reg,immed mem,immed accum,immed reg,reg mem,reg reg,immed mem,immed accum,immed reg16 mem16 reg16 mem16

XADD mem,reg XCHG XCHG XCHG XCHG XCHG reg,reg reg,mem mem,reg accum,reg reg,accum

xadd string,bl xchg xchg xchg xchg xchg cx,dx bx,pointer [bx],ax ax,cx cx,ax

4 3 3 3 2 2 4 4 1 2 3 1 3 1

XLAT [[segreg:]mem] XLATB [[segreg:]mem] XOR XOR XOR XOR XOR XOR reg,reg reg,mem mem,reg reg,immed mem,immed accum,immed

xlat xlatb es:table xor xor xor xor xor xor cx,bx cx,flags [bp+10],cx bl,1 switches[bx],101b ax,01010101b