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1) Th nghi m 1_1: Th c hi n m ch th nghi m c ng vo la 10 cng t c SW9->0, v ng ra l 10 n LED mu LEDR9->0 dng c tr ng thi cc ng vo. - Vi t ch ng trnh Verilog : module tn1_1 (SW, LEDR); input [9:0] SW; output [9:0] LEDR; assign LEDR = SW; endmodule Bin d ch m ch c thi t k

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2) Th nghi m 1_2 Dng 4 b multiplexer 2 sang 1 th c hi n m ch multiplexer 2 sang 1-4 bt. M ch c 2 ng vo nh phn 4 bt X v Y, v ng ra 4 bt M. N u s=0 th M=X, cn n u s=1 th M=Y. - Vi t ch ng trnh Verilog : module tn1_2(s,x,y,m); input [3:0]x,y; input s; output [3:0]m; assign m= (~s&x)|(s&y); endmodule

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3) Th nghi m 1_3 Dung 2 b multiplexer 4 sang 1 th c hi n m ch multiplexer 4 sang 1- 2bit. - Vi t ch ng trnh Verilog : module tn1_3(s,u,v,w,x,m); input [1:0]s,u,v,w,x; output [1:0]m; wire [1:0]g,t; assign g[0]=(~s[0]&u[0])|(s[0]&v[0]); assign g[1]=(~s[0]&u[1])|(s[0]&v[1]); assign t[0]=(~s[0]&w[0])|(s[0]&x[0]); assign t[1]=(~s[0]&w[1])|(s[0]&x[1]); assign m[0]=(~s[1]&g[0])|(s[1]&t[0]); assign m[1]=(~s[1]&g[1])|(s[1]&t[1]); endmodule Bin d ch m ch

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