8051 Compact Assembly Reference

const16 const8 direct addr16 Opcode 11+a 24 26+i 25 28+n 34 36+i 35 38+n 01+a 54 56+i 55 58+n B0 82 53 52 B6+i B4 B5 B8+n E4 C2 C3 F4 B2 B3 D4 16+i 14 15 18+n 84 D5 D8+n 06+i 04 05 A3 08+n 20 10 40 73 30 50 70 60 12 02 76+i F6+i A6+i 74 E6+i E5 E8+n = = = = 16bit Code const 8bit Code const 8bit IData addr 16bit Code addr Operands Bytes CY CY CY CY CY CY CY CY addr11 rel bit i=0-1 Flags AC AC AC AC AC AC AC AC OV OV OV OV OV OV OV OV = 11bit Code absaddr = 8bit Code reladdr signed = 8bit IData bit addr n=0-7 a=32*(absaddr shr 8) Cycles P P P P P P P P P P P P CY CY 2 1 1 1 1 1 1 1 1 2 1 1 1 1 2 2 2 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 4 2 2 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 1 1 2 1 1 1 1 92 A2 75 86+i F5 85 88+n 90 78+n F8+n A8+n 93 83 F0 F2+i E0 E2+i A4 00 44 46+i 45 48+n A0 72 43 42 D0 C0 22 32 23 33 03 13 D2 D3 80 94 96+i 95 98+n C4 C6+i C5 C8+n D6+i 64 66+i 65 68+n 63 62 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX MUL NOP ORL ORL ORL ORL ORL ORL ORL ORL POP PUSH RET RETI RL RLC RR RRC SETB SETB SJMP SUBB SUBB SUBB SUBB SWAP XCH XCH XCH XCHD XRL XRL XRL XRL XRL XRL 3 2 1 0 PSW 7 6 5 4 CY AC F0 RS1 RS0 OV F1 P RS0 RS1: register bank selection; mem: 00 :00-07 01 :08-0f 10 :10-17 11 :18-1f bit, C C, bit direct, #const8 direct, @Ri direct, A direct, direct direct, Rn DPTR, #const16 Rn, #const8 Rn, A Rn, direct A, @A+DPTR A, @A+PC @DPTR, A @Ri, A A, @DPTR A, @Ri AB 2 2 3 2 2 3 2 3 2 1 2 1 1 1 1 1 1 1 1 A, #const8 2 A, @Ri 1 A, direct 2 A, Rn 1 C, /bit 2 C, bit 2 direct, #const8 3 direct, A 2 direct 2 direct 2 1 1 A 1 A 1 A 1 A 1 bit 2 C 1 rel 2 A, #const8 2 A, @Ri 1 A, direct 2 A, Rn 1 A 1 A, @Ri 1 A, direct 2 A, Rn 1 A, @Ri 1 A, #const8 2 A, @Ri 1 A, direct 2 A, Rn 1 direct, #const8 3 direct, A 2 2 1 2 2 1 2 2 2 1 1 2 2 2 2 2 2 2 4 1 1 1 1 1 2 2 2 1 2 2 2 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1

Mnemonic ACALL ADD ADD ADD ADD ADDC ADDC ADDC ADDC AJMP ANL ANL ANL ANL ANL ANL ANL ANL CJNE CJNE CJNE CJNE CLR CLR CLR CPL CPL CPL DA DEC DEC DEC DEC DIV DJNZ DJNZ INC INC INC INC INC JB JBC JC JMP JNB JNC JNZ JZ LCALL LJMP MOV MOV MOV MOV MOV MOV MOV

addr11 2 A, #const8 2 A, @Ri 1 A, direct 2 A, Rn 1 A, #const8 2 A, @Ri 1 A, direct 2 A, Rn 1 addr11 2 A, #const8 2 A, @Ri 1 A, direct 2 A, Rn 1 C, /bit 2 C, bit 2 direct, #const8 3 direct, A 2 @Ri, #const8, re3 A, #const8, rel 3 A, direct, rel 3 Rn, #const8, rel3 A 1 bit 2 C 1 A 1 bit 2 C 1 A 1 @Ri 1 A 1 direct 2 Rn 1 AB 1 direct, rel 3 Rn, rel 2 @Ri 1 A 1 direct 2 DPTR 1 Rn 1 bit, rel 3 bit, rel 3 rel 2 @A+DPTR 1 bit, rel 3 rel 2 rel 2 rel 2 addr16 3 addr16 3 @Ri, #const8 2 @Ri, A 1 @Ri, direct 2 A, #const8 2 A, @Ri 1 A, direct 2 A, Rn 1

CY

P P

CY

P P OV P P P P P

CY CY CY CY P CY P CY CY

CY CY

P P

CY CY CY CY CY CY CY AC AC AC AC OV OV OV OV

P P

CY

OV P

P P P P P P P P P P P P

P P P P

Memory organization

SFRs