Propagation Delays

Tphl

Tplh

50% point

Inverter Propagation Delay

Propagation Delays

clock
tsu thd

changing

stable

changing

Setup time (tsu) : the time that the signal must be stable before the clock edge Hold time (thd): the time that the signal must remain stable after the clock edge.

Propagation Delays
SEQUENTIAL SYSTEM DELAY 1. Pin to pin Propagation delay path (t P2P) : is any path from an input to an output that passes through any combinational gates (it can not pass to any register). Do not determine minimum clock period. 2. Clock to Output Delay path (t C2Q) : passes through exactly one register. (tC2Q)_SYS = tcomb_I2C + tC2Q_FF + tcomb_Q2O 3. Register-to-Register Delay path (tR2R) : the path involves two registers starting from the output of one register to the input of another register. (tR2R) must be equal or larger than the clock period. (tR2R) = (tC2Q)_ FF + tcomb_R2R + tsu_FF

Propagation Delays