ICSE2004 Proc.

2004, Kuala Lumpur, Malaysia

A 1.8-V Fully Differential 2-Stage OPAMP Switched-

Capacitor Delta-Sigma Modulator for Bluetooth Application
Zulfiqar Ali Abdul Aziz, Tun Zainal Azni Zulkifli and Basir Saibon
RFIC Group
School of Electrical and Electronic Engineering
Universiti Sains Malaysia
14300 Nibong Tebal Pulau Pinang.
,

E-mail: eezulfiq@eng.usm.mY, eezainal(&eng.usm.my, basir @gsm.m

Abstract This paper presents a fully- shall be able to operate at high-speed (the clock
differential OPAMP for the switched- frequency of the modulator will be 32-MHz)
capacitor multi-bit delta-sigma modulator. while consuming minimum amount of power.
The OPAMP has been designed using Silterra Traditionally, single-stage operational
0.18-jm CMOS technology for operation at transconductance amplifiers (OTAs) are
1.8-V. Simulation shows that the OPAMP is preferred in driving fully capacitive loads such as
capable to give mid-band gain as high as 76.59 those in a switched-capacitor circuit because they
dB and the unity gain frequency is 284.1-MRHz are very efficient in terms of speed and power
while consuming only 1.618-mW of power. At especially for the case of a telescopic
1.2-pF capacitive load, the OPAMP archives a
73.610 phase margin and will increase as the configuration.
As new technologies with shorter channel
load decreases.
lengths being used, it becomes more and more
I. INTRODUCTION difficult to archive high gain in single-stage
OTAs due to the degradation of output-
OPAMP being the most basic building block in impedance caused by short channel effects. The
most analog and mixed-signal IC circuit is cascode current mirror solves the problem at the
always the performance limiting factor of a expense of lower voltage swing. As the power-
design. In applications such as switched- supply voltage scales down below 3-V, single-
capacitor filter, delta-sigma modulator, and stage OTAs become less attractive because of the
sample-and-hold amplifier, speed and settling difficulties in realizing high output-impedance
accuracy is determined by the performance of the active load without reducing the output voltage
OPAMP. The settling speed is mainly governed swing significantly. Although the introduction of
by the unity gain frequency and linear settling wide-swing current mirrors [*] are able to
time while the settling accuracy is determined by perform better than traditional cascode circuits,
the DC gain of the OPAMP. Switched-capacitor the improvements they offer does not help much
circuits rely on charge being transferred from one when the power supply drops below 2-V and the
capacitor to another rapidly; therefore it is not even shorter channel lengths being used.
uncommon for the OPAMP to slew-rate limit On the other hand, the 2-stage OPAMP has
thus adding another design consideration. For the historically been the most popular approach for
use in switched-capacitor circuits, a general rule both bipolar and CMOS OPAMP. The fully-
of thumb is that the clock frequency should be 5 differential versions of this classic OPAMP are
times lower in frequency and than the unity gain well-suited to low-voltage application because
frequency and the phase margin is at greater than they do not require cascode output stages. One of
70 degrees. [*] the downside of it is that extra capacitor is
This paper describes the design of a low- needed for frequency compensation, thus
voltage operational amplifier operating at 1.8-V reducing the bandwidth. Extra power is needed
for the switched-capacitor multi-bit delta-sigma in order to reclaim the lost bandwidth and
modulator. Compared to prior art [*], the causing it to dissipate more power compared to
principal challenge here is to implement the its single-stage counterparts.
OPAMP using CMOS process. The OPAMP

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 ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

II. ARCHITECTURES these are very desirable but, sadly, they also
A. Cutrrent Mirror OPAM increase the parasitic capacitance at node N I and
N2. This causes the design very difficult to
Two different architectures have been
considered to be used in the multi-bit delta-sigma converge without consuming too much power
modulator, the current-mirror fully-differential and area.
architecture and the 2-stage fully-differential B. 2-Stage Differential OPAMP
architecture. The schematic of the current-mirror An alternative to the current mirror OPAMP is
OPAMP is showed below. the fully-differential version of the classical 2-
stage. It is capable of very high gain and output
swing. The input referred noise will be smaller
vdd also compared to other architecture because the
vbiasp noise of the 2nd gain stage will be attenuate by
the differential stage. The main design issue with
vip Vill
vcasc p
this topology is the compensation. Miller
yap! voni compensation, also known as pole-splitting
vc ascn compensation, moves the dominant pole to a
lower frequency without affecting the second
pole. This effect makes the OPAMP more stable
gnd but slower at the same time. In lead
compensation, the right-half plane zero is moved
Fig. I. Fully-differential current-mirror OPAMP - K into the left half plane to cancel the non-
indicates the current gain. dominant pole. Another alternative is to move
the zero to a frequency slightly higher than the
It is immediately seem that all nodes are low unity gain frequency that would result if the lead
impedance except for the output node. The resistor were not present. In this case, the unity-
output current mirrors have been implemented gain frequency will be about 15 % below the
using wide-swing cascode current mirrors in equivalent second-pole frequency.
order to archive high gain and large output swing.
The K factor is the current gain from the input vdd
transistors to the output sides of the current vbiasp
mirrors connected to the output node. Obviously,
for larger values of K, the transconductance is -1 3F<n~ vcSm Hvc trt
higher and therefore the unity gain frequency and Cc
ml M2
Cc
the dc gain will be higher.
The non-dominant poles of OPAMP are
determined primarily by N I and N2. As the K yap von
increase, the total capacitance at the NI and N2 M3 I1
nodes increases as well causing the equivalent M4
second pole to move to lower frequencies. If K
increases too much, an increase in the load
capacitance is needed to keep unity gain Fig. 2. Fully-differential 2-stage OPAMP
frequency below the frequency of the equivalent
second pole to maintain stability, which in turn The transconductance of the differential pair
slows down the OPAMP tremendously. Besides, and the compensation capacitor determine the
there are a few other contradicting requirements unity gain frequency as given as below; signify
surrounding these 2 nodes. First of all, increasing that either increasing the transconductance of the
the size of the active NMOS loads will reduce differential pair (by larger bias current or large
the I/f noise significantly. Secondly, increasing W/L ratio) or reducing the capacitance of the
the L of the load NMOS will increase the DC compensation capacitor will increase the unity
gain by increasing the load impedance. Both of gain frequency. In this design, efforts had been
made to minimize the compensation capacitance

0-7803-8658-2/04/$20.00(c)2004 IEEE 438

 ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia
in order to reduce the power dissipation and area
while still being considerable stable.
ola __ (1)
C'
It is realized that the OPAMP to be used in a
multi-bit delta-sigma is not necessary very fast
because the multi-bit architecture does not
require a very high oversampling ratio to archive
high SNR ratio. Simulation results shown that
the fully-differential 2-stage OPAMP is capable
of providing adequate speed while consuming
modest amount of power and space although the
current-mirror and folded cascode OPAMP
seems to catch up at higher speed.
The noise of the OPAMP is primarily
contributed by the i/f of input differential pair
and the NMOS loads. Noise can be reduce
significantly by increasing the area of them, but
this will degrade the speed and stability since
increasing the area of the device will introduce
more parasitic capacitance (shown as C,) which
will lower down the equivalent pole.
1rgnl 'in
Fig. 3. Equivalent half circuit of the OPAMP - The RI
is the parallel combination of the MI and M3
transistors which is the output resistance of the first
stage amplifier. Cl is mainly contributed by the gate
of M4 and the drain of M3. R2 is the output resistance.
C2 is contributed by load capacitance
The dominant pole of the circuit will be
determined by the compensation capacitance and
the gain of the 2nd stage (Miller effects) as show
in the following equation.
I The capacitor labeled Cc generates the average
co = (2)
r RthnRpCg
d
Whereas the non-dominant pole is given by
0-7803-8658-2/04/$20.00(c)2004 IEEE 439
Ct) = gm4
(3)
2C +C2
III. COMMON-MODE FEEDBACK
A common-mode feedback (CMFB) circuit is
typically needed to control the common-mode
voltage at differential nodes that cannot be
stabilized by the negative differential feedback.
The common-voltage is usually set to yield
maximum differential voltage gain and also
maximum output voltage swing. The CMFB also
capable of suppressing common-mode
component, that tends to saturate the differential
stage. There are two typical approaches to
designing CMFB circuits - a continuous-time
approach and a switched capacitor approach. The
former approach is often the limiting factor on
maximizing the signal swings. The switched-
capacitor approach is often used in switched-
capacitor circuits since they allow a larger output
signal swing.
vop vctrt vo1n
Cc Cc
02 0~'2 c12
Cs Cs
ct1i tt~1 $1
Ic ,--I I
Fig. 4. The common-mode feedback circuit - noticed
the differences between conventional CMFB where
all the phase I switches are connected to the common
mode voltage.
of the output voltages, which is used to create
reference voltages to be compared with the
common-mode voltage. A differential pair shown
in figure 5 will then amplified the difference
between the common mode voltage and the
sensed voltage from the switched-capacitor
 ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

network and generate the bias voltage for the
OPAMP's current sources accordingly. The
CMFB circuitry must be fast enough to ensure
fast settling. All the switches are realized by
minimum-size n-channel transistors except for
the switches connected to the output, which is
realized by transmission gates to accommodate
wider signal swing.
vdd
vbiasp
vc trl
Figure 6 shows the nominal open loop
frequency response of the OPAMP. It is obvious
that the equivalent 2nd pole of the OPAMP lies at
frequency higher than the unity gain frequency
due to lead compensation.
Figure 7 shows the phase plot of the OPAMP.
The common-mode rejection ratio and the power
supply rejection ratio are primarily determined
by the device mismatch. The process device
mismatch information is still not available up to
the time of this writing. Therefore, the simulated
CMRR and PSRR are not realistic, but the
numbers do shows the very good rejection to
common-mode signal such as noise compared to
its single-ended counterparts.
i nn

to opamp D gain 76d

current 80

source 60

Fig. 5. Differential pair that generate bias voltage 20

m
IV. SIMULATIONS ._

1 1 1 , 1l )3 10bA,1 5 1 ) 1) 1D Ito
The simulations had been carried out by using
SpectreRF® because of the switched-capacitor
CMFB cannot be simulated using normal AC -40
Uriity §ain Ireq,uenoy - 303M Hz
analysis. To accommodate a low power supply
voltage with good sampling switch performance,
the input common-mode voltage Vcm, of the
-60L i iX
operational amplifier in the modulator was set at Frequency (Hz)
0.6 V. This permitted the use of small, single n- Fig. 6. Differential gain plot for the OPAMP.
channel device for accurate definition of
sampling time conforming to a low value of the 0
input common-mode voltage. The input stage of 1 010
the amplifier employed a p-channel device, with
added benefit of lower Ilf noise and high slew
rate. i
II
The OPAMP was designed to have a dc gain Q)9
i0
of 76 dB, a unity gain frequency of 300 MHz, c--10
and a phase margin of 750 with two I pF
capacitive loads. As mentioned above, a
switched-capacitor is used to set the output
common-mode voltage at 0.9 V which
maximized the output swing. Transient analysis -270
shows that the OPAMP is capable of more than Frequency (Hz)
200 V/4is slew rate. The overshoot is 12% and
the settling time is 17.6 ns. Fig. 7. Differential phase plot for the OPAMP

0-7803-8658-2/04/$20.00(c)2004 IEEE 440

 ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

[2] Lei Wang, S. H. K. Embabi, "Low-Voltage High-

Speed Switched-Capacitor Circuits Without Voltage
Bootstrapper", IEEE Journal Of Solid-State Circuits,
Vol. 38, No. 8, August 2003, pp. 1411-1415
TABLE I [3] David A. Johns, Ken Martin, "Analog Integrated
SUMMARY OF THE PERFORMANCE OF THE 2-STAGE Circuit Design", John Wiley & Sons, Inc. 1997
OPAMP
Dc gain 76.44 dB
Gain-bandwidth Product 264.0 MHz
Unity Gain Frequency 303.3 MHz
Phase Margin 74.70
Gain Margin -23.8 dB
3dB Frequency 39.67 kHz
Common-mode rejection ratio 331.026 dB
Power-supply rejection ratio + 318.389 dB
Power-supply rejection ratio - 294.872 dB
Power 1.617 mW

TABLE II
TRANSIENT CHARACTERISTIC OF THE 2-STAGE
OPAMP
Slew rate (positive direction) 212.6 V/ps
Slew rate (negative direction) 212.6 V/s
Overshoot (positive direction) 11.9 %
Overshoot (negative direction) 11.9 %
Settling time (both direction) 17.6 ns

V. CONCLUSION

The fully-differential 2-stage operational

amplifier was successfully designed. It found that
for moderate speed and power, the 2-stage
topology is more suitable than the current-mirror
operational amplifier. The design archive a unity
gain frequency of 303 MHz and slew rate of
212.6 V/ps which is theoretically adequate for
switched-capacitor circuit at 32 MHz. At even
higher operating frequency, the single stage
transconductance operational amplifier with
regulated load will be more appropriate. The
proposed amplifier consumes 1.617 mW of
power is still within the power budget of the
whole delta-sigma modulator.

REFERENCES
[1] Jorge Grilo, Ian Galton, Kevin Wang, Raymond G.
Montemayor, "A 12-mW ADC Delta-Sigma
Modulator with 80 dB of Dynamic Range Integrated in
a Single-Chip Bluetooth Transceiver", IEEE Journal
Of Solid-State Circuits. Vol. 37, No. 3, March 2002, pp.
27 1-277

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