SDIN

LRCLK
SCLK
MCLK
RESET
PDN
SDA
PLL_FLTM
PLL_FLTP
AVDD/DVDD PVDD
OUT_A
OUT_C
OUT_B
OUT_D
BST_A
BST_C
BST_B
BST_D
3.3V 8V24V
SCL
Digital
Audio
Source
I C
Control
2
Control
Inputs
LC
LC
Left
Right
B0264-03
Loop
Filter*








SDIN
MCLK
SCLK
LRCLK
Serial
Audio
Port
Protection
Logic
ClickandPop
Control
Digital AudioProcessor
(DAP)
SDA
SCL
4
Order
th
Noise
Shaper
and
PWM
S
R
C
SampleRate
Autodetect
andPLL
Serial
Control
Microcontroller
Based
System
Control
TerminalControl
OUT_A
OUT_B
2 HB
FET Out
OUT_C
OUT_D
2 HB
FET Out
B0262-06




Temp.
Sense
VALID
FAULT
AGND
OC_ADJ
Power
On
Reset
Under-
voltage
Protection
GND
PWM_D
OUT_D
PGND_CD
PVDD_D
BST_D
Gate
Drive
PWM
Rcv
Overcurrent
Protection
4
Protection
and
I/OLogic
PWM_C
OUT_C
PGND_CD
PVDD_C
BST_C
Timing
Gate
Drive
Ctrl
PWM
Rcv
GVDD_CD
PWM_B
OUT_B
PGND_AB
PVDD_B
BST_B
Timing
Gate
Drive
Ctrl
PWM
Rcv
PWM_A
OUT_A
PGND_AB
PVDD_A
BST_A
Timing
Gate
Drive
Ctrl
PWM
Rcv
GVDD_AB
Ctrl
PulldownResistor
PulldownResistor
PulldownResistor
PulldownResistor
4
GVDD_CD
Regulator
GVDD_AB
Regulator
Timing
I
sense
B0034-05
P
W
M

C
o
n
t
r
o
l
l
e
r
FAULT






L R
+ +
+ +
+
+
V
o
l
1
V
o
l
1
e
a
l
p
h
a
e
a
l
p
h
a
1
B
Q
1
B
Q
1
B
Q
1
B
Q
5
B
Q
5
B
Q
2
B
Q
2
B
Q
2
B
Q
I n p u t M u x i n g
L
o
g
M
a
t
h
L
o
g
M
a
t
h
A
t
t
a
c
k
D
e
c
a
y
A
t
t
a
c
k
D
e
c
a
y
1 1
4
6

[
D
0
]
D
R
C
-
1
D
R
C
-
2
4
6

[
D
1
]
E n e r g y
M A X M U X
E n e r g y
M A X M U X
e
a
l
p
h
a
e
a
l
p
h
a
[
0
]
[
0
]
[
1
]
[
1
]
[
2
]
[
2
]
[
1
]
[
1
]
[
0
]
[
0
]
[
0
]
[
3
]
[
3
]
[
2
]
[
2
]
[
1
]
5
1
5
5
2
A
5
3
5 7
H
e
x

n
u
m
b
e
r
s

r
e
f
e
r

t
o

I
C

s
u
b
a
d
d
r
e
s
s
e
s
[
i
]

b
y
t
e

"
i
"

o
f

m
u
l
t
i
b
y
t
e

s
u
b
a
d
d
r
e
s
s
[
D
i
]

b
i
t

"
i
"

o
f

s
u
b
a
d
d
r
e
s
s
2
3
1
2
B
-
2
F
3
2
-
3
6
5
8
-
5
9
5
C
-
5
D
5
E
-
5
F
2
9
3
0
5
4
S
u
m
/
2
L R
2
1

[
D
8
]
V
o
l
2
+
5
2
5 6
2
B
Q
5
A
-
5
B
T o P W M
B
0
3
2
1
-
0
5
3
A
3
A
3
D
3
D
3
E
-
3
F
3
B
-
3
C
5
0

[
D
7
]





SSTIMER
OC_ADJ
PLL_FLTP
VR_ANA
NC
AVSS
PLL_FLTM
BST_A
GVDD_OUT
PVDD_A
OUT_A
RESET
PVDD_A
STEST
P
D
N
V
R
_
D
I
G
O
S
C
_
R
E
S
D
V
S
S
O
DVDD
M
C
L
K
F
A
U
L
T
S
C
L
K
S
D
I
N
L
R
C
L
K
A
V
D
D
S
D
A
S
C
L
DVSS
GND
VREG
B
S
T
_
B
P
V
D
D
_
B
P
V
D
D
_
C
O
U
T
_
C
PVDD_D
BST_D
P
G
N
D
_
A
B
O
U
T
_
B
P
G
N
D
_
C
D
OUT_D
AGND
P
G
N
D
_
A
B
P
V
D
D
_
B
P
G
N
D
_
C
D
PVDD_D
B
S
T
_
C
P
V
D
D
_
C
GVDD_OUT
P0075-06
PHP Package
(TopView)
TAS5709
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33

t
h1
t
su1
t
(edge)
t
su2
t
h2
SCLK
(Input)
LRCLK
(Input)
SDIN
T0026-04
t
r
t
f

SCL
SDA
t
w(H)
t
w(L)
t
r
t
f
t
su1
t
h1
T0027-01
SCL
SDA
t
h2
t
(buf)
t
su2
t
su3
Start
Condition
Stop
Condition
T0028-01

t
w(RESET)
RESET
t
d(I2C_ready)
SystemInitialization.
EnableviaI C.
2
T0421-01
I C Active
2
I C Active
2

f Frequency Hz
20
PVDD = 18 V
R
L
= 8
100 1k 10k
T
H
D
+
N

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

%
20k
G001
P = 1 W
P = 5 W
0.001
0.01
10
0.1
1
f Frequency Hz
20
PVDD = 12 V
R
L
= 8
100 1k 10k
T
H
D
+
N

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

%
20k
G002
P = 2.5 W
0.001
0.01
10
0.1
1
P = 0.5 W

f Frequency Hz
20
PVDD = 8 V
R
L
= 8
100 1k 10k
T
H
D
+
N

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

%
20k
G003
P = 0.5 W
P = 1 W
0.001
0.01
10
0.1
1 P = 2.5 W
P
O
Output Power W
0.01
PVDD = 18 V
R
L
= 8
0.1 1 10
T
H
D
+
N

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

%
0.001
0.01
10
40
0.1
G004
1
f = 20 Hz
f = 1 kHz
f = 10 kHz
P
O
Output Power W
0.01
PVDD = 12 V
R
L
= 8
0.1 1 10
T
H
D
+
N

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

%
0.001
0.01
10
40
0.1
G005
1
f = 20 Hz
f = 1 kHz
f = 10 kHz
P
O
Output Power W
0.01
PVDD = 8 V
R
L
= 8
0.1 1 10
T
H
D
+
N

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

%
0.001
0.01
10
40
0.1
G006
1
f = 20 Hz
f = 1 kHz
f = 10 kHz













PVDD Supply Voltage V
2
4
6
8
10
12
14
16
18
20
8 9 10 11 12 13 14 15 16 17 18
P
O

O
u
t
p
u
t

P
o
w
e
r

W
G010
R
L
= 8
THD+N = 1%
THD+N = 10%
P
O
Output Power (Per Channel) W
0
10
20
30
40
50
60
70
80
90
100
0 4 8 12 16 20 24 28 32 36 40
E
f
f
i
c
i
e
n
c
y

%
G012
PVDD = 12 V
PVDD = 18 V
R
L
= 8
PVDD = 8 V
100
90
80
70
60
50
40
30
20
10
0
f Frequency Hz
C
r
o
s
s
t
a
l
k

d
B
G013
20 100 1k 10k 20k
Left to Right
Right to Left
P
O
= 0.25 W
PVDD = 18 V
R
L
= 8
100
90
80
70
60
50
40
30
20
10
0
f Frequency Hz
C
r
o
s
s
t
a
l
k

d
B
G014
20 100 1k 10k 20k
Left to Right
Right to Left
P
O
= 0.25 W
PVDD = 12 V
R
L
= 8













100
90
80
70
60
50
40
30
20
10
0
f Frequency Hz
C
r
o
s
s
t
a
l
k

d
B
G015
20 100 1k 10k 20k
Left to Right
Right to Left
P
O
= 0.25 W
PVDD = 8 V
R
L
= 8

23 22
SCLK
32Clks
LRCLK(NoteReversedPhase)
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15 14
MSB LSB
32Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0034-01
5 4 9 8
1 0
0
4 5
1 0
23 22 1
19 18
15 14
MSB LSB
5 4 9 8
1 0
0
4 5
1 0
SCLK

23 22
SCLK
24Clks
LRCLK
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15 14
MSB LSB
24Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput/Output(24-Bit TransferWordSize)
2
T0092-01
3 2 5 4 9 8 17 16
1 0
0
4 5 13 12
1 0 9 8
23 22
SCLK
1
19 18
15 14
MSB LSB
3 2 5 4 9 8 17 16
1 0 4 5 13 12
1 0 9 8
SCLK
16Clks
LRCLK
LeftChannel
16-BitMode
1 1 15 15 14 14
MSB LSB
16Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0266-01
3 3 2 2 5 5 4 4 9 9 8 8 0 13 13 10 10 11 11 12 12
SCLK
MSB LSB

















23 22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15 14
MSB LSB
32Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput
T0034-02
4 5 9 8
1 4 5
1
0
0
0
23 22 1
19 18
15 14
MSB LSB
4 5 9 8
1 4 5
1
0
0
0
SCLK















23 22
SCLK
24Clks
LRCLK
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15 14
MSB LSB
24Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput(24-Bit TransferWordSize)
T0092-02
4 5 9 8 17 16
1 4 5 13 12
1 9 8
0
0
0
21
17
13
23 22
SCLK
1
19 18
15 14
MSB LSB
4 5 9 8 17 16
1 4 5 13 12
1 9 8
0
0
0
21
17
13
SCLK
16Clks
LRCLK
LeftChannel
16-BitMode
1 1 15 15 14 14
MSB LSB
16Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput
T0266-02
3 3 2 2 5 5 4 4 9 9 8 8 0 0 13 13 10 10 11 11 12 12
SCLK
MSB LSB













23 22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15 14
MSB LSB
SCLK
32Clks
RightChannel
2-ChannelRight-Justified(SonyFormat)StereoInput
T0034-03
19 18
1 19 18
1
0
0
0
15 14
15 14 23 22 1
15 14
MSB LSB
19 18
1 19 18
1
0
0
0
15 14
15 14















23 22
SCLK
24Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15 14
MSB LSB
SCLK
24Clks
RightChannel
MSB
2-ChannelRight-JustifiedStereoInput(24-Bit TransferWordSize)
T0092-03
5 19 18
1 5 19 18
1 5
0
0
0
2
2
2
6
6
6
15 14
15 14 23 22 1
15 14
5 19 18
1 5 19 18
1 5
0
0
0
2
2
2
6
6
6
15 14
15 14
LSB

7-BitSlave Address
R/
W
8-BitRegister Address(N) A
8-BitRegisterDataFor
Address(N)
Start Stop
SDA
SCL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
A
8-BitRegisterDataFor
Address(N)
A A
T0035-01























































A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress DataByte
T0036-01

D7 D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress LastDataByte
A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK
Start
Condition
Acknowledge Acknowledge Acknowledge
FirstDataByte
A4 A3 A6
OtherDataBytes
ACK
Acknowledge
D0 D7 D0
T0036-02












































A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress DataByte
D7 D6 D1 D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/W A1 A1
RepeatStart
Condition
T0036-03

A6 A0 ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/W A6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
T0036-04






















O
u
t
p
u
t
L
e
v
e
l
(
d
B
)
Input Level (dB)
T
O
K
M0091-02
1:1 TransferFunction
Implemented TransferFunction
S
Z
1
AlphaFilterStructure
w
a
B0265-01
Energy
Filter
a w , T,K,O a w
a
,
a d d
/ , a w
DRC1
DRC2
0x3A 0x40,0x41,0x42 0x3B/0x3C
0x3E/0x3F 0x43,0x44,0x45 0x3D
Compression
Control
Attack
and
Decay
Filters
AudioInput DRCCoefficient
NOTE:
=1 w


















2 Bit
23
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
2 Bit
5
2 Bit
1
2 Bit
0
SignBit
2 Bit
1
M0125-01



































(1or0) 2 +
1
(1or0) 2 +(1or0) 2 +.......(1or0) 2 +.......(1or0) 2
0 1 4 23
2 Bit
1
2 Bit
0
2 Bit
1
2 Bit
4
2 Bit
23
M0126-01
u
Coefficient
Digit8
u u u u u S x
Coefficient
Digit7
x. x x x
Coefficient
Digit6
x x x x
Coefficient
Digit5
x x x x
Coefficient
Digit4
x x x x
Coefficient
Digit3
x x x x
Coefficient
Digit2
x x x x
Coefficient
Digit1
Fraction
Digit5
Fraction
Digit4
Fraction
Digit3
Fraction
Digit2
Fraction
Digit1
Integer
Digit1
Sign
Bit
Fraction
Digit6
u=unusedordontcarebits
Digit=hexadecimaldigit
M0127-01
0






























I
n
i
t
i
a
l
i
z
a
t
i
o
n
5
0

m
s
5
0

m
s
2
s
m
2
s
m
2
s
m
2
s
m
A
V
D
D
/
D
V
D
D
P
D
N
P
V
D
D
R
E
S
E
T
T
0
4
1
9
-
0
1
3

V
3

V
0

n
s
0

n
s
0

n
s
1
0
s
m
1
0
0
s

1
3
.
5

m
s
1
0
0
s
m
6

V
6

V
8

V
8

V
I
S
2
M
C
L
K
L
R
C
L
K
S
C
L
K
S
D
I
N
I
C
2
S
C
L
S
D
A
T
r
i
m
V
o
l
u
m
e

a
n
d

M
u
t
e

C
o
m
m
a
n
d
s
C
l
o
c
k

C
h
a
n
g
e
s
/
E
r
r
o
r
s

O
K
S
t
a
b
l
e

a
n
d

V
a
l
i
d

C
l
o
c
k
s
S
t
a
b
l
e

a
n
d

V
a
l
i
d

C
l
o
c
k
s
E
x
i
t
S
D
E
n
t
e
r
S
D
D
A
P
C
o
n
f
i
g
O
t
h
e
r
C
o
n
f
i
g
1

m
s

1
.
3

t
s
t
a
r
t
(
2
)
1

m
s

1
.
3

t
s
t
a
r
t
(
2
)
t
P
L
L
(
1
)
t
P
L
L
(
1
)
1

m
s

1
.
3

t
s
t
o
p
(
2
)
0

n
s
N
o
r
m
a
l

O
p
e
r
a
t
i
o
n
S
h
u
t
d
o
w
n
P
o
w
e
r
d
o
w
n
(
1
)

t
h
a
s

t
o

b
e

g
r
e
a
t
e
r

t
h
a
n

2
4
0

m
s

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PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
TAS5709PHP ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TAS5709PHPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TAS5709PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TAS5709PHPRG4 ACTIVE HTQFP PHP 48 1000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-May-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)
W
(mm)
Pin1
Quadrant
TAS5709PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 23-May-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5709PHPR HTQFP PHP 48 1000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-May-2009
Pack Materials-Page 2