MN HC

Thit k board giao tip

(Interface Board Design)

By Trn Vn Hng Mechatronics Dept

http://www.ntu.edu.vn/
Email: tvh42th@gmail.com

Ti liu tham kho

1. 2. 3. 4. 5. 6. Microprofessors and microcpmputers hardware and softwware, Ronaid J.Tocci, Frank J.Ambrosio, Prentice Hall, 2003 Interfacing Sensors To The Pc, Willis J.Tompkin, Jonh G.webster, Prentice Hall, 1998 Microprocessor Interfacing techniques, R. Zaks & A. Lease, Sybex Micro Processor and Interfacing, D. Hall, McGraw Hill; Parallel port complete, J.Axelson, LakeViewReseach Mastering Serial Communication, P.W.Gofton, Sybex

Ni dung chng trnh

n n n n n n

Ch01: Giao thc ghp ni Ch02: Giao din bus Ch03: Giao din s Ch04: Giao din tng t Ch05: Vi iu khin Ch06: Bn phm

Cc bi ton
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

Thit k mch iu khin nh sng theo chng trnh nh trc Thit k mch trang tr bng n LED Thit k mch nhn dng im phc v (thm t nht 2IC) Thit k mch o lng ma Thit k mch iu khin nhit khng kh Thit k mch iu khin nhit dung dch Thit k mch ng h in t Thit k mch tnh thi gian cho cc mn in kinh Thit k bng quang bo Thit k mch kho in t Thit k mch iu khin thit b bng remote Kt ni bn phm my tnh vi VXL, hin th k t ln LCD Thit k mch iu khin Robot chy theo qy o (sd motor bc) Thit k mch iu khin tc ng c DC Thit k mch iu khin gc quay ca mt, n tc cho motor.

Chng 1: Giao thc ghp ni

n n n n n n

Tn hiu Format Tc In/Out Li v kim sot li B lnh v tr li Kch bn

1.1 Tn hiu
Khi thit k, xy dng ghp ni my tnh, cn ch c bit ti cc tn hiu theo yu cu:
n Analog/Digital
n Digital:

Trng thi ca s vt, hin tng, format, mc logic, p/dng, di o, phn ly, thi gian tc ng, chnh xc, lp li, gi tr o

n Analog:

n Hn

mt thit b? => bus/mng hay khng? => dng bit (trng) a ch - ty tng ngi

1.1 Tn hiu (tip)

n

Nu dng bus => Standard bus hay khng (ISA, I2C, USB, hay cc bus trn chun RS485)? IDE v LPT Mode 0 cables l bus? Ti sao? Khong cch: Xa/gn => Serial, Parallel, c lin quan n tc Xa: Daisy chain cho tn hiu hoc ngun cp Cc tn hiu iu khin trng thi
n n n

n n

n n

Control signals Status signals Handshaking sighals

1.1 Tn hiu (tip)

n

Daisy chain
Ni cc thit b c khong cch t vi n vi chc m, output ca port (modul) th i ni vi input ca i+1. c bit cc Field Buses, c th ln ti km n Dng cho c tn hiu \\ v ni tip, ngun cp, handshaking,
n

CPU
IO_0 IO_1

IO_n

1.1 Tn hiu (tip)

n

Tnh cht vt l ca tn hiu: l hm ca thi gian, mc U/I

n n n n n

Direction: In/Out, ch v chiu ca dng in Voltage/Current/Optical/Wave Ch Input Voltage Mc in p: Mc p? (TTL, CMOS, ) Single End (n cc) Differrential signal:
n

Single End signed:

n n n n

Tn hiu so vi mt in th chun, thng l GND (0 Volt) V d: Cc tn hiu trn bus (data, add, control) C n tn hiu => c t nht n+1 dy dn Nhy cm vi nhiu, tc thp hn so vi cng chun

1.1 Tn hiu (tip)

n

Differential Signal: Tn hiu vi sai

n

n tn hiu => 2*n dy dn pha thu

n n

(Va Vb)>100mV=> logic 1, ty thuc vo chun c p dng (Va Vb)<100mV=> logic 0

Thu: Nu c hai dy c cng kch thc, di, tr khng, v gn nhau, th mi trn h c loi tr => chu c nhiu rt tt v pha thu
n

Uin = k(Va Vb) => nhng thnh phn ging nhau c loi b

n n n

Khong cch ln, tc cao. IC: SN75176 ca TI l v d a ch ng dng: USB cable, Profibus,
n cc n cc A B

+ Vc = k(Va Vb)

1.1 Tn hiu (tip)

n

Kh nng phi hp ti dng in ra:

n n

S ti Chiu dng in Sink hay Source

n n n n

Ni chung/ghp ni bus n gin: 3 state, Mux, Switch. Hot swap hot plugible: yu cu Vcc v tn hiu Cch ly (isolation): Relay, Opto coupler, IrLED Bus slot, Connecter, chun, s chn (pin)

1.1 Tn hiu (tip)

5V

Sourse

MCU

Outport Buffer

LED

Sink
R LED

5V

Hnh: Sink Sourse connection

1.1 Tn hiu (tip)

5V

Hnh: Open collecter

1.1 Tn hiu (tip)

n

Connecter
n n

D shell: DB9, DB25, DIN

Cable
n n n

Flat Coaxial, Shield: Cho tn hiu hoc ngun cp Twisted Pair: 5, 6 Vi sai Optical Fiber
Hnh: Connecter

n n n

1.2 Format
n

Thng tin c nh dng theo: binary/hex (ASCII)

VD: 1 s o nhit 12 bits, di gi tr 0 n 9990 C. Khi lu trong CSDL, truyn tin:
n n

12 bits (1,5 byte) tit kim b nh, thi gian truyn ASCII: 3 characters: D qun l, kim sot sai, hin th

Lng tin ln => khi trao i (vi DAS, PLC, GPS, Digi-Oscillocope,)
n

Header: [tn (bn tin, gi), s th t, kt bt tay, kt ng b, s kt/byte trong gi,] khng mang tin. Content: ni dung tin mang thng tin Tailer: M bt tay kt thc, [m kim li] khng mang tin

n n

1.2 Format (tip)

8 bits 0 1023 bytes 16bits

PID

Data
Hnh: USB data packet format

CRC16

Byte s liu/character/frame: (truyn khng ng b, RS-232, RS-485, RS-422): c nh dng thnh 1 frame:
n n n n

1 start bit = 0 5/6/7/8 data bit, D0 first [parity: Even/odd] 1/1.5/2 stop bit = 1

1.3 Tc In/Out
n

Xut pht t: Nhu cu trao i thng tin ca h (tc v khong cch) => chn kiu truyn thch hp, c lin quan n tn hiu:
n

Ch ra cc bottle_neck, khc phc c => xut hin cc bottle neck mc thp hn Ph thuc vo khong cch tch s (k/c v tc ) Nhiu: theo cng thc ca Shannon bps = BW log2(1+P/N). Vi BW: bandwidth, P/N: t s cng sut tn hiu/nhiu ng truyn: (cng nghip) cp ng trc, cp quang, wireless,) Synchronous/Asynchronous Modulation/Demodulation=>Tc bao nhiu kbps/kBps?

n n

n n n

VD: LPT: SPP mode: 50100kBps; RS-232: 2400/4800/9600/19200/bps

1.4 Li v kim sot li

n

Khi trao i thng tin thng gy ra li, c bit truyn xa/chuyn i tn hiu. Nhiu phng php (hardware, Software) h tr kim tra: [Block] check sum BCC, phn mm: tnh tng ca tt c cc k t, cc byte. Kt qu c th ly 1 byte
n

VD: ROM BIOS, Ext BIOS started @ chn 2K, 2 u l m 0x55 v 0xAA, di ca mng ROM l 512 byte; checksum b 2 sao cho tng ca tt c cc byte v m checksum lun bng zero

n n n

CRC, ECC, vi mch/software subroutine Parity, 1 hoc 2 chiu Redundancy (RAID), tha d

1.5 B lnh v tr li
n

Khi ghp Intelligent Devices (Computerized devices mouse, KB, Printer, modem, FDC, HDC, RTU) c nhiu tham s, ch hot ng => xy dng b lnh (command set) v thng tin tr v (response set) n Cc cu lnh phn mm => bt tn hiu v cng phn cng
n

Tp hp cc yu cu t CS command set n Tp hp cc tr li, trng thi result/response/reaction set Data down/up n Symtax of command and response (structure and grammar)
n

1.6 Kch bn
n

Lit k cc trng hp ri c th p cc php ton x l tng ng m bo vic ghp ni: khng mt tin, tha tin, qun, treo, Thng xy dng theo liu Step List hoc chart Timeout

Master

Slave

ACK ACK NACK

n n

t
Hnh: Scenario Chart

V d: giao thc gia PC v VK trong vic trao i d liu (U, I, t0,)

n n n n n n n

Tn hiu? Format? Tc ? Li? Lnh v tr li? Kch bn? .

1.7 Bi tp
1. Vit chng trnh gi lp RS-232 2. Vit chng trnh nhp k t trn my tnh ri hin th k t ln LCD 3. o gi tr nhit ( m, U, I,) ri hin th ln my tnh (gtr v dng biu ).

Chng 2: Giao din Bus

n n n n

Khi nim v Bus ghp ni - In/Out Buses ISA Bus USB Philips I2C

2.1 Khi nim v Bus ghp ni

n n

n n n

L PCB (Printed Circuit Board), Cable (Copper/Optic), Slot, Connector Ni nhiu thit b slave [master], dng chung: trong mt thi im ch c mt talker 1 hoc nhiu listener Bus song song (n bit) hoc ni tip (I2C, USB, Profi,) IO Buses, Mem, CPU, Local Buses Thnh phn (physical lines/time sharing:
n n n n

Address Data Control/Status/Handshake/datacheck Power susply

2.2 Industry Small Architecture Bus

n n

n n

n n n

ISA, 1984, IBM, PC-104 bus ghp thm cc card/ thit b I/O chun vi Mother Board, 112Slots, hin ti cc my thng thng khng dng. 8/16 bits for data transfers 4,77=>8,33 MHz/11.1MHz => 2.75MWps/5.5MWps max, DMA 16 Only 1 BusMaster, CPU hoc DMAC, w AEN No data integrity, khng kim tra parity Dng ghp ni vi cc thit b chm, kiu k t: keyboard, mouse,

2.2 Industry Small Architecture Bus (tip)

(http://pinouts.ru/Slots/ISA_pinout.shtml)

Hnh: ISA Bus

2.2 USB

Hnh: USB logo

2.2 USB (tip)

n

Chia thnh nhiu Tiers Cc Tiers ni vi cc thit b: Hub hoc chc nng Mi Tier c Hub(s)

Hnh: USB topology

2.2 USB (tip)

n n

Ch c mt USB host (USB controller trong h Devices, c 2 loi

n n

Hub, m rng thm thit b ni vo USB Cc thit b chc nng JoyStick, KeyBoard, Printer, Digital Camera, USB Protocol Chun H ca USB: config v reset Communication Standard

Cc thit b chun interface USB theo:

n n n

2.2 USB (tip)

n

Thng s k thut:
n n n n

1.5Mbps Low speed moade v 12 Mbps (Revision 1.1) Ngun cp +5V, vi metre Power management

Revision 2.0: 480Mbps u im: n Tn hiu vi sai pht/thu, bc kim, chng nhiu n CRC Protection i vi data & control fields n T pht hin attach/detach, xc nh cu hnh cc thit b t ng mc h thng n TimeOut i vi trng hp mt tin/gi tin li

2.2 USB connecter (tip)

2.2 USB signal (tip)

Hnh: Signal

2.2 USB signal (tip)

Token Packet Format

Start-Of-Frame (SOF) Packet Format

Data Packet Format

Handshake Packet Format

2.3 Philips I2C Bus

n

n n n n n

Dng nhiu trong cc h thng nhng (embeded system) nh: mobil phone, TV, ATM, Khng cn dng bus interface chip(s), built-in Intergrated addressing & data transfer, cho php dng phn mm nh cu hnh n gin ghp ni, nhiu C h tr I2C n gin tm li, khoanh cng li nhanh Gim thiu kch thc: 2 wire serial, khng cn dng cc mch addr decoder v glue logic, dng phn mm Truyn ng b, 100Kbps standard mode, 400Kps Fast mode, 3,4Mbps HiSpeed mode

2.3 Philips I2C Bus (tip)

SCL SDA Device_0 Device_1 Device_2 Device_3 Device_4 Device_5 Device_6

Hnh: I2C Topology

2.3 Philips I2C Bus (tip)

SCL SDA Slave_0

C th c nhiu Masters, trong mt thi im ch c 1 Master hot ng

Master_0 Slave_1 Slave_2 Master_1 Slave_3 Slave4

Hnh: Configuration with 2 masters

2.3 Philips I2C Bus (tip)

Hnh: Start and stop

2.3 Philips I2C Bus (tip)

Hnh: Data transfer

2.3 Philips I2C Bus (tip)

5V

Hnh: Open collecter

2.3 Philips I2C Bus mt s chip(tip)

Atmega, PIC, n EEPROM, RAM, n RTC,
n

Bi tp chng 2
1. Vit chng trnh gi lp I2C

10

Chng 3: Digital Interface

n

Parallel Interface

Serial Interface

3.1 Parallel - principle

n

In/Out nhiu bit ng thi, tc nhanh nhng khong cch gn Mt u IO

n n

Output Port: latched Output (cht ra), D-Flip-Flops Unlatched In Input

3.1 Parallel - principle

n

D Flip Flop (HC373, 374)

n n n

L mt dy nhng phn t c bn ca dy D data, lu tr mt bit s liu 4/6/8 D flip-flop => to ra 4/6/8 bits register, nhiu register ng trong mt chip l SRAM

3.1 Parallel principle D Flip Flop

n

Output:
n n

Q - ng vi gi tr data input vo thi im c clock /Q o ca Q. Data bit: 1 hoc 0 Clock, thng l sn ln, ghi nhn gi tr ca data v lu li cho ti khi c bt s liu khc ghi ln [C th. c] clear xa; Preset t trc Slave (HC374)

Input
n n

C 2 lo.i: Transparent (HC373) v Mastern

3.1 Parallel principle D Flip Flop

n

Write pin: bit 0 or 1, clock =

n

Write bit 0: D flip-flop => Q = 0; /Q = 1 => gate = 1 => R(ds) MOSFET = ON => pin = 0 Write bit 1 D flip-flop => Q = 1; /Q = 0 => gate = 0 => R(ds) MOSFET = OFF => pin = 1

Read pin: (Input line out 1 firstly)

ReadPin = 0 (!) => open 3 state lower buffer => 1/0 from pin => data bus (i)

ReadLatch (Reading bit out previously):

ReadLatch = 0 (!) => open 3 state higher buffer => 1/0 from pin => data bus (i)

3.1 Parallel - principle

n

ng dng ghp ni LED, DAC,

Data
3 4 7 8 13 14 17 18 2 1 11 1 3 74LS02

+5V U38 D0 D1 D2 D3 D4 D5 D6 D7 CLK OE 74LS374 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19

IOW CS Strobe

3.1 Parallel - principle

n

ng dng ghp ni LED, DAC, ADC,

3.1 Parallel - principle

n

Latched Input Port

n n

Unlatched Inport Latched Inport

3.1 Parallel - principle

n

Output Port

3.1 Parallel - principle

n n

Ghp ni PPI 8255 vi PC qua ISA bus Addr: 300h-303h, Mode 0 all, PA & PC In, PB Out

3.1 Parallel - principle

n n

Mt cng IO Cng c tn hiu bt tay/trng thi

n n n

Cng ra n gin c cht (74HC 374/373/273,) Cng vo n gin ko cht (74244, 74245,) Cng vo c cht Gi mt packet ra ngoi vi, cn ng b gia hai pha Peripheral ch c b m cng khi c s liu.

Cng c tn hiu bt tay/trng thi

n n

3.1 Parallel - LPT

n

Data port
n

Out port: Gi mt byte ra cng

n n n

Mov dx, 378h Mov al, solieu Out dx, al Mov dx, 378h In al, dx

In port: c gi tr cng
n n

Control Outport, ch dng 4 bit: b0b3

n

Gi 4 bit
n n n

Mov, dx, 37Ah Mov al, control Out dx, al

3.1 Parallel - LPT

n

Control Outport, ch dng 4 bit: b0b3

n

c 4 bit
n n n

Out dx, al Mov, dx, 37Ah Out al, dx

Status Port: ch c trng thi, unlatched

n n

Mov dx, 378h In al, dx

3.1 Parallel - LED

n

LED: Light Emitting Diode Color:

n n n n

Red, Green, Yellow, Amber, R+G Infra Red, UV LASER: Light Amplification by Stimulated Emission of Radiation Blue, Cyan ...

Symbol & characteristics

3.1 Parallel - LED

n

Package and Applications:

n n n

Single point, status of devices 7 segment/ 16 segment, Arabian digit, char Matrix 8x8 / 16 x 16, character box, graphics modules

sng: Indoor, Outdoor (super light) and semioutdoor. sng ph thuc vo tng loi pha tp, t150mcd (normal) n 7000mcd (super light) c tnh LED: l diode phn cc thun, ty pha tp =>cho nhiu mu khc nhau v in p thun t: 1.5V..2.1V v 3.2.. 3.5V. TriColor: Red Green Blue => PWM driving => Fullcolor 16,7M colors (3 byte)

3.1 Parallel - LED

3.1 Parallel - LED

n n n n n n

Tnh ton mch iu khin LEDs: LED sng tnh sng lin tc Static Mode: Chn sng tng i Dng thun I, t 10 n 20mA in p thun U, t 1.6 n 3.4V Tnh R1 = (Vcc U)/I. V d: Vcc=5V, Chn RLI = 2 => IF=20mA => UF= 2V => R = (Vcc UF)/20mA = 150 Ohm

3.1 Parallel - LED

LED ch qut, Scan Mode: n Mch in t s iu khin sng 1 nhm phn t trong ton b bng mt khong thi gian (ms), ri iu khin nhm phn t tip theo cho n ht vng. Vi iu kin phi thc hin 50=>120 frames/second n Ty thuc sng v mi trng (in/outdoor) => thit k rng (duty cycle) ca tng phn t. Thng c chon l 1, , , 1/8 v 1/16

3.1 Parallel - LED

n

Tnh ton mch: cng ging nh cch tnh mch sng tnh, thng chn sng t 2cd=>5cd. Ch :
n

H s sng c th chn l: 1, , , 1/8 v 1/16 sng yu cu v dng LED outdoor an ton, tui th LED, gi tr gii hn ca IF , n mc no ni chung LED s khng sng thm khi IF>50mA

n n

Gc b tr ngc sng/thun sng View angle

3.1 Parallel - LED

Kt ni LED n 7406, ULN 2003... Open Collector n Inverter Buffer: upto 30V, 50-500mA; n Transistor npn: C945 khi outport = 1 => LED sng n Transistor pnp: A564, n khi outport=0 => LED n Mtl s outport cho php drive trc tip, sink/sourse upto 40mA

10

3.1 Parallel - LED

Kt ni LED

3.1 Parallel LED (7 seg)

LED 7 on, mu, kch thc, CA/CC?

11

3.1 Parallel - LED (7 seg)

n

Kt ni

3.1 Parallel - LED (7 seg)

n

iu khin LED

12

3.1 Parallel - LED (7 seg)

n n

C 4 LED (32 pins) iu khin ch qut ch 01 LED sng trong mt thi im => gim thiu phn cng, tng tnh mm do ca hin th - dng phn mm iu khin, khng dng Ics BCD/7 seg
n

Mun sng (0, 1, 9) => gi m 7 thanh qua cc anodes Mun sng LED no, iu khin ON Anode LED trong mt thi gian t v l duy nht Tnh t: theo s LED v 50100 fps

3.1 Parallel LED (Matrix)

Mu, s mu, kch thc?

00010000 00101000 01000100 01000100 01111100 01000100 01000100 01000100

13

3.1 Parallel LED (Matrix)

n n

C 8 hng, 8 ct iu khin ch qut ch 01 LED sng trong mt thi im, dng 74138 chn hng

3.1 Parallel LED (Matrix)

n

Kt ni LED

14

3.1 Parallel LED (Matrix)

void Shift_Right(void)
{ char tmp; tmp = Row_00[numLED-1] & 0x01; for(i=(numLED-1); i>0; i--) { if(Row_00[i-1] & 0x01) Row_00[i] = (Row_00[i]>>1) | 0x80; else Row_00[i] = (Row_00[i]>>1) & 0x7F; } if(tmp) Row_00[0] = (Row_00[0]>>1) | 0x80; else Row_00[0] = (Row_00[0]>>1) & 0x7F; }

3.1 Parallel LED (Matrix)

void Shift_Right(void)
{ char tmp; tmp = Row_00[row][numLED-1] & 0x01; for(i=(numLED-1); i>0; i--) { if(Row_00[row][i-1] & 0x01) Row_00[row][i] = (Row_00[row][i]>>1) | 0x80; else Row_00[row][i] = (Row_00[row][i]>>1); } if(tmp) Row_00[row][0] = (Row_00[row][0]>>1) | 0x80; else Row_00[row][0] = Row_00[row][0]>>1; }

15

3.1 Parallel LED (Matrix)

#define LED_SCK PORTD.5 #define LED_RCK PORTD.6 #define LED_data PORTD.7 #define TIME_595 20 void Out_74595(char data) { char i; LED_RCK = 0; for(i=0; i<8; i++) { LED_SCK = 0; LED_data = (data & 0x01); data = data>>1; delay_us(TIME_595); LED_SCK = 1; delay_us(TIME_595); } LED_RCK = 1; }

3.1 Parallel LED (LCD)

16

3.1 Parallel LED (LCD)

n n

Cng ngh LCD Liquid Crystal Display, hin text/graphics phn gii
n n n n

1 line x 16 character box, 5x7 (7x9) dot matrix/character box 2 line x 16 character box 4 line x 20 character box Graphics (64 x 128) hoc (128 x 256) dot graphics font down loadable, color (16/4096/64K/16,7M).

n n n

ASCII, 128 characters/ set, 8 user fonts or APA: All Points Addressable - graphics Back light: Cng sut tiu th nh Dng cho cc h nh, mang xch, my o, (Embedded Systems)

3.1 Parallel LED (LCD)

17

3.1 Parallel LED (LCD)

3.1 Parallel LED (LCD)

Read/Write LCD information n 4 line x 20 column LCD => 80 char boxes n Write Addr Reg first (RS=0) n Write Data Reg after (RS=1) n MSB = 1 Address > 7Fh => control registers n V d mt chu k c/ghi LCD panel 8 bit bus:
n n n n n n n n

E=0 Pht a ch to Chip Select v chn Reg To tn hiu R/W E = 1, delay for 1 s or more E=0 Data out Disabling Addr, data, R/W E = 1.

18

3.1 Parallel Encoder

3.1 Parallel Encoder

n

n n n

n n

Dng ghp ni, o lng dch chuyn c hc: chiu di, vn tc, (c thng v quay), gia tc, nh v, robot Cng ngh vt liu t - nam chm vnh cu hoc quang hng ngoi/laser phn ly cao: upto 224 , chu shock,.. Tc upto 10k rpm, mmen cm downto 10-3Nm Output: cc xung lch nhau 900 (incremental), n bits (absolute) Tn hiu ra TTL hoc vi sai (truyn i xa) Manufacturers: Tamagawa Seiki, Hewlett-Packard, Epson...

19

3.1 Parallel Encoder

3.2 Serial in/out - Principle

n n

n n

Thng tin trong H VXL/My tnh: byte, word (//) Khi truyn i xa : serialize - byte => bit stream => ln ng truyn=> bit stream => byte (deserialize): gim thit b thu pht v ng truyn => Gim chi chi ph, kch thc vs tc chm M hnh di:

Central System

UART/ SIO

Modem

Coupler/ TransReceive

Trans Line

20

3.2 Serial in/out - Principle

Serial ports: n Nhim v/ chc nng n Vo ra ni tip: bin i byte => dng bit [thm start/ stop/ parity] gi ln ng truyn; dng bit => byte, loi cc bit khng mang tin, kim tra li thu. n Ghp ni vi h trung tm: cc bus/tn hiu addr, data, control bng cc phng php polling, Interrupt hoc DMA (t) n Ghp ni vi ng truyn [via modem]: TxD, RxD n Ghp ni modem: qua cc tn hiu bt tay /RTS, /CTS, /DSR, /DTR, /CD, /RI (low active signals) n V d: UART 8250, 16450, 16550A (Intel, NS...), ACIA 6850 Motorola, USART 8251 - Intel

3.2 Serial in/out - Principle

Modem: n L thit b bin i bit (0/1) thnh tn hiu vt l,ph hp vi mi trng truyn xa (iu ch Modulation) v ngc li (gii iu chDemoulation) n V d: Converter/ driver:
n n n n n

Maxim 232/ ICL 232 (232 modem): TTL <=> EIA 232, Single end, so vi Gnd: -3V .. -15 V <=> '1' +3V .. +15 V <=> '0 n gin, 100feet @ 9600 bps, d b nhiu Thng dng ghp ni cc thit b thng minh, gn: my th nghim, my o lng, Switching system, PLC,

21

3.2 Serial in/out - Principle

n

Max 485/ SN 75 116 TI ... (485/422 modem): Vi sai - Differential, so in p gia 2 dy tn hiu vi nhau. Mi tn hiu gm 2 dy a v b 7576/75176/75116
n n n n

[V(a) - V(b)] > 100 mV..5V => '1' [V(a) - V(b)] < -100 mV.. 5V => '0' 5000feet @ 1Mbps, thc t c th ln ti vi km, gim tc Thng dng trong cng nghip

Current Sourcer Ngun dng in: 0 v 20 mA [hoc 20 v 60 mA]

n n n

Chu nhiu tt Truyn i xa, ty thuc vo R ca dy dn Thng c cch ly quang hc

3.2 Serial in/out - Principle

n

RS 485 Bus

22

3.2 Serial in/out - Principle

n n n

ASK: Amplitude Shift Keying FSK: Frequency Shift Keying PSK: Phase Shift Keying

3.2 Serial in/out - Principle

n n

Truyn tin ng b v khng ng b Thng tin thng c ng gi thnh cc gi tin - package. => packets ng b:
n

Trong 1 packet: byte - byte, bit - bit, khng c du hiu phn cch. Tc truyn do sender: clock (cng vi data) hoc xut hin ln u ti u gi tin (sync. character). Tc cao, kh, t l bit khng mang tin nh, truyn gn LAN

23

3.2 Serial in/out - Principle

n

Truyn tin khng ng b: Asynchronous Comm.

n n

n n n

Mi k t/byte u c 1 sn/xung ng b (start). Clock ca pha thu v pht c th lch nhau khong: 3-6% V d: 10 bit format 8, n, 1; T: time of frame; t: time of bit, T: thi gian lch gia Tpht v Tthu. T < 1/2 t (5%). C khong trng ga 2 byte/k t data, 1 PE, 2 stop

3.2 Serial in/out - Principle

n

Truyn tin khng ng b: Asynchronous Comm.

n

n n

T l cc bit khng mang tin ln (start, stop, parity,), ln n 33% (v d: : format 1 start, 8 data, 1PE, 2 stop) n gin, d lp trinh, d ghp ni c bit c chp nhn rng ri: Thit b ngoi vi thng minh, o lng iu khin, modem,

24

3.2 Serial in/out - Principle

n

Truyn tin khng ng b: Asynchronous Comm.

Talker

Litsener

Simplex

S1

S2

Half duplex

S1

S2

[Full] duplex

3.2 Serial in/out - Principle

n

Truyn tin khng ng b: Asynchronous Comm.

25

3.2 Serial in/out - Principle

n

Truyn tin khng ng b: Asynchronous Comm.

Bi tp
1. Thit k mch iu khin 6 x LED 7 on 2. Thit k mch iu khin 4 LED ma trn 8x8 3. o khong dch chuyn, vn tc (encoder)

26

Chng 4: Analog Interface

n n n n

Analog Signal Interface Overview Analog Electronics - Conditioner Digital to Analog Converters Analog to Digital Converters

4.1 Analog Signal Interface Overview

n

L mt hm ca 1 (hoc nhiu) bin c lp, i lng vt l theo thi gian: nh ting ni, nhit ,theo thi gian: A = f(t, h) Xut hin lin tc trong khong thi gian t0 => t1 Gi tr bin thin lin tc trong khong bin t A0 => A1, c th a tr.

A A1

A0 0 t0 t1 t

4.1 Analog Signal Interface Overview

4.1 Analog Signal Interface Overview

n n

Trong thc t: Ri rc ha Trong My tnh s, thng tin thu v:

n n

Ri rc ha v thi gian Ri rc ha v gi tr

=> my tnh thu thp, cn phi ri rc ha cc tn hiu v thi gian v gi tr, dng thit b chuyn i ADC to ra cc tn hiu s, :
n n n

X l, ct vo kho s liu Truyn i xa Ti to li hay tng hp tn hiu: Dng thit b DAC to li cc tn hiu analog

4.1 Analog Signal Interface Overview

i tng vt l, cng ngh

. . . . . .

ADC CPU, Mem DAC

Storage

4.1 Analog Signal Interface Overview

4.1 Analog Signal Interface Overview

n

Process:
n

L cc qu trnh cng ngh nh: dy chuyn lm giy; phi-trn-nghin-nung => sn xut cement; dy chuyn luyn-nung-cn thp; sn xut-trn phn bn NPK, cc nh my in, L vt liu/thit b dng chuyn i cc i lng vt l khng in t (T, Ph,) thnh tn hiu in (u, I, R, f) Vt liu: do c tnh t nhin ca vt cht v d Pt100, cp nhit in, Thit b: C s gia cng, ch tc v d LM35, V tn hiu t Sensors rt nh, c th c nhiu v phi tuyn => c mch in t analog x l tn hiu: khuch i, lc nhiu, b phi tuyn, cho ph hp.

Sensors:
n n n

Conditioners:
n

4.1 Analog Signal Interface Overview

n n n n n n n

MUX: analog multiplexer Trch mu v gi - Sample & Hold ADC: analog to digital convertor: Central system: h nhng/MT: DAC: digital to analog convertor Mch in t analog Actuators: C cu chp hnh

4.2 Analog Electronics - Conditioner

n

n n n n n

Operational Amplifiers - OpAmps khuch i thut ton to cc b conditioners chun ha tn hiu Analog Switches & Analog Multiplexers Reference Voltage Sourcers ngun p chun Sample & Hold Trch mu v gi Converssion Errors Sai s chuyn i

4.2 Analog Electronics - OPAMP

n n

L vi mch khuch i, x l tn hiu t 0Hz Tn hiu gm:

n n n n n

2 chn tn hiu Inv.Inp v Non Inv.Inp Chn output Ngun cp: +Vcc, -Vcc (GND) Chnh offset C thm chn ni t b tn s

4.2 Analog Electronics - OPAMP

n n

X l tn hiu DC (0Hx up) H s khuch i ln, t kiloMegaand even more Tr vo ln vi K n 1012, tr ra nh, tt cho cc mch ghp ni analog, phi hp tr khng.

E1 Rin r1

E2 LOAD r2

4.2 Analog Electronics - OPAMP

n

Comparator

4.2 Analog Electronics - OPAMP

n

NON Inverting Amp

4.2 Analog Electronics - OPAMP

n

Inverting Amp

4.2 Analog Electronics - OPAMP

n

Adder (Mixer)

4.2 Analog Electronics - OPAMP

n

Differential

4.2 Analog Electronics - OPAMP

n

Instrumentation

4.2 Analog Electronics - OPAMP

n

Integrator

4.2 Analog Electronics - OPAMP

n

Differentiator

4.2 Analog Electronics - OPAMP

n

Follower

Uout = Uin

10

4.2 Analog Electronics - OPAMP

n

I/U converter

4.2 Analog Electronics - OPAMP

Mt s lu khi dng n H s khuch i chn ty thuc cc mch:
n

Mch k thng thng (o du v khng o du: vi ln n 10 ln), nu h s khuch i ln th nhiu tng => n nh v d dng kim sot. Mch khuch i vi sai (Differential apmlifier): t 10 => 50 ln, vo vi sai ra vi sai (Instrumentation Ampl): 30 => 100 ln Chn h s khuch i cng ln:
n n n

Bng thng gim by nhiu ln in tr vo gim by nhiu ln n nh ca mch gim: tri zero theo thi gian, nhit ,

11

4.3 Digital to Analog Converters

n

Digital to Analog: s => tn hiu dng in/in p, lin tc v thi gian, ri rc v gi tr. Phn loi:
n n n n

Cng ngh ch to S bit (reslution) Thi gian chuyn i 10s ns .. 100s ns, Cu trc: Built-in latched ghp ni trc tip vi bus/unlatched cn c out-port, bus 8 hay 16 bit Signed in p ra 2 du hoc unsnigned in p ra 1 du

4.3 Digital to Analog Converters

n

ng dng
n

Tng hp tn hiu
n n n

n Organ Pht tn hiu chun Voice chip

n n n

VGA/SVGA: RAM-DAC Ti to: m thanh s, MP3, CD, Ghp ni gia cc h thng (PC, PLC, ) => b iu khin analog, to ra cc Setpoint B nhn tn hiu analog 4 gc: nhn h s vi Uin thay cho Uref

12

4.3 Digital to Analog Converters

n

Nguyn l cu trc v hot ng

4.3 Digital to Analog Converters

R-2R Ladder DAC: n L phng php dng li in tr R-2R chia cy nh phn dng in n n gin n Chnh xc cao n Chuyn i nhanh n R n Trn th trng dng phng php ny

13

4.3 Digital to Analog Converters

R-2R Ladder DAC: n Mng R-2R ni kiu cy nh phn n Khi bi = 0 or 1 => ki R or L, Non Inv.Inp of OpAmp grounded => Inv. Inp = #0V => ki lun ng xung t bt k bi = x

4.3 Digital to Analog Converters

R-2R Ladder DAC: n Nu mun thay i gi tr? n V d: Uref = 5,12V, n = 10 => Uout = ?

14

4.3 Digital to Analog Converters

R-2R Ladder DAC: To cc tn hiu c bn

4.3 Digital to Analog Converters

R-2R Ladder DAC: Sng iu ch

15

4.3 Digital to Analog Converters

R-2R Ladder DAC, tham kho n Tra cu cc vi mch DAC: (pdf files) n www.national.com/product/interface/ad-da
n n n n

DAC0808 - single pole, 8 bit, 100ns DAC0800 - signed voltage output, 8 bit, 100ns DAC0832 - latched 8 bit dac - bus interface directly, DAC1210 - latched 12 bit dac 8/16 bit bus interface directly, 200ns

4.3 Digital to Analog Converters

R-2R Ladder DAC

16

4.3 Digital to Analog Converters

R-2R Ladder DAC

4.3 Analog to Digital Convertors

n

L thit b c hai chc nng (lng t ha):

n n

Ri rc ha tn hiu v thi gian Ri rc ha tn hiu v bin Theo tng ng dng: ADC x l tn hiu v o Chuyn i gin tip: u(t) => time (i lng trung gian) => code Chuyn i trc tip: u(t) => code Chuyn i phi tuyn: CODE (TP3057 Mitel hay AC97 Intel)

Phn loi:
n n n n

17

4.3 Analog to Digital Convertors

n

Chuyn i gin tip: Tch phn hai sn dc

n n n

u(t) => Time Interval/f/T => code Chm, r tin ($s), phn ly v chnh xc cao Dng trong o lng, thu thp s liu trong cng nghip khng cn nhanh, loi c nhiu Nhanh, phn ly thp hn [t tin], dng thu thp v x l tn hiu bin thin nhanh Chuyn i kiu xp x lin tip: 10k 10MSps Chuyn i song song: 10M 500 MSps

Chuyn i trc tip: u(t) => code

n

n n

4.3 Analog to Digital Convertors

n

Chuyn i gin tip: Tch phn hai sn dc

n n n

u(t) => Time Interval/f/T => code Chm, r tin ($s), phn ly v chnh xc cao Dng trong o lng, thu thp s liu trong cng nghip khng cn nhanh, loi c nhiu Nhanh, phn ly thp hn [t tin], dng thu thp v x l tn hiu bin thin nhanh Chuyn i kiu xp x lin tip: 10k 10MSps Chuyn i song song: 10M 500 MSps

Chuyn i trc tip: u(t) => code

n

n n

18

4.3 Analog to Digital Convertors

n

nh l ly mu Shannon - Kochennicov:
Tn hiu u(t) lin tc, trong n c cha thnh phn fmax, (nng lng ca tn hiu fmax = 0) th c th khi phc li tn hiu khng b sai t nhng gi tr gin on, vi iu kin:

n n

fSAMPLE >= 2fMAX nh l ny c tnh php l k s hiu s mu ti thiu bao nhiu l , khng qu dy => lng ph (tc ADC, thi gian x l, b nh); ly tha th s b sai

4.3 Analog to Digital Convertors

n

Dual Slope Integration ADC:

19

4.3 Analog to Digital Convertors

n

Successive Approximation ADC:

4.3 Analog to Digital Convertors

n n

Successive Approximation ADC, ICs: ICL 7107

n n n

In: -2V..2V, Out: -1999 => 1999, 4.000 counts <=> 12 bit, LED 7 Seg drive directly w current soursers for display Converssion time: 20..40ms Inp: -0.2V +02.V ho.c -2V..+2V, 40.000 count > 15bit, Out: -19999 => +19999, 400 ms converssion time De-Multiplexed Out BCD for 5 digits of 7 Seg, scanned Inp: -2V..+2V, Out: 12 bin + pole, 8/16 bit interface to CS

ICL 7135
n

ICL 7109, w REF & Clock

n

20

4.3 Analog to Digital Convertors

n

Interfacing to the ICL - 7135 ADC:

4.3 Analog to Digital Convertors

n

Successive Approximation ADC:

21

Bi tp
1. Vit chng trnh to cc tn hiu c bn (vung, rng ca, sin, tam gic,) 2. Gi lp DAC bng phn mm. 3. Thit k mch o nhit 4.

22

Chng 6: Bn phm

n n

Keypad Keyboard

6.1 Keypad bn phm 4x4

S901 K0 K4 S911 K5 S921 K6 S931 K7

S902 K1

S903 K2

S904 K3

S912

S913

S914

S922

S923

S924

S932

S933

S934

6.1 Keypad bn phm 4x4

n

c bn phm
Qut vng? n S dng ngt?
n

Chng rung
Kim tra thi gian ca bit trng thi (0 or 1) di n Dng t lc nhiu u vo
n

6.1 Keypad bn phm 4x4

6.1 Keypad bn phm 4x4

#define keypad_out PORTA #define keypad_in PINA flash char row[4] = {0xEF, 0xDF, 0xBF, 0x7F}; DDRA = 0xF0; for(i=0; i<4; i++) { keypad_out = row[i]; key = keypad_in & 0x0F; if(key!=0x0F) break; } if(i<4) key *= (i+1); else key = 0;

6.1 Keypad bn phm 4x4

6.1 Keypad Resistor matrix & ADC

If the key "5" is pressed, a voltage divider gets active: * 1 k + 820 = 1,82k to ground, * 3,3 k + 680 + 180 = 4,16k to plus. At an operating voltage of 5 Volt a divided voltage of: 5 * 1,82 / (1,82 + 4,16) = 1,522 Volt

6.2 Keyboard PC Keyboard

AT keyboard gom mot ma tran ln cac phm, tat ca c giam sat bi mot bo x ly on-board. Bo x ly khac biet nhau t ban phm nay en ban phm khac( chip thong dung gom 8048, 8049, 6868 va 6805) nhng tat chung c ban lam giong mot viec : Giam sat nhng phm c nhan / tha va gi d lieu tng xng ti may chu. Bo x ly nay cham soc tat ca d lieu ra va em bat c d lieu nao vao bo em 16-byte cua no neu can. Tat ca viec giao tiep gia may chu va ban phm dung PS/2 protocol.

6.2 Keyboard PC Keyboard

6.2 Keyboard PC Keyboard

n n

The keyboard sends data to the host in 11-bit words Contain a 0 start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a 1 stop bit. The keyboard generates 11 clock transitions (at around 20 - 30KHz) when the data is sent, and data is valid on the falling edge of the clock.

6.2 Keyboard PC Keyboard

Keyboard to Host

Host to Keyboard