Bi 5.

1 - Giao tip UART ch Multi-Processor

I. Ch Multi-Processor trong AVR UART.
AVR h tr mt kh nng giao tip UART ch a x l (Multiprocessor) hay Master-Slaves. iu u tin bn cn bit l ch ny khng phi l chun ca UART m ch c bit trn cc chip AVR (v c th trn mt s chip khc ca Atmel). Bit MPCM (bit 0) trong thanh ghi UCSRA l nhn t quan trng nht quyt nh ch hot ng ny. Cu hnh mng MasterSlave dng UART c tm tt nh sau: - Trn mng ny ch c 1 Master v c th c nhiu Slaves, cc ng TxD v RxD ca cc Slaves c ni chung vi nhau (ni song song). Cc Slaves v Master c ni vi nhau theo kiu bt cho, TxD chung ca Slaves ni vi RxD ca Master v ngc li. Mi Slave mang 1 a ch ring do ngi dng gn, c bit c th c nhiu Slave trng a ch vn khng nh hng n hot ng ca mng. - Cc Slaves v Master phi c ci t khung truyn v baudrate nh nhau (cng nh truyn thng UART thng thng). Khung truyn trong ch Master-Slaves c th 5, 6, 7,8 hay 9 bit nhng thng thng khung 9 bit c chn. Bi ny cng hng dn da trn khung 9 bit. Trong khung truyn 9 bit, 8 bit u tin c cha trong thanh ghi d liu UDR nh thng thng v bit th cao nht l bit TXB8 trong thanh ghi USCRB (trng hp pht) hay bit RXB8 trong thanh ghi UCSRB (trng hp thu). - Bit MPCM (bit 0) trong thanh ghi UCSRA cho php mt chip lm vic ch Master-Slave. Tuy nhin bit ny ch c tc dng chip Slaves, mt chip lm vic nh mt Slave (ch lnh t Master) th bit MPCM ca chip ny phi c set ln 1. Bit MPCM ca Master khng cn set. C ch lm vic ca ch Master-Slaves c gii thch nh sau: lc u, cc bit MPCM trn tt c cc Slaves u c set ln 1, ngt nhn d liu RXCIE ca cc Slaves c kch hot v chng ang ch ch lnh t Master. Khi chip Master mun thc hin mt cuc gi vi mt Slave no , n s pht ra mt gi a ch bao gm 8 bits cha a ch ca Slave cn gi v bit cao nht (TXB8) lun bng 1 (xem hnh 1).

Hnh 1. Gi a ch. Khi tt c 9 bit c cc Slaves nhn, bit cao nht s c Slaves cha trong bit RXB8. Nu bit ny bng 1 cc Slaves bit rng y l gi a ch, ngt RXCIE s xy ra trn tt c cc Slaves. Qu trnh ny c chip thc hin mt cch hon ton t ng. Trong trnh phc v ngt RXCIE (SIG_UART_RECV) ngi lp trnh s thc hin so snh gi tr 8 bits a ch nhn v vi a ch ca tng Slave. Nu mt Slave nhn thy a ch m Master gi khp vi a ch ca n, ngi lp trnh cn reset bit MPCM v 0 tch Slave ny ra khi ch ch (ch a ch). Tip theo Master s gi lin tip cc gi d liu trn ng truyn. Khc vi gi a ch, bit cao nht (TXB8) trong gi d liu bng 0 ch khng bng 1. Trn chip Master, ngi lp trnh cn vit 2 on chng trnh pht gi a ch v gi d liu ring bit. i vi cc Slaves, do bit cao nht nhn v RXB8=0, ngt RXCIE ch duy nht xy ra trn Slave c bit MPCM=0. Nh th, tt c cc Slaves khc s b qua gi ny (ngt RXCIE khng xy ra, khng nh hng n cc vic khc) ch duy nht Slave c a ch trng trc nhn d liu. Mt ch rt quan trng l sau khi byte d liu cui cng c nhn, Slave (chip c chn) phi set li bit MPCM ln 1 (do ngi lp trnh thc hin) a Slave tr li trng thi ch cc cuc gi tip theo. Nh vy, bng cch no Slave phi bit trc c s lng bytes d liu m Master mun gi kp thi set bit MPCM ln 1 sau byte cui. C mt s cch bit trc s lng bytes m Master s gi nh tha thun trc s bytes c nh cho mi cuc gi; hoc n gin Master dng byte d liu u tin (sau byte a ch) bo s lng bytes s gi tip theo; hoc hay hn c th ghp thng s ch lng bytes cn truyn vo gi a ch nu nh khng c qu nhiu Slaves trn mng v s lng bytes truyn cng khng qu ln. Nhng d cch no i na, cn c s tha thun khi lp trnh cho Master v Slave. C mt du hiu khc c th c dng phn bit gia gi d liu v gi a ch l trng thi bit RXB8, bng vic kim tra trng thi bit ny chng ta s bit c gi no l d liu (RXB8=0) v gi no l a ch (RXB8=1). Tuy nhin cch ny khng nhn bit c byte d liu cui cng c gi v vy khng c s dng set bit MPCM ln 1.

II. S dng Multi-Processor.

Trong v d bi ny ti dng phng php n gin l tha thun trc gia Master v Slave s lng bytes trong mt ln truyn, c th chng ta s thit lp mt mng Master-Slaves vi 1 Master v 2 Slaves. Cc Slave c a ch ln lt l 1 v 2, chng ta dng 2 chn PC0 v PC1 set a ch cho Slaves (vic ny gip chng ta c th s dng 1 chng trnh chung cho 2 Slaves). Master ch n gin gi n mi Slave 1 gi a ch v 2 bytes d liu. Cc Slaves s hin th 2 bytes d liu ln 2 dng ca LCD. Mch in m phng v d trnh by trong hnh 2.

Hnh 2. V d mng Master-Slaves dng UART. Chng ta cn vit 2 on chng trnh ring cho Master v Slaves. on chng trnh cho Master c trnh by trong List1. List 1. Chng trnh cho Master.

Vi chip Master, nh trnh by chng ta cn vit ring 2 on chng trnh con phc v pht gi d liu v gi a ch. Trong list 1, hai on chng trnh ny c tn uart_char_tx v uart_address_tx nm t dng 38 n 48. y ch on code pht uart thng thng (xem bi AVR5 Giao tip UART) cng thm vi vic set v reset bit TXB8. Trong on chng trnh pht gi d liu, bit TXB8 c reset v 0 bng cu lnh UCSRB &= ~(1<<TXB8); trong khi on chng trnh pht gi a ch bit ny c set ln 1, UCSRB |= (1<<TXB8); (ch bit TXB8 nm trong thanh ghi USCRB). Phn ci t cho UART (t dng 14 n dng 20) bn c hy xem li bi AVR5. Ch n cc dng t 24 n 30. y l phn gi a ch v d liu n cc Slave. Trc khi mun gi d liu n Slave1, chng ta cn gi chng trnh con pht a ch uart_address_tx(1) nh trong dng 24, tip theo l pht 2 bytes d liu theo cch thng thng (v d byte1=200, byte2=123). Tng t chng ta c th pht2 bytes d liu n Slave2 theo cch ny (dng 28, 29 v 30).

List

2.

Chng

trnh

cho

Slaves.

Do chng ta s dng TextLCD hin th kt qu nhn v t Master, cn include th vin myLCD.h (dng 6). Th vin stdio.h cha cc hm x l chui k t gip ch cho vic hin th LCD (chng ta s dng hm sprintf) nn cng cn c include vo (dng 5). Bin my_address cha a ch ca Slave, u_data cha gi tr nhn v t UART, bin ind l ch s ch s bytes nhn v. Gi d liu nhn v cha trong mng alldata[3], mng dis[5] l mng k t tm thi hin th ln LCD (xem cc khai bo bin trong 2 dng 14. 15). a ch Slave do 2 chn PC0 v PC1 quyt nh, vic c a ch ny c thc hin vi dng lnh my_address=PINC & 0x03. Bng cch chn a ch ng nh th chng ta khng cn vit ring chng trnh cho mi Slave. Cc dng lnh t 24 n 30 ci t thng s cho UART, ch cn cho php ngt RXCIE xy ra dng 29 v 30). Phn ni dung quan trng nht c vit trong trnh phc v ngt ISR(SIG_UART_RECV) (t dng 44 n 60). Khi mt ngt RXCIE vic u tin cn lm l c gi tr nhn v vo bin u_data (dng 45), nu y l byte u tin nhn v (tc ind=0, byte a ch) th chng ta cn so snh xem a ch c khp khng (dng 47). Nu ng l a ch ca Slave ny th cn reset bit MPCM v 0 sn sng nhn d liu (dng 48), tng bin ind ln 1. Nu byte nhn v khng phi l byte u tin m l byte d liu (bin ind khc 0) chng ta s gn byte nhn v vo mng alldata v tng bin ch s ind (cc dng t 52 n 54). V trong v d ny chng ta tha thun trc Master ch gi 2 bytes d liu n mi Slave nn khi bin ind bng 3, tc l nhn 2 bytes d liu chng ta cn set li bit MPCM kt thc qu trnh nhn, a Slave v li trng thi ch, ng thi tr bin ch s ind v 0 (lm li t u) (xem cc dng 55 n 57). Khi m phng, bn hy np chng trnh trong List 1 cho chip Master v list2 cho 2 Slaves. Cn set xung clock 8MHz. Nu bn thc hin ng kt qu s hin th nh trong hnh 1.