DesignWithFPGA K51

Thit k h thng s
dng vi mch logic kh

trnh
Digital System Design with
Programmable Logic Devices

Ging vin: TS. Phm Ngc Nam
DHBK 2007
2
About your lecturer
B mn k thut in t tin hc, HBK H ni
Office: C9-401
Email: pnnam-fet@mail.hut.edu.vn
Research:
FPGA, embedded systems
Tr tu nhn to
Embedded system and Reconfigurable computing Lab: 618 th vin
in t
Education:
K37 in t-HBK H ni (1997)
Master v tr tu nhn to 1999, i hc K.U. Leuven, vng quc B
ti: Nhn dng ch vit tay
Tin s k thut chuyn ngnh in t-tin hc, 9/ 2004, i hc K.U.
Leuven, Vng Quc B
ti: qun l cht lng dch v trong cc ng dng a phng tin tin
tin

DHBK 2007
3
Mc ch ca mn hc
Nm c cng ngh IC kh trnh PLD
Nm c quy trnh thit k h thng s vi PLD
C kh nng thit k h thng s dng ngn ng
VHDL
C kh nng s dng cng c thit k ca Xilinx v
Altera
DHBK 2007
4
Ti liu tham kho:
Slides
E-books
VHDL programming by Example 4
th
edition by Douglas L. Perry
Website
www.xilinx.com
www.Altera.com
Course email: thietkevoifpga@gmail.com password: hut123456
nh gi
iu kin d thi: hon thnh bi tp ln v ln lp y
Kim tra gia k (30%)
Bi tp ln (30 %) (lm theo nhm 4-5 sinh vin)
Thi cui k (40 %)
DHBK 2007
5
Ni dung mn hc
1. Gii thiu chung v cng ngh IC kh trnh
2. Thit k dng IC kh trnh ca Xilinx v Altera
3. Thit k s (nhc li)
4. Ngn ng m t phn cng VHDL

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6
Chng 1. Gii thiu chung v cng
ngh IC kh trnh PLD
1.1 Cc bc thit k VLSI
1.2 Cc cng ngh dng trong thit k
1.3 Cng ngh IC kh trnh
1.4 ng dng ca cng ngh IC kh trnh

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V d: Thit k b chy a DVD
DHBK 2007
8
System Specification
Architectural Design
Logic Design
Circuit Design
Physical Design
Functional Design Fabrication
Packaging
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System Specification Xc nh kch thc, tc ,
cng sut v cc chc nng ca h thng
Architectural Design Xc nh kin trc ca h thng:
v d: RISC/CISC, s lng ALU, kch thc b nh
cache. Vic xc nh kin trc s gip cho vic c
lng tc x l ca h thng, kch thc chip, cng
sut tiu th
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Functional Design Xc nh cc khi chc nng chnh
v kt ni gia cc khi. Cha cn xc nh chi tit
cch thc thc hin cc khi ny.

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Logic Design Thit k logic, v d: thit k mch
logic t hp, logic dy, ALU, khi iu khin. Kt
qu ca bc thit k ny l bn m t RTL (Register
Transfer Level). RTL c biu din bng ngn ng m
t phn cng HDL (Hardware Description Language),
e.g., VHDL, Verilog.

X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)
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Circuit Design Thit k mch bao gm cc cng logic,
transistors v cc kt ni. Kt qu thu c t bc
thit k ny l mt netlist.

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Net list:
net1: top.in1 i1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out

Component list:
top: in1=net1 n1=topin1 n2=topin2
n3=botin1 out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1 xin2=topin2
xin3=botin1 B=net2 out=net3
i2: in=net3 out=outnet

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top
i1 xxx i2
Component hierarchy
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Physical Design Chuyn t netlist sang dng biu din
hnh hc. Cch biu din hnh hc ny c gi l
layout.

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Fabrication Bao gm cc qu trnh nh quang khc,
nh bng, khuych tn ch to ra chip (IC).
Packaging Sp xp cc IC trn mt board mch in
PCB (Printed Circuit Board) hoc trn mt module a
chp MCM (Multi-Chip Module)

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System Specification
Architectural
Specification
RTL in HDL
Netlist
Layout
Timing & relationship
between functional units
Chips
Packaged and
tested chips
Architectural
Design
Functional
Design
Logic
Design
Physical
Design
Fabrication
Packaging
Circuit Design
or
Logic Synthesis
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18
Full-Custom ASICs (Application specific IC)
Cc khi logic (logic cells) v cc lp mt n khng c thit k sn m
do ngi thit k thit k
Semicustom ASICs
Cc khi logic ( logic cells) c thit k sn (c nh ngha trong th
vin cell) v cc lp mt n c thit k bi ngi thit k
2 loi:
Standard-cell based and Gate-array-based ASICs
Cc linh kin logic kh trnh (Programmable logic devices)
Tt c cc khi logic c thit k sn v khng cn phi thit k lp
mt n no
Types: PAL, PLA, CPLD, FPGA

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Full-Custom ASIC
Full-Custom ASICs
i vi mi mt chip ASIC, ngi thit k phi thit k ton
b cc khi logic, mch in, layout
Full-custom ICs l loi t nht ch to v thit k
Thi gian ch to 1 IC (khng k thi gian thit k) l 8 tun
Dng khi:
Khng c cc khi logic c sn trong th vin
Cc khi logic hin c khng nhanh
Cc khi logic hin c c kch thc ln
Cc khi logic hin c tiu th cng sut ln
Chp ASIC cn thit k qu c bit dn ti nhiu mch phi c
thit k mt cch tu bin

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Full-Custom ASIC
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Cell-based ASIC
Cell-Based ASIC (CBIC) s dng cc khi logic c
thit k sn (cng AND, OR gates, multiplexers, flip-
flops, ...)
Vng khi logic chun bao gm cc hng khi logic chun
Vng khi logic chun c th kt hp vi cc khi khc ln
hn cng c thit k sn nh vi iu khin, vi x l, cc
khi ny c gi l megacell

DHBK 2007
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Cell-based ASIC
c im:
Cc khi tu bin c th c nhng vo chip ASIC. Ngi
thit k ASIC ch phi nh ngha v tr t cc khi logic
chun v kt ni gia cc khi
Cc khi chun c th c t bt k ch no trn phin
silicon nn tt c cc lp mt n ca CBIC c th c t do
thit k
Thi gian ch to l 8 tun
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Gate-Array-Based ASICs
Bao gm mt mng 2 chiu cc cng logic ging ht
nhau (v d cc cng NAND) c xc nh sn trn
phin silic
Cc cng logic c ni vi nhau bi cc lp kt ni.
Vic kt ni gia cc cng c thc hin bi mt n
do ngi thit k to ra.
Thi gian ch to t vi ngy n 2 tun
Gi thnh r hn cc loi ASIC khc

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Realisation as AND-OR:
F
1
=xy+xyz+xyz
Realisation as OR-AND:
F
1
=((x+y) (x+y+z)
(x+y+z))
x y z
F
1

x y z
F
1

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Programmable logic array
PLA
And
plane
And
plane
Or
plane
Input
Output
Programmable
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Programmable logic array
PLA
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Programmable Array Logic
PAL
And
plane
And
plane
Or
plane
Input
Output
Programmable
Fixed
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Programmable Array Logic
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Complex Programmable Logic Devices
CPLD
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Complex Programmable Logic Devices
Cc cng ngh lp trnh
PROM: Lp trnh 1 ln
EPROM, flash, EEPROM: lp trnh nhiu ln

Non-volatile
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V d: PROM
4
2
-
t
o
-
4

D
e
c
o
d
e
r

2
MSB
Address
2-to-4 Mux
2
LSB
V
cc
V
cc
V
cc
V
cc

Data
Fuse
After manufacturing
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V d: PROM
4
2
-
t
o
-
4

D
e
c
o
d
e
r

2
MSB
Address
2-to-4 Mux
2
LSB
V
cc
V
cc
V
cc
V
cc

Data
After programming
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33
Field-programmable Gate Array
FPGA: XC40xx
CLB CLB
CLB CLB
CLB
CLB
Long lines
SM SM SM SM
SM SM SM SM
SM SM SM SM
Routing via switching matrices
I/O I/O I/O
I
/
O

I
/
O

I
/
O

I/O
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34
Cu to ca mt CLB (Configurable Logic Block)
16x1
LUT:
Bool-function
of 4
variables
16x1
LUT:
Bool-function
of 4
variables
FF
G
G
GQ
FF
F
F
FQ
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FPGA: Switching Matrix SM
Pass
TOR
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Cng ngh lp trnh:
SRAM-based:
Volatile
Reprogrammble
Antifuse
Non-volatile
Programmed only-one
IP security

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Hng cung cp FPGA hng u th gii
Cng ty Xilinx: http://www.xilinx.com/
Cng ty Altera: http://www.altera.com/
Cng ty Lattice Semiconductor: http://www.latticesemi.com/
Cng ty Actel: http://www.actel.com/
Cng ty Crypress: http://www.cypress.com/
Cng ty Atmel: http://www.atmel.com/
Cng ty QuickLogic: http://www.quicklogic.com/
DHBK 2007
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u im
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u im
FPGA vs Custom ASIC
FPGAs are more flexible
FPGAs are more cost effective for small quantities
ASICs have higher densities
FPGA vs Parallel Computer
FPGAs are more cost effective
FPGAs are smaller
Parallel Computers are easier to program

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Volume
Total cost
ASIC .13
FPGA .13
FPGA .09
ASIC .09
ASIC Design
Cost is much
higher
(and increasing)!!
For each technology advance,
crossover volume moves higher
1.3 FPGA vs. ASIC Cost
ASIC: High volumes needed to recover design cost
ASIC cost/part
is lower
Courtesy: Richard Sevcik, Xilinx
DHBK 2007
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1.4 ng dng ca cng ngh IC kh
trnh
Aerospace & Defense
Automotive
Consumer
Digital Video Technologies
Industrial/Scientific & Medical
Test & Measurement
Wired Communications
Wireless Communications
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trnh

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trnh
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trnh
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trnh
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trnh
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trnh
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trnh
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trnh
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trnh
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Chng 2: Thit k dng IC kh
trnh ca Xilinx v Altera

2.1 Cc h PLD ca Xilinx
2.2 Cu trc PLD ca Xilinx
2.3 Cc bc thit k vi PLD ca Xilinx
2.4 Cc h PLD ca Altera
2.5 Cu trc PLD ca Altera
2.6 Cc bc thit k vi PLD ca Altera
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A Decade of Progress
200x More Logic
Plus memory,
P etc.
40x Faster
50x Lower Power
500x Lower Cost

CLB Capacity
Speed
Power per MHz
Price
Virtex &
Virtex-E
XC4000
100x
10x
1x
Spartan-2
1000x
Virtex-II &
Virtex-II Pro
Virtex-4 XC4000 &
Spartan
Spartan-3
'91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04
Year
Courtesy: Richard Sevcik, Xilinx
DHBK 2007
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H Virtex:
Virtex-5
2006, 1 V, 65 nm
550 MHz, low power
330,000 logic cells, DSP, PowerPC
1200 I/O pins
Virtex-4:
2004, 1.2 V, 90nm
500 MHz, low power
200.000 logic cells, DSP, PowerPC
Thay th ASIC, ASSP
Virtex-II Pro /X
2002, 1.5 V, 130nm
400 MHz
3K to 99K logic cells + DSP, PowerPC

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H Virtex:
Virtex-II
2001, 1.5 V, 150nm
300 MHz
3K to 99K logic cells
Virtex /E
1998/1999, 2.5 /1.8 V, 220 / 180 nm
150/ 200 MHz
3K to 70K logic cells

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H Spartan:
Spartan-3A DSP/AN/A/E /L
2003, 1.5 V, 90nm
300 MHz
5M gates

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CPLD- H Coolrunner
CoolRunner-II
1.8V, 180 nm
303 MHz
32-512 macrocells
Ultra Low power
CoolRunner-XPLA3
3.3 V
200 MHz
32-512 macrocells
Low power

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CPLD- H XC9500
XC9500XV
2.5 V
250 MHz
36-288 macrocells
Low cost
XC9500XL
3.3 V
200 MHz
36-288 macrocells
Low cost
XC9500
5 V, 200 MHz
36-288 macrocells
Low cost

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All Xilinx FPGAs contain the same basic resources
Slices (grouped into CLBs)
Contain combinatorial logic and register resources
IOBs
Interface between the FPGA and the outside world
Programmable interconnect
Other resources
Memory
Multipliers
Global clock buffers
Boundary scan logic

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Slices and CLBs
Each Virtex
'
-II CLB
contains four slices
Local routing provides
feedback between slices in the
same CLB, and it provides
routing to neighboring CLBs
A switch matrix provides
access to general routing
resources
CIN
Switch
Matrix
BUFT
BUF T
COUT COUT
Slice S0
Slice S1
Local Routing
Slice S2
Slice S3
CIN
SHIFT
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Slice 0
LUT Carry
LUT Carry
D Q
CE
PRE
CLR
D
Q
CE
PRE
CLR
Simplified Slice Structure
Each slice has four outputs
Two registered outputs,
two non-registered outputs
Two BUFTs associated
with each CLB, accessible
by all 16 CLB outputs
Carry logic runs vertically,
up only
Two independent
carry chains per CLB
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Detailed Slice Structure
LUTs
MUXF5, MUXF6,
MUXF7, MUXF8
(only the F5 and
F6 MUX are shown
in this diagram)
Carry Logic
MULT_ANDs
Sequential Elements
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Combinatorial Logic
A
B
C
D
Z
Look-Up Tables
Combinatorial logic is stored in Look-Up
Tables (LUTs)
Also called Function Generators (FGs)
Capacity is limited by the number of inputs,
not by the complexity
Delay through the LUT is constant
A B C D Z
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
. . .
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
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Connecting Look-Up Tables
F
5

F
8

F
5

F
6

CLB
Slice S3
Slice S2
Slice S0
Slice S1
F
5

F
7

F
5

F
6

MUXF8 combines the two
MUXF7 outputs (from the CLB
above or below)
MUXF6 combines slices S2
and S3
MUXF7 combines the two
MUXF6 outputs
MUXF6 combines slices S0 and S1
MUXF5 combines LUTs in each slice
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D
CE
PRE
CLR
Q
FDCPE
D
CE
S
R
Q
FDRSE
D
CE
PRE
CLR
Q
LDCPE
G
_1
Flexible Sequential Elements
Either flip-flops or latches
Two in each slice; eight in each CLB
Inputs come from LUTs or from an
independent CLB input
Separate set and reset controls
Can be synchronous or
asynchronous
All controls are shared within a slice
Control signals can be inverted
locally within a slice
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Shift Register LUT (SRL16CE)
Dynamically addressable serial shift
registers
Maximum delay of 16 clock cycles
per LUT (128 per CLB)
Cascadable to other LUTs or
CLBs for longer shift registers
Dedicated connection from
Q15 to D input of the next
SRL16CE
Shift register length can
be changed asynchronously
by toggling address A
LUT
D Q
CE
D Q
CE
D Q
CE
D Q
CE
LUT
D
CE
CLK
A[3:0]
Q
Q15 (cascade out)
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IOB Element
Input path
Two DDR registers
Output path
Two DDR registers
Two 3-state enable
DDR registers
Separate clocks and
clock enables for I and O
Set and reset signals
are shared
Reg
Reg
DDR MUX
3-state
OCK1
OCK2
Reg
Reg
DDR MUX
Output
OCK1
OCK2
PAD
Reg
Reg
Input
ICK1
ICK2
IOB
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SelectIO Standard
Allows direct connections to external signals of varied
voltages and thresholds
Optimizes the speed/noise tradeoff
Saves having to place interface components onto your board
Differential signaling standards
LVDS, BLVDS, ULVDS
LDT
LVPECL
Single-ended I/O standards
LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
PCI-X at 133 MHz, PCI (3.3V at 33 MHz and 66 MHz)
GTL, GTLP
and more!
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Other Virtex-II Features
Distributed RAM and block RAM
Distributed RAM uses the CLB resources (1 LUT = 16 RAM
bits)
Block RAM is a dedicated resources on the device (18-kb
blocks)
Dedicated 18 x 18 multipliers next to block RAMs
Clock management resources
Sixteen dedicated global clock multiplexers
Digital Clock Managers (DCMs)
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Distributed SelectRAM Resources
Uses a LUT in a slice as memory
Synchronous write
Asynchronous read
Accompanying flip-flops
can be used to create
synchronous read
RAM and ROM are initialized
during
configuration
Data can be written to RAM
after configuration
Emulated dual-port RAM
One read/write port
One read-only port
RAM16X1S
O
D
WE
WCLK
A0
A1
A2
A3
LUT
RAM32X1S
O
D
WE
WCLK
A0
A1
A2
A3
A4
RAM16X1D
SPO
D
WE
WCLK
A0
A1
A2
A3
DPRA0 DPO
DPRA1
DPRA2
DPRA3
Slice
LUT
LUT
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Block SelectRAM Resources
Up to 3.5 Mb of RAM in 18-kb
blocks
Synchronous read and write
True dual-port memory
Each port has synchronous read
and write capability
Different clocks for each port
Supports initial values
Synchronous reset on output
latches
Supports parity bits
One parity bit per eight data bits
DIA
DIPA
ADDRA
WEA
ENA
SSRA
CLKA
DIB
DIPB
WEB
ADDRB
ENB
SSRB
DOA
CLKB
DOPA
DOPB
DOB
18-kb block SelectRAM memory
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Dedicated Multiplier Blocks
18-bit twos complement signed operation
Optimized to implement Multiply and Accumulate functions
Multipliers are physically located next to block SelectRAM
memory
18 x 18
Multiplier
Output
(36 bits)
Data_A
(18 bits)
Data_B
(18 bits)
4 x 4 signed
8 x 8 signed
12 x 12 signed
18 x 18 signed
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Global Clock Routing Resources
Sixteen dedicated global clock multiplexers
Eight on the top-center of the die, eight on the bottom-center
Driven by a clock input pad, a DCM, or local routing
Global clock multiplexers provide the following:
Traditional clock buffer (BUFG) function
Global clock enable capability (BUFGCE)
Glitch-free switching between clock signals (BUFGMUX)
Up to eight clock nets can be used in each clock region
of the device
Each device contains four or more clock regions
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Digital Clock Manager (DCM)
Up to twelve DCMs per device
Located on the top and bottom edges of the die
Driven by clock input pads
DCMs provide the following:
Delay-Locked Loop (DLL)
Digital Frequency Synthesizer (DFS)
Digital Phase Shifter (DPS)
Up to four outputs of each DCM can drive onto global
clock buffers
All DCM outputs can drive general routing
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CPLD/FPGA design flow
Design Flow
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Design Entry
Using schematic editor:
Works well with small designs: 5k to 10 k gates
Schematic can be compiled to HDL
Using HDL (Hardware Description Language)
VHDL, Verilog
Others: Abel
Works with large design: > 100 k gates
Using State Editor:
Mostly for controller
FSM can be compiled to HDL
Higher level design language
System C: C based
Ocapi-xl: C and C++ based

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Design Entry
Design tools:
Webpack ISE (min ph)
Thit k cho CPLD, FPGA
C cng c thit k dng schematic, ngn ng m t phn
cng, cng c tng hp, m phng v vt l
http://www.xilinx.com/ise/logic_design_prod/webpack.htm
ISE Foundation (khng min ph)
chc nng tng t nh Webpack
EDK and Platform studio
Dng thit k h thng nhng vi FPGA

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Schematic diagram: example
Language based
refinement:
VHDL editor
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VHDL: Example
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Design Synthesis
Synthesis process:
Check code syntax
Analyze the hierarchy of the design
Compile RTL to gate level
Create netlist of the design
Take into account the architecture of the target FPGA
Synthesis tools:
XST (Xilinx synthesis technology)
Generate a NGC file
LeonardoSpectrum from Mentor Graphics, Inc
Synplify and Synplify Pro from Synplicity Inc.

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Design Implementation
Translate:
Translate the design netlist and constraints into (Xilinx) primitives
Input: NGC file, Output: NGD file (Native Generic Database)
Map:
Map the primitives to the actual physic circuit of the device
Input: NGD file, Output: NCD file ( Native Circuit Description)
Place and Route (PAR):
Place the circuits on the CLB and find a good route to connect them
Input: NCD file, Output: NCD file

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Xilinx device programming
Create a bitstream to program the device
Input: NCD file, Output: bit file
Programming tools:
Download software + download cable

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Design verification
M phng chc nng vi behavioral simulation
M phng v thi gian vi timing simulation
Kim tra phn cng
Verification tools:
ModelSim
ChipScope Pro
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H Cyclone:
Cyclone III:
2007, 65 nm FPGA
Low power, low cost
Embedded memory, embedded multipliers

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H Cyclone:
Cyclone II:
90 nm FPGA
Low power, low cost
Embedded memory, embedded multipliers

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H Cyclone:
Cyclone:
2003, 0.13 um
Low power, low cost
Embedded memory
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H Stratix:
Stratix III:
2007, 65 nm
Low power, high performance, high density
Embedded memory, multipliers
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H Stratix:
Stratix II:
90 nm
high performance, high density
Embedded memory, multipliers, DSP
blocks
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H Stratix:
Stratix:
0.13-m
high performance, high density
Embedded memory, multipliers, DSP blocks
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H CPLD:
Max II:
Low cost, high performance
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Logic array block (LAB): 10 Logic elements(LE)
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Logic element (LE)
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Global clock and PLL
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IOE structure
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2.6 Cc bc thit k vi PLD ca
Altera

FPGA design flow
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Altera

CPLD design flow
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Altera

Software tools
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Chng 3. Thit k s
3.1 Cc mc thit k
3.2 Thit k mch s t hp
3.3 Thit k mch s tun t
3.4 Cu trc FSMD

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3.1 Cc mc thit k
Thit k dng cc cng logic ri rc (Gate level):
AND, OR, NAND, NOT, Flip Flops
Dng cho cc bi ton thit k n gin nh thit k b tng,
tng ca tch, b m
Kt qu: module
Thit k dng cc thanh ghi v cc module s (RTL:
register transfer level)
Thanh ghi dch, decoder, ALU, Mux, b cng, nhn, b
m
Dng cho cc bi ton thit k t trung bnh n phc tp nh
thit k vi x l, thit k cc b m ho v gii m m thanh,
hnh nh
Kt qu: vi mch (IC)

DHBK 2007
104
3.1 Cc mc thit k
Thit k h thng (system level design)
Vi x l, b nh, cc b m ho v gii m hnh nh, m
thanh s, cc b x l tn hiu s
Dng cho thit k cc h thng s phc tp nh my rt tin
t ng, cc ng dng a phng tin
Kt qu: PCB
Trong qu trnh thit k mt h thng s, cc mc trn
c th c s dng 1 n nhiu ln

DHBK 2007
105
Ba Karnaugh
Mc ch: dng ti thiu ho hm Boole thc hin
mch mt cch ti u
V du: F=xyz+xyz =xy(z+z) =xy

x y z
F=xyz+xyz
x y z
F
Ti thiu ho dng cch bin i hm boole rt phc tp v
khng c l thuyt no chng minh kt qu ti thiu ho l ti u
DHBK 2007
106
Ba Karnaugh
Ba Karnaugh cha cc thng tin tng t nh bng s
tht, cc st nhau ch khc nhau mt bin
x x
x
0 1
xy xy
xy xy
x
0
1
y
0 1
xyz xyz
xyz xyz
x
0
1
yz
00 01
xyz xyz
xyz xyz
11 10
x
y
z
xz (khng ph thuc y)
xyz xyz
xyz xyz
xz (khng ph thuc y)
xyz xyz
xy ( khng ph thuc z)
DHBK 2007
107
Ba Karnaugh
m
0
m
1

x
0 1
m
0
m
1

m
2
m
3

x
0
1
y
0 1
0 1
4 5
x
0
1
yz
00 01
3 2
7 6
11 10
x
y
z
DHBK 2007
108
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Ba Karnaugh
0 1
4 5
xy
00
01
zw
00 01
3 2
7 6
11 10
x
z
w
12 13
8 9
15 14
11 10
11
10
y
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0 1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
0
x y z w F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
1
DHBK 2007
109
Ba Karnaugh
1 0
0 1
xy
00
01
zw
00 01
0 0
1 0
11 10
x
z
w
0 1
1 0
1 0
0 1
11
10
y
Ti thiu ho
F=xyzw+xyzw+xyzw+xyzw+xyzw+xyzw+xyzw
F= yw
+xyw
+yzw
DHBK 2007
110
Ba Karnaugh
Thc hin F=xyzw+xyzw+xyzw+xyzw+xyzw+xyzw+xyzw
x y z w
F
DHBK 2007
111
Ba Karnaugh
Thc hin: F=yw+xyw+yzw
x y z w
F
DHBK 2007
112
Ba Karnaugh
0
xy
00
01
zw
00 01 11 10
1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
18 19 17 16
22 23 21 20
30 31 29 28
26 27 25 24
xy
11
10
10 11 01 00
00
01
11
10
x
y
z
w
x
z
w
v
y
F(v,x,y,z,w)
DHBK 2007
113
Ba Karnaugh
0
xy
00
01
zw
00 01 11 10
1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
18 19 17 16
22 23 21 20
30 31 29 28
26 27 25 24
xy
11
10
10 11 01 00
00
01
11
10
x
y
z
w
x
z
w
v
y
40 41 43 42
44 45 47 46
36 37 39 38
32 33 35 34
58 59 57 56
62 63 61 60
54 55 53 52
50 51 49 48
10
11
01
00
x
y
10
11
01
00
x
y
u
F=(u,v,x,y,z,w)
DHBK 2007
114
Gi tr khng xc nh (dont care)
Hm boole khng y
BCD7-segment
a
b
c
d
e
f
g
x y z w a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 x x x x x x x
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 x x x x x x x
1 0 1 1 x x x x x x x
1 1 0 0 x x x x x x x
1 1 0 1 x x x x x x x
1 1 1 0 x x x x x x x
1 1 1 1 x x x x x x x
DHBK 2007
115
Xy dng ba Karnaugh
1 0 1 1
0 1 1 1
x x x x
1 1 x x
1 1 1 1
1 0 1 0
x x x x
1 1 x x
1 1 1 0
1 1 1 1
x x x x
1 1 x x
1 0 1 1
0 1 0 1
x x x x
1 1 x x
1 0 0 1
0 0 0 1
x x x x
1 0 x x
1 0 0 0
1 1 0 1
x x x x
1 1 x x
0 0 1 1
1 1 0 1
x x x x
1 1 x x
x
x
y
y
z z z z
w w w w
a b c d
e f g
DHBK 2007
116
Ti thiu ho ba Karnaugh
1 0 1 1
0 1 1 1
x x x x
1 1 x x
x
y
z
w
a
yw
z
yw
x
a=yw+z+yw+x
DHBK 2007
117
1 1 1 1
1 0 1 0
x x x x
1 1 x x
z
w
b

yw
z
yw
x
a=yw+z+yw+x
zw
zw
b=y+zw+zw
y
DHBK 2007
118
1 1 1 0
1 1 1 1
x x x x
1 1 x x
z
w
c

yw
z
yw
x
a=yw+z+yw+x
y
zw
zw
b=y+zw+zw
z
w
y
c=z+w+y
DHBK 2007
119
1 0 1 1
0 1 0 1
x x x x
1 1 x x
z
w
d

yw
z
yw
x
a=yw+z+yw+x
y
zw
zw
b=y+zw+zw
z
w
y
c=z+w+y
yw
yz
yzw
zw
x
d=yw+yz+yzw+zw+x
DHBK 2007
120
1 0 0 1
0 0 0 1
x x x x
1 0 x x
x
y
e
z
yw
x
a=yw+z+yw+x
y
zw
zw
b=y+zw+zw
z
w
y
c=z+w+y
yz
yzw
zw
d=yw+yz+yzw+zw+x
yw yw
zw
e=yw+zw
DHBK 2007
121
1 0 0 0
1 1 0 1
x x x x
1 1 x x
f

z
yw
x
a=yw+z+yw+x
y
zw
zw
b=y+zw+zw
z
w
y
c=z+w+y
yz
yzw
zw
d=yw+yz+yzw+zw+x
e=yw+zw
zw
yz
yw
x
f=zw+yz+yw+x
yw
DHBK 2007
122
0 0 1 1
1 1 0 1
x x x x
1 1 x x
g

z
yw
x
a=yw+z+yw+x
y
zw
zw
b=y+zw+zw
z
w
y
c=z+w+y
yz
yzw
zw
d=yw+yz+yzw+zw+x
e=yw+zw
yz
yw
f=zw+yz+yw+x
yz
yz
yw
x
g=yz+yz+yw+x
yw
DHBK 2007
123
xyzw
a c b d e f g
DHBK 2007
124
Cc mch logic t hp c bn
Ripple-carry adders
Adder/subtractors
Multipliers
Logic units
Arithmetic-logic units
Decoders
Selectors
Buses
Magnitude comparators

DHBK 2007
125
Ripple-carry adders
B na tng (Half Adder):
x
i
y
i
c
i+1
s
i
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
0 0
0 1
x
i

y
i
c
i+1

0 1
1 0
x
i

y
i
s
i

x
i
y
i

c
i+1
s
i

HA
x
i
y
i

c
i+1

s
i

DHBK 2007
126
Ripple-carry adders
B tng y (Full Adder)
x
i
y
i
c
i
c
i+1
s
i
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
1
1 1 1 c
i

x
i

y
i

c
i+1

1 1
1 1 c
i

x
i

y
i

s
i

x
i

y
i

c
i

c
i+1
s
i

FA
x
i
y
i

c
i

c
i+1

s
i

DHBK 2007
127
Ripple-carry adders
4-bit ripple-carry adder
FA
x
0
y
0

c
0
=0 c
1

s
0

FA
x
1
y
1

c
2

s
1

FA
x
2
y
2

c
3

s
2

FA
x
3
y
3

c
4

s
3

DHBK 2007
128
Adder-subtractors
FA
x
0
y
0

c
0

c
1

f
0

FA
x
1
y
1

c
2

f
1

FA
x
2
y
2

c
3

f
2

FA
x
3
y
3

c
4

f
3

S
S Function Note
0 X+Y Addition
1 X-Y=X+Y*=X+Y+1 Subtraction
Adder/
subtractor
X Y
F
S
C
out

overflow
Ch dng cho s b 2
DHBK 2007
129
Multipliers
B nhn 1bit x 1bit C = B A
b
0

a
0

a
0
b
0

b
0
a
0
c
0
=a
0
.b
0
0 0 0
b
0
a
0
c
0
=a
0
.b
0
0 0 0
0 1 0
b
0
a
0
c
0
=a
0
.b
0
0 0 0
0 1 0
1 0 0
b
0
a
0
c
0
=a
0
.b
0
0 0 0
0 1 0
1 0 0
1 1 1
b
0
a
0
c
0
=a
0
.b
0
0 0 0
0 1 0
1 0 0
1 1 1
=> Cng AND
a
0
b
0

c
0

DHBK 2007
130
Multipliers
B nhn 2bit x 2bit C = B A
a
0
b
0

b
0

a
0

b
1

a
1

a
0
b
1

a
1
b
0
a
1
b
1

c
0
c
1
c
2
c
3

b
0

b
1

a
0

b
0

b
1

a
1

HA HA
c
0
c
1
c
2
c
3

DHBK 2007
131
Multipliers
B nhn 4bit x 3 bit
b
0

b
1

a
0

b
2
b
3

b
0

b
1

a
1

b
2
b
3

4-bit adder
0
b
0

b
1

a
2

b
2
b
3

4-bit adder
c
0
c
1
c
2
c
3
c
4
c
5
c
6

s
0
s
1
s
2
s
3
c
out

s
0
s
1
s
2
s
3
c
out

DHBK 2007
132
Logic units
Function value
for x,y
1-minterms 00 01 10 11 Expression
- 0 0 0 0 F
0
=0
m
3
0 0 0 1 F
1
=xy
m
2
0 0 1 0 F
2
=xy
m
2
+m
3
0 0 1 1 F
3
=x
m
1
0 1 0 0 F
4
=xy
m
1
+m
3
0 1 0 1 F
5
=y
m
1
+m
2
0 1 1 0 F
6
=xy+xy
m
1
+m
2
+m
3
0 1 1 1 F
7
=x+y
m
0
1 0 0 0 F
8
=(x+y)
m
0
+m
3
1 0 0 1 F
9
=xy+xy
m
0
+m
2
1 0 1 0 F
10
=y
m
0
+m
2
+m
3
1 0 1 1 F
11
=x+y
m
0
+m
1
1 1 0 0 F
12
=x
m
0
+m
1
+m
3
1 1 0 1 F
13
=x+y
m
0
+m
1
+m
2
1 1 1 0 F
14
=(xy)
m
0
+m
1
+m
2
+m
3
1 1 1 1 F
15
=1
DHBK 2007
133
Logic units
S
0

S
1

S
2

S
3

x
i

y
i

f
i

LU
x
i
y
i

f
i

S
0..3

DHBK 2007
134
FA FA FA FA FA
a
0
b
0
a
1
b
1
a
2
b
2
a
3
b
3
a
4
b
4

f
0

f
1
f
2
f
3
f
4

S
C
out

S selects the function to be executed:
0=addition, 1=subtraction
DHBK 2007
135
M
M selects the type of operation: 0=logic, 1=arithmetic
S
0
and S
1
select the operation
FA
a
0
b
0

f
0

ALE
FA
a
1
b
1

f
1

ALE
FA
a
2
b
2

f
2

ALE
FA
a
3
b
3

f
3

ALE
FA
a
4
b
4

f
4

ALE
C
out

S
01

X Y
DHBK 2007
136
M S
1
S
0
Function F X Y C
0
0 0 0 Complement A A 0 0
M S
1
S
0
Function F X Y C
0
0 0 1 AND A AND B A AND B 0 0
M S
1
S
0
Function F X Y C
0
0 1 0 Identity A A 0 0
M S
1
S
0
Function F X Y C
0
0 1 1 OR A OR B A OR B 0 0
M S
1
S
0
Function F X Y C
0
0 1 1 OR A OR B A OR B 0 0
1 0 0 Decrement A-1 A all 1 0
M S
1
S
0
Function F X Y C
0
0 1 1 OR A OR B A OR B 0 0
1 0 1 Add A+B A B 0
M S
1
S
0
Function F X Y C
0
0 1 1 OR A OR B A OR B 0 0
1 0 1 Add A+B A B 0
1 1 0 Subtract A-B A B 1
M S
1
S
0
Function F X Y C
0
0 1 1 OR A OR B A OR B 0 0
1 0 1 Add A+B A B 0
1 1 1 Increment A+1 A all 0 1
DHBK 2007
137
M S
1
S
0
Function F X Y C
0
0 1 1 OR A OR B A OR B 0 0
1 0 1 Add A+B A B 0
1 1
M
S
1

S
0

c
0

M S
1

c
0

DHBK 2007
138
M S
1
S
0
Function F X Y C
0
0 1 1 OR A OR B A OR B 0 0
1 0 1 Add A+B A B 0
1
1 1
M
S
1

S
0

X
1 1 1
1 1
a
i

b
i

1 1 1 1
1 1 1 1
S
1

S
0

b
a
S
0

S
1

M
X
DHBK 2007
139
M S
1
S
0
Function F X Y C
0
0 1 1 OR A OR B A OR B 0 0
1 0 1 Add A+B A B 0
b
i

M
S
1

S
0

Y
a
i

1 1
1 1
1 1
1 1
S
1

S
0

b
a
S
0

S
1

M
Y
DHBK 2007
140
M
FA
a
0
b
0

f
0

ALE
FA
a
1
b
1

f
1

ALE
FA
a
2
b
2

f
2

ALE
FA
a
3
b
3

f
3

ALE
FA
a
4
b
4

f
4

ALE
C
out

S
01

X Y
DHBK 2007
141
Decoders
E A
1
A
0
C
3
C
2
C
1
C
0
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
E
A
1

A
0

C
3
C
2
C
1
C
0

Decoder
C
3..0

A
1..0

E
DHBK 2007
142
Decoders
Decoder
C
3..0

A
1..0

E
Decoder
C
7..4

A
1..0

E
Decoder
C
11..8

A
1..0

E
Decoder
C
15..12

A
1..0

E
Decoder
A
3..2

E
DHBK 2007
143
Selectors
S
1
S
0
Y
0 0 D
0
0 1 D
1
1 0 D
2
1 1 D
3
D
3
D
2
D
1
D
0

S
1

S
0

Y
4-to-1
MUX
D
3..0

S
1..0

Y
DHBK 2007
144
Selectors
S
1
S
0
Y
0 0 D
0
0 1 D
1
1 0 D
2
1 1 D
3
D
3
D
2
D
1
D
0

Y
D
e
c
o
d
e
r

S
1

S
0

Cch thc hin khc
DHBK 2007
145
Selectors
4-to-1
selector
S
3..2

4-to-1
selector
D
7..4

S
1..0

4-to-1
selector
D
11..8

S
1..0

4-to-1
selector
D
15..12

S
1..0

4-to-1
selector
D
3..0

S
1..0

Y
DHBK 2007
146
Buses
Bus vi mch iu khin 3 trng thi
D
e
c
o
d
e
r

D
3
D
2
D
1
D
0
S
1
S
0

E Y
0 Z
1 D
Y
DHBK 2007
147
x
1
y
1
x
0
y
0
G (X>Y) L (X<Y)
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 0 0
x
1
y
1
x
0
y
0
G (X>Y) L (X<Y)
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 0 1
x
1
y
1
x
0
y
0
G (X>Y) L (X<Y)
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 1 0
x
1
y
1
x
0
y
0
G (X>Y) L (X<Y)
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 0 0
x
1
y
1
x
0
y
0
G (X>Y) L (X<Y)
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 0 0
1
1
1 1 1 1
y
1

x
1

x
0

y
0

G
1
1 1 1 1
1
y
1

x
1

x
0

y
0

L
DHBK 2007
148
x
1

x
0

y
1

y
0

1
1
1 1 1 1
y
1

x
1

x
0

y
0

G
1
1 1 1 1
1
y
1

x
1

x
0

y
0

L
G
L
Comp
X
i
Y
i

G
i

L
i

G
i+1

L
i+1

DHBK 2007
149
Comp
x
1
y
1

Comp
x
2
y
2

Comp
x
3
y
3

Comp
x
4
y
4

Comp
x
5
y
5

Comp
x
6
y
6

Comp
x
7
y
7
x
0
y
0

G
L
Comp
x
1
y
1
x
2
y
2

Comp
x
3
y
3
x
4
y
4

Comp
x
5
y
5
x
6
y
6

Comp
x
7
y
7
x
0
y
0

Comp
Comp
Comp
G L
DHBK 2007
150
Cc b so snh vi hng s n gin
y=1 when X=0
X
y
y=1 when X=255
y=1 when X>=64
X
y
y=1 when X<192
x
7
x
6

y
y=1 when X is even
x
0

y
x
7
x
6

y
X is
8 bits
DHBK 2007
151
Cc loi flip-flop
Mt s khi nim:
Mch logic t hp: tn hiu u ra l hm s ca cc gi tr hin ti ca
cc tn hiu u vo
Mch logic tun t: tn hiu u ra l hm s ca cc gi tr hin ti ca
tn hiu u vo v trng thi hin ti (c ngha l cng l hm s ca cc
gi tr trc ca tn hiu u vo)
Mch logic tun t khng ng b: tn hiu u ra v trng thi thay i
ngay khi tn hiu u vo thay i
Mch logic tun t ng b: tn hiu u ra v trng thi ch thay i khi
tn hiu u vo l ng h xung nhp c 1 gi tr no y
Chu k xung nhp: khong thi gian gia hai ln chuyn t 1 xung 0
ca tn hiu xung nhp
Tn s xung nhp: 1 / chu k xung nhp
Chu k tc ng ca xung nhp: (thi gian tn hiu xung nhp = 1) / chu
k xung nhp
Sn ln: tn hiu xung nhp chuyn t 01
Sn xung: tn hiu xung nhp chuyn t 10

DHBK 2007
152
Cc loi flip-flop
S
R
Clk
Q
Q
Symbol
Tam gic c ngha l tc ng sn ln
Tc ng sn xung
S R Q(next)
0 0 Q
0 1 0
1 0 1
1 1 NA
Characteristic table
(for design of SR flip-flop)
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
Excitation table
(for design with SR flip-flop)
Tc ng mc 1
Tc ng mc 0
SR flip-flop
DHBK 2007
153
Cc loi flip-flop
J
K
Clk
Q
Q
Symbol
J K Q(next)
0 0 Q
0 1 0
1 0 1
1 1 Q
(for design of JK flip-flop)
Q Q(next) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
Excitation table
(for design with JK flip-flop)
Circuits that use
JK flip-flops are cheaper
than those using SR flip-flops:
more dont cares
JK flip-flop
DHBK 2007
154
Cc loi flip-flop
D
Clk
Q
Q
Symbol
(for design of D flip-flop)
D Q(next)
0 0
1 1
Excitation table
(for design with D flip-flop)
Q Q(next) D
0 0 0
0 1 1
1 0 0
1 1 1
Designing with D flip-flop
is easy
D flip-flop
DHBK 2007
155
Cc loi flip-flop
T
Clk
Q
Q
Symbol
(for design of T flip-flop)
T Q(next)
0 Q
1 Q
Excitation table
(for design with T flip-flop)
Q Q(next) T
0 0 0
0 1 1
1 0 1
1 1 0
D
Clk
Q
Q
T
T flip-flop
DHBK 2007
156
Thit k mch s tun t ng b
My trng thi hu hn Finite State Machine (FSM)
FSM loi Moore (ph thuc vo trng thi)
FSM loi Mealy (ph thuc vo tn hiu vo)
Cc bc thit k:
Bc 1: V s trng thi
Bc 2: Ti thiu ho s lng cc trng thi
Bc 3: M ho trng thi
Bc 4: La chn flip-flop
Bc 5: Thc hin mch logic t hp
Bc 6: Phn tch tn hiu theo thi gian
DHBK 2007
157
Finite State Machine
V d: Thit k mt b m 4. B m s m khi c tn
hiu CE=1 (Count Enable) v ngng m khi CE= 0.
Bc 1: V s trng thi FSM
Count=0
CE=0 CE=0
CE=0 CE=0
Count=1
CE=1
Count=2
CE=1
Count=3
CE=1
CE=1
DHBK 2007
158
Count=0
CE=0 CE=0
CE=0 CE=0
Count=1
CE=1
Count=2
CE=1
Count=3
CE=1
CE=1
Ch chuyn trng thi ti sn ln ca xung nhp
Ti sn ln ca xung nhp, ch c php 1 iu kin chuyn trng thi xy ra
1. Ta ang trng thi Count=0
2. CE = 0: i chn ca sn ln ca xung nhp
3. CE=1: i chn ca 1 sn ln khc nhng cha m
4. Sn ln ca xung nhp: chuyn sang trng thi Count=1, CE vn =1
5. CE = 0: i chn ca 1 sn ln khc
6. Sn ln ca xung nhp: chyn sang Count=1, vi CE=0
Count=0
CE=0 CE=0
CE=0 CE=0
Count=1
CE=1
Count=2
CE=1
Count=3
CE=1
CE=1
Count=0
CE=0 CE=0
CE=0 CE=0
Count=1
CE=1
Count=2
CE=1
Count=3
CE=1
CE=1
Count=0
CE=0 CE=0
CE=0 CE=0
Count=1
CE=1
Count=2
CE=1
Count=3
CE=1
CE=1
Count=0
CE=0 CE=0
CE=0 CE=0
Count=1
CE=1
Count=2
CE=1
Count=3
CE=1
CE=1
DHBK 2007
159
Q
1
Q
0
=00
CE=0 CE=0
CE=0 CE=0
Q
1
Q
0
=01
CE=1
Q
1
Q
0
=10
CE=1
Q
1
Q
0
=11
CE=1
CE=1
Bc 2: Ti thiu ho s trng thi
Bc 3: M ho cc trng thi
DHBK 2007
160
Bc 4: Chn loi flip-flop. y n gin ta chn
loi D
Bc 5: Thc hin mch
DHBK 2007
161
Chuyn FSM sang bng trng thi k tip
Q
1
Q
0
=00
CE=0 CE=0
CE=0 CE=0
Q
1
Q
0
=01
CE=1
Q
1
Q
0
=10
CE=1
Q
1
Q
0
=11
CE=1
CE=1
Present state Next state
Q
1
Q
0
Q
1n
Q
0n

CE=0 CE=1
00 00 01
01 01 10
10 10 11
11 11 00

DHBK 2007
162
Xc nh cc hm u vo flip-flop D
Present state Next state
Q
1
Q
0
Q
1n
Q
0n
CE=0 CE=1
00 00 01
01 01 10
10 10 11
11 11 00
0 0 1 1
0 1 0 1
CE
Q
1n
=D
1

Q
0

Q
1

Q Q(next) D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation table
for D flip-flop
D to be applied
is identical to Q
n

0 1 1 0
1 0 0 1
CE
Q
0n
=D
0

Q
0

Q
1

DHBK 2007
163
Thc hin:
0 0 1 1
0 1 0 1
CE
Q
1n
=D
1

Q
0

Q
1

0 1 1 0
1 0 0 1
CE
Q
0n
=D
0

Q
0

Q
1

CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
DHBK 2007
164
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Clk
CE
Q
1

Q
0

CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
DHBK 2007
165
FSM loi Moore
V d: Thit k b m 4, m n 3 th bo
Bc 1: V s trng thi FSM:
Count=0
Y=0
CE=0 CE=0
CE=0 CE=0
Count=1
Y=0
CE=1
Count=2
Y=0
CE=1
Count=3
Y=1
CE=1
CE=1
DHBK 2007
166
c im:
Tn hiu u ra c xc nh ti mi trng thi
Tn hiu ra ch ph thuc vo trng thi hin ti m khng
ph thuc vo tn hiu vo
Do , gi tr tn hiu ra c ghi bn trong vng trn biu
din trng thi
FSM loi Moore
DHBK 2007
167
Q
1
Q
0
=00
Y=0
CE=0 CE=0
CE=0 CE=0
Q
1
Q
0
=01
Y=0
CE=1
Q
1
Q
0
=10
Y=0
CE=1
Q
1
Q
0
=11
Y=1
CE=1
CE=1
Bc 2: Ti thiu ho s lng trng thi
Bc 3: M ho trng thi
FSM loi Moore
DHBK 2007
168
loi D
Bc 5: Thc hin mch
FSM loi Moore
DHBK 2007
169
Q
1
Q
0
=00
Y=0
CE=0 CE=0
CE=0 CE=0
Q
1
Q
0
=01
Y=0
CE=1
Q
1
Q
0
=10
Y=0
CE=1
Q
1
Q
0
=11
Y=1
CE=1
CE=1
Present state Next state Outputs
Q
1
Q
0
Q
1n
Q
0n
Y
CE=0 CE=1
00 00 01 0
01 01 10 0
10 10 11 0
11 11 00 1
Y ch ph thuc trng thi
hin ti, khng ph
thuc vo tn hiu vo
FSM loi Moore
DHBK 2007
170
0 0 1 1
0 1 0 1
CE
Q
1n
=D
1

Q
0

Q
1

Q Q(next) D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation table
for D flip-flop
D to be applied
is identical to Q
n
0 1 1 0
1 0 0 1
CE
Q
0n
=D
0

Q
0

Q
1

Present state Next state Outputs
Q
1
Q
0
Q
1n
Q
0n
Y
CE=0 CE=1
00 00 01 0
01 01 10 0
10 10 11 0
11 11 00 1
0 0
0 1
Y
Q
1

Q
0

FSM loi Moore
DHBK 2007
171
Thc hin mch:
0 0 1 1
0 1 0 1
CE
Q
1n
=D
1

Q
0

Q
1

0 1 1 0
1 0 0 1
CE
Q
0n
=D
0

Q
0

Q
1

CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
0 0
0 1
Y
Q
1

Q
0

Y
FSM loi Moore
DHBK 2007
172
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
Clk
CE
Q
1

Q
0

Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
Danger for
Glitch!
FSM loi Moore
DHBK 2007
173
FSM loi Mealy
V d: Thit k b m 4, nu tn hiu m CE=1 v gi
tr m =3 th tn hiu ra Y=1
Bc 1: V s trng thi FSM:
Count=0
CE=0/Y=0 CE=0/Y=0
CE=0/Y=0 CE=0/Y=0
Count=1
CE=1/Y=0
Count=2
CE=1/Y=0
Count=3
CE=1/Y=0
CE=1/Y=1
DHBK 2007
174
c im:
Tn hiu ra c xc nh cho mi trng thi v cc tn hiu
vo ti trng thi
Tn hiu ra ph thuc vo trng thi u hin ti v cc gi
tr u vo ti trng thi
Do gi tr tn hiu ra c ghi ti mi tn chuyn trng
thi
FSM loi Mealy
DHBK 2007
175
Q
1
Q
0
=00
CE=0/Y=0 CE=0/Y=0
CE=0/Y=0 CE=0/Y=0
Q
1
Q
0
=01
CE=1/Y=0
Q
1
Q
0
=10
CE=1/Y=0
Q
1
Q
0
=11
CE=1/Y=0
CE=1/Y=1
Bc 3: M ho trng thi
FSM loi Mealy
DHBK 2007
176
loi D
Bc 5: Thc hin mch

FSM loi Mealy
DHBK 2007
177

Q
1
Q
0
=00
CE=0/Y=0 CE=0/Y=0
CE=0/Y=0 CE=0/Y=0
Q
1
Q
0
=01
CE=1/Y=0
Q
1
Q
0
=10
CE=1/Y=0
Q
1
Q
0
=11
CE=1/Y=0
CE=1/Y=1
Present state Next state/Outputs
Q
1
Q
0
Q
1n
Q
0n
/Y
CE=0 CE=1
00 00/0 01/0
01 01/0 10/0
10 10/0 11/0
11 11/0 00/1
Y ph thuc vo trng thi
hin ti, v ph
thuc vo c tn hiu vo
FSM loi Mealy
DHBK 2007
178
0 0 1 1
0 1 0 1
CE
Q
1n
=D
1

Q
0

Q
1

Q Q(next) D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation table
for D flip-flop
D to be applied
is identical to Q
n
0 1 1 0
1 0 0 1
CE
Q
0n
=D
0

Q
0

Q
1

Present state Next state/Outputs
Q
1
Q
0
Q
1n
Q
0n
/Y
CE=0 CE=1
00 00/0 01/0
01 01/0 10/0
10 10/0 11/0
11 11/0 00/1
0 0 0 0
0 0 1 0
CE
Y
Q
0

Q
1

FSM loi Mealy
DHBK 2007
179
Thc hin mch:
0 0 1 1
0 1 0 1
CE
Q
1n
=D
1

Q
0

Q
1

0 1 1 0
1 0 0 1
CE
Q
0n
=D
0

Q
0

Q
1

CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
0 0 0 0
0 0 1 0
CE
Y
Q
0

Q
1

Y
FSM loi Mealy
DHBK 2007
180

Clk
CE
Q
1

Q
0

Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
Danger for
Glitch!
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
CE Q
1
Q
0

Q
1n

Q
0n

D
1

Q
1

Q
D
0

Q
0

Q
Y
FSM loi Mealy
DHBK 2007
181
M hnh FSM loi Moore
D
Clk
Q
S*=F(S,I)

Mch logic
t hp
cho trng
thi k
tip
O=H(S)

Mch logic
t hp
cho tn
hiu ra
D
Clk
Q
D
Clk
Q
Clock
Next
State S*
Current
State S
Outputs
O
Inputs I
DHBK 2007
182
M hnh FSM loi Mealy
D
Clk
Q
S*=F(S,I)

Mch logic
t hp
cho trng
thi k
tip

O=H(S,I)

Mch logic
t hp
cho tn
hiu ra
D
Clk
Q
D
Clk
Q
Clock
Next State S*
Current
State S
Outputs
O
Inputs I
DHBK 2007
183
Bc 1: V s trng thi FSM
FSM c xy dng t bn miu t chi tit bi ton
La chn loi FSM cho ph hp: Moore hay Mealy
V trng thi u tin v cc trng thi tip theo da
vo iu kin chuyn trng thi ...
DHBK 2007
184
Mc ch: t trng thi ng ngha vi t flip-flop
Nguyn tc:
2 FSM c coi l tng ng nu nh chng cho cng mt
chui tn hiu ra vi cng mt chui tn hiu vo
2 trng thi ca FSM loi Moore c th c thay th bi 1
trng thi nu nh 2 trng thi c cng tn hiu ra ng
thi c cng trng thi k tip khi c cng tn hiu vo
2 trng thi ca FSM loi Mealy c th c thay th bi 1
trng thi nu nh chng c cng tn hiu ra cho cng tn hiu
vo ng thi chng c cng trng thi k tip khi c cng tn
hiu vo

DHBK 2007
185
V d:
NEXT STATE / OUTPUT PRESENT
STATE
AB=00 AB=01 AB=10
s
0
s
4
/1 s
2
/0 s
1
/1
s
1
s
2
/0 s
5
/1 s
4
/1
s
2
s
1
/1 s
0
/0 s
3
/1
s
3
s
2
/0 s
5
/1 s
4
/1
s
4
s
0
/0 s
5
/1 s
1
/1
s
5
s
2
/0 s
4
/1 s
2
/1
DHBK 2007
186
Xy dng bng nh sau:
STATE
AB=00 AB=01 AB=10
s
0
s
4
/1 s
2
/0 s
1
/1
s
1
s
2
/0 s
5
/1 s
4
/1
s
2
s
1
/1 s
0
/0 s
3
/1
s
3
s
2
/0 s
5
/1 s
4
/1
s
4
s
0
/0 s
5
/1 s
1
/1
s
5
s
2
/0 s
4
/1 s
2
/1
s
1

s
2

s
3

s
4

s
5

s
0
s
1
s
2
s
3
s
4

DHBK 2007
187
Xo tt c cc t hp trng thi c tn hiu ra khc nhau
cho cng tn hiu vo
STATE
AB=00 AB=01 AB=10
s
0
s
4
/1 s
2
/0 s
1
/1
s
1
s
2
/0 s
5
/1 s
4
/1
s
2
s
1
/1 s
0
/0 s
3
/1
s
3
s
2
/0 s
5
/1 s
4
/1
s
4
s
0
/0 s
5
/1 s
1
/1
s
5
s
2
/0 s
4
/1 s
2
/1
s
1

s
2

s
3

s
4

s
5

s
0
s
1
s
2
s
3
s
4

DHBK 2007
188
Ch r nhng cp trng thi k tip no phi tng
ng cho cp trng thi ang xt cng l tng
ng
STATE
AB=00 AB=01 AB=10
s
0
s
4
/1 s
2
/0 s
1
/1
s
1
s
2
/0 s
5
/1 s
4
/1
s
2
s
1
/1 s
0
/0 s
3
/1
s
3
s
2
/0 s
5
/1 s
4
/1
s
4
s
0
/0 s
5
/1 s
1
/1
s
5
s
2
/0 s
4
/1 s
2
/1
s
1

s
2

s
3

s
4

s
5

s
0
s
1
s
2
s
3
s
4

1-4
1-3
1-4
1-3
OK
1-4
1-3
0-2
OK
1-4
1-3
4-5
2-4
0-2
OK
1-4
1-3
4-5
2-4
0-2
0-2
1-4
OK
1-4
1-3
4-5
2-4
4-5
2-4
0-2
0-2
1-4
OK
1-4
1-3
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2
0-2
1-4
OK
DHBK 2007
189
1-4
1-3
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2
0-2
1-4
OK
Xo nhng cp trng thi m khng th c cp trng
thi k tip tng ng
STATE
AB=00 AB=01 AB=10
s
0
s
4
/1 s
2
/0 s
1
/1
s
1
s
2
/0 s
5
/1 s
4
/1
s
2
s
1
/1 s
0
/0 s
3
/1
s
3
s
2
/0 s
5
/1 s
4
/1
s
4
s
0
/0 s
5
/1 s
1
/1
s
5
s
2
/0 s
4
/1 s
2
/1
s
1

s
2

s
3

s
4

s
5

s
0
s
1
s
2
s
3
s
4

1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2
0-2
1-4
OK
1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2
1-4
OK
1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2
1-4
OK
1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2: ?
1-4: ?
OK
1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2: ?
1-4: ?
OK
1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2: ?
1-4: ?
OK
DHBK 2007
190
Lp li cho n khi khng cn xo c cp trng thi
no na th dng
STATE
AB=00 AB=01 AB=10
s
0
s
4
/1 s
2
/0 s
1
/1
s
1
s
2
/0 s
5
/1 s
4
/1
s
2
s
1
/1 s
0
/0 s
3
/1
s
3
s
2
/0 s
5
/1 s
4
/1
s
4
s
0
/0 s
5
/1 s
1
/1
s
5
s
2
/0 s
4
/1 s
2
/1
s
1

s
2

s
3

s
4

s
5

s
0
s
1
s
2
s
3
s
4

1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2: ?
1-4: ?
OK
1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2: ?
1-4: ?
OK
1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2: ?
1-4: ?
OK
1-4: ?
1-3:OK
4-5
2-4
4-5
2-4
0-2, 4-5
1-2
0-2: ?
0-2: ?
1-4: ?
OK
S lng trng thi ti thiu : 3
{s
0
,s
2
}=u
0

{s
1
,s
3
,s
4
}=u
1

{s
5
}=u
2
DHBK 2007
191
Xy dng bng trng thi mi
STATE
AB=00 AB=01 AB=10
s
0
s
4
/1 s
2
/0 s
1
/1
s
1
s
2
/0 s
5
/1 s
4
/1
s
2
s
1
/1 s
0
/0 s
3
/1
s
3
s
2
/0 s
5
/1 s
4
/1
s
4
s
0
/0 s
5
/1 s
1
/1
s
5
s
2
/0 s
4
/1 s
2
/1
STATE
AB=00 AB=01 AB=10
u
0
u
1
/1 u
0
/0 u
1
/1
u
1
u
0
/0 u
2
/1 u
1
/1
u
2
u
0
/0 u
1
/1 u
0
/1
S lng trng thi ti thiu : 3
{s
0
,s
2
}=u
0

{s
1
,s
3
,s
4
}=u
1

{s
5
}=u
2
DHBK 2007
192
Bc 3: M ho trng thi
n trng thi cn t nht log
2
n flip-flops.
C tt c n! kh nng m ho (n la chn cho trng thi
u tin, n-1 cho trng thi th 2 ...)
No. s0 s1 s2 s3 No. s0 s1 s2 s3
1 00 01 10 11 13 10 00 01 11
2 00 01 11 10 14 10 00 11 01
3 00 10 01 11 15 10 01 00 11
4 00 10 11 01 16 10 01 11 00
5 00 11 01 10 17 10 11 00 01
6 00 11 10 01 18 10 11 01 00
7 01 00 10 11 19 11 00 01 10
8 01 00 11 10 20 11 00 10 01
9 01 10 00 11 21 11 01 00 10
10 01 10 11 00 22 11 01 10 00
11 01 11 00 10 23 11 10 00 01
12 01 11 10 00 24 11 10 01 00
DHBK 2007
193
C cn thit phi la chn cch m ho?
C, bi mi s la chn s cho ta phc tp ca mch t
hp cng nh tr ca ton b mch
Cc kiu m ho thng dng:
Straightforward
Minimum-bit-change
One-hot
Bc 3: M ho trng thi
DHBK 2007
194
Kiu m ho ny s dng gi tr nh phn ca th t
trng thi lm m cho trng thi (s
0
000,
s
5
101, )
STATE
CD=0X CD=10 CD=11
s
0
s
0
/0 s
1
/0 s
2
/1
s
1
s
1
/0 s
2
/0 s
0
/0
s
2
s
2
/0 s
0
/1 s
1
/0
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Bc 3: M ho trng thi-Straightforward
DHBK 2007
195
M s c gn cho trng thi sao cho tng s bt thay
i khi chuyn trng thi ca tt c cc trng thi l nh
nht
Phng php m ho ny hay c s dng khi mun
ti thiu ho kch thc chip cng nh cng sut tiu
th
00 01
10 11
1
1
2 2
00 01
11 10
1
1
1 1
Straightforward Minimum-bit-change
Gray code
counter
Bc 3: M ho trng thi-minimum bit change
DHBK 2007
196
0 1
2
Possible
encoding:
s
0
=00
s
1
=10
s
2
=11
STATE
CD=0X CD=10 CD=11
s
0
s
0
/0 s
1
/0 s
2
/1
s
1
s
1
/0 s
2
/0 s
0
/0
s
2
s
2
/0 s
0
/1 s
1
/0
STATE
CD=0X CD=10 CD=11
00 00/0 10/0 11/1
10 10/0 11/0 00/0
11 11/0 00/1 10/0
Bc 3: M ho trng thi-minimum bit change
DHBK 2007
197
Mi trng thi ng vi mt flip-flop, Q ca 1 FF =1, Q
ca cc FF khc =0
Dng khi s lng trng thi nh
Rt d thc hin, mch t hp n gin
Cu trc ca FPGA rt ph hp vi kiu m ho ny
Bc 3: M ho trng thi- one hot
DHBK 2007
198
One-hot encoding
s
0
=001
s
1
=010
s
2
=100
STATE
CD=0X CD=10 CD=11
s
0
s
0
/0 s
1
/0 s
2
/1
s
1
s
1
/0 s
2
/0 s
0
/0
s
2
s
2
/0 s
0
/1 s
1
/0
STATE
CD=0X CD=10 CD=11
001 001/0 010/0 100/1
010 010/0 100/0 001/0
100 100/0 001/1 010/0
DHBK 2007
199
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
C
D
Y
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
Q
0

D
Q
1

D
Q
2

D
P
C C
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
DHBK 2007
200
M ho One-hot vi flip-flop D
Mi mt mi tn chuyn trng thi ti mt trng thi cn mt
cng AND
DHBK 2007
201
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
Q
0

S R
Q
1

S R
Q
2

S R
C
D
Y
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
P C C
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
CD=10
Y=1
s
0

CD=0X
Y=0
s
1

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
s
2

CD=10
Y=0
CD=11
Y=0
CD=0X
Y=0
CD=11
Y=1
DHBK 2007
202
M ho One-hot vi flip-flop SR :
Mi mt mi tn chuyn trng thi xut pht t mt trng
thi khc cn mt cng AND ti u vo S
Mi mt mi tn hng ti cc trng thi khc cn 1 cng
AND ti u vo R
DHBK 2007
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Bc 4: La chn loi Flip-flop
JK flip-flop
y l loi flip-flop t nht
Kh thit k nht
C nhiu trng thi dont cares nn mch t hp nhanh v r
nht
SR flip-flop
flip-flop r
Kh thit k

DHBK 2007
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D flip-flop
flip-flop r
D thit k nht
Khng c dont cares dn ti mch t hp phc tp v chm
nht
T flip-flop
flip-flop r
D thit k
Khng c dont cares dn ti mch t hp phc tp v chm
nht
Thng c dng thit k b m v b chia tn
Bc 4: La chn loi Flip-flop
DHBK 2007
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Bc 5: Thc hin mch logic t hp D flip-flop

Q Q(next) D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation table
for D flip-flop
D to be applied
is identical to Q
n

0 0 x 0
0 0 x 0
Y
Q
0

Q
1

1 0 x 0
0 0 x 1
C
D
0 0 x 1
0 0 x 1
Q
1n
=D
1

Q
0

Q
1

1 0 x 0
0 1 x 0
C
D
0 1 x 0
0 1 x 0
Q
0n
=D
0

Q
0

Q
1

0 0 x 1
1 0 x 0
C
D
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
DHBK 2007
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0 0 x 0
0 0 x 0
Y
Q
0

Q
1

1 0 x 0
0 0 x 1
C
D
0 0 x 1
0 0 x 1
Q
1n
=D
1

Q
0

Q
1

1 0 x 0
0 1 x 0
C
D
0 1 x 0
0 1 x 0
Q
0n
=D
0

Q
0

Q
1

0 0 x 1
1 0 x 0
C
D
Q
1

D
Q
0

D
C
D
Y
Clr Clr
Bc 5: Thc hin mch logic t hp D flip-flop
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207
Xc nh cc hm u vo T
Q Q(next) T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation table
for T flip-flop
0 0 x 0
0 0 x 0
Y
Q
0

Q
1

1 0 x 0
0 0 x 1
C
D
0 0 x 0
0 0 x 0
T
1

Q
0

Q
1

1 0 x 1
0 1 x 1
C
D
0 0 x 0
0 0 x 0
T
0

Q
0

Q
1

0 1 x 1
1 1 x 0
C
D
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Bc 5: Thc hin mch logic t hp T flip-flop
DHBK 2007
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0 0 x 0
0 0 x 0
T
0

Q
0

Q
1

0 1 x 1
1 1 x 0
C
D
0 0 x 0
0 0 x 0
T
1

Q
0

Q
1

1 0 x 1
0 1 x 1
C
D
0 0 x 0
0 0 x 0
Y
Q
0

Q
1

1 0 x 0
0 0 x 1
C
D
Q
1

T
Q
0

T
C
D
Y
Cost: 32
Clr Clr
Bc 5: Thc hin mch logic t hp T flip-flop
DHBK 2007
209
Xc nh cc hm u vo S v R
Excitation table
for SR flip-flop
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
S
1

Q
0

Q
1

C
D
R
1

Q
0

Q
1

C
D
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
0
0
x
x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
0 0
0 0
x x
x x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
0 0 x
0 0 x
x x 0
x x 0
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
0 0 x
0 0 x
0
x x 0
x x 0
x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
0 0 x
0 0 x
0 1
x x 0
x x 0
x 0
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
0 0 x
0 0 x
0 1 0
x x 0
x x 0
x 0 1
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
0 0 x
0 0 x
1 0 0
0 1 0
x x 0
x x 0
0 x 1
x 0 1
0 0 x x
0 0 x x
1 0 x 0
0 1 x 0
x x x 0
x x x 0
0 x x 1
x 0 x 1
Bc 5: Thc hin mch logic t hp SR flip-flop
DHBK 2007
210
Excitation table
for SR flip-flop
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
S
0

Q
0

Q
1

C
D
R
0

Q
0

Q
1

C
D
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
0 x 0
0 x 0
x 0 x
x 0 x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
0 x 0
0 x 0
1 0 0
x 0 x
x 0 x
0 1 x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
0 x 0
0 x 0
0 0 1
1 0 0
x 0 x
x 0 x
x 1 0
0 1 x
0 x x 0
0 x x 0
0 0 x 1
1 0 x 0
x 0 x x
x 0 x x
x 1 x 0
0 1 x x
0 0 x 0
0 0 x 0
Y
Q
0

Q
1

1 0 x 0
0 0 x 1
C
D
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0

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S
1

Q
0

Q
1

C
D
R
1

Q
0

Q
1

C
D
0 0 x x
0 0 x x
1 0 x 0
0 1 x 0
x x x 0
x x x 0
0 x x 1
x 0 x 1
Q
1

S R
Q
0

S R
C
D
C
C
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S
0

Q
0

Q
1

C
D
R
0

Q
0

Q
1

C
D
Q
1

S R
Q
0

S R
C
D
C
C
0 x x 0
0 x x 0
0 0 x 1
1 0 x 0
x 0 x x
x 0 x x
x 1 x 0
0 1 x x
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S
0

Q
0

Q
1

C
D
R
0

Q
0

Q
1

C
D
Q
1

S R
Q
0

S R
C
D
C
C
0 x x 0
0 x x 0
0 0 x 1
1 0 x 0
x 0 x x
x 0 x x
x 1 x 0
0 1 x x
0 0 x 0
0 0 x 0
Y
Q
0

Q
1

1 0 x 0
0 0 x 1
C
D
Y
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Xc nh cc hm u vo J v K
Excitation table
for JK flip-flop
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
J
1

Q
0

Q
1

C
D
K
1

Q
0

Q
1

C
D
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
0
0
x
x
0 0
0 0
x x
x x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
0 0 x
0 0 x
x x 0
x x 0
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
0 0 x
0 0 x
0 1 x
x x 0
x x 0
x x 1
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
0 0 x
0 0 x
1 0 x
0 1 x
x x 0
x x 0
x x 1
x x 1
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
0 0 x x
0 0 x x
1 0 x x
0 1 x x
x x x 0
x x x 0
x x x 1
x x x 1
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Bc 5: Thc hin mch logic t hp JK flip-flop
DHBK 2007
215
Excitation table
for JK flip-flop
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
Q Q(next) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
J
0

Q
0

Q
1

C
D
K
0

Q
0

Q
1

C
D
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
0 x 0
0 x 0
x 0 x
x 0 x
0 x 0
0 x 0
1 x 0
x 0 x
x 0 x
x 1 x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
0 x 0
0 x 0
0 x 1
1 x 0
x 0 x
x 0 x
x 1 x
x 1 x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
0 x x 0
0 x x 0
0 x x 1
1 x x 0
x 0 x x
x 0 x x
x 1 x x
x 1 x x
STATE
CD=0X CD=10 CD=11
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
0 0 x 0
0 0 x 0
Y
Q
0

Q
1

1 0 x 0
0 0 x 1
C
D

DHBK 2007
216
J
1

Q
0

Q
1

C
D
K
1

Q
0

Q
1

C
D
Q
1

J K
Q
0

J K
C
D
C
C
0 0 x x
0 0 x x
1 0 x x
0 1 x x
x x x 0
x x x 0
x x x 1
x x x 1
DHBK 2007
217
J
0

Q
0

Q
1

C
D
K
0

Q
0

Q
1

C
D
Q
1

J K
Q
0

J K
C
D
C
C
0 x x 0
0 x x 0
0 x x 1
1 x x 0
x 0 x x
x 0 x x
x 1 x x
x 1 x x
0 0 x 0
0 0 x 0
Y
Q
0

Q
1

1 0 x 0
0 0 x 1
C
D
Y
DHBK 2007
218
Xc nh tn s ti a:
Tn s ti a = 1/tr ca ng di nht
ng di nht l ng c tr mch t hp ln nht gia
hai sn xung nhp
V d:
Q
1

D
Q
0

D
C
D
Y
Clr Clr
Q
1

D
Q
0

D
C
D
Y
Clr Clr
DHBK 2007
219
Cc mch s tun t c bn
Thanh ghi (Registers)
Thanh ghi dch (Shift registers)
B m (Counter)
Tp thanh ghi (Register files)
Cu trc hng i vo sau ra trc LIFO (stack)
Cu trc hng i vo trc ra trc FIFO
DHBK 2007
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Registers
Register
D Q D Q D Q D Q
Clk
I
3
I
2
I
1
I
0

Q
3
Q
2
Q
1
Q
0

Register
I
3
I
2
I
1
I
0

Q
3
Q
2
Q
1
Q
0

Symbol
DHBK 2007
221
D Q D Q D Q D Q
Clk
I
3
I
2
I
1
I
0

Q
3
Q
2
Q
1
Q
0

1 0
S
Load
1 0
S
1 0
S
1 0
S
Thanh ghi c th np d liu
Register
I
3
I
2
I
1
I
0

Q
3
Q
2
Q
1
Q
0

Symbol
Load
Registers
DHBK 2007
222
Thanh ghi dch vo ni tip ra song song (SIPO)
D Q D Q D Q D Q
Clk
I
L

Q
3
Q
2
Q
1
Q
0

1 0
S
SE
1 0
S
1 0
S
1 0
S
Shift Registers
DHBK 2007
223
Shift Register
Q
3
Q
2
Q
1
Q
0

Symbol
SE
I
L

Thanh ghi dch vo ni tip ra song song (SIPO)
Shift Registers
DHBK 2007
224
Thanh ghi dch vo song song, ra ni tip (PISO)
D Q D Q D Q D Q
Clk
I
L

Q
0

1 0
S
Sh/Ld
1 0
S
1 0
S
1 0
S
I
3
I
2
I
1
I
0

CE
Shift
Register
I
3
I
2
I
1
I
0

Q
0

Symbol
I
L

CE
Sh/Ld
Shift Registers
DHBK 2007
225
Counters
B m tng ng b
D Q D Q
Clk
Q
1
Q
0

Clear
D Q
Q
2
Output
carry
HA HA HA
E
DHBK 2007
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2.4 Cu trc FSMD

DHBK 2007
227
2.4 Cu trc FSMD
FSMD: Finite State Machine with Datapath
FSMD = hardcoded processor
Consists of a datapath that performs the computations
and a controller which indicates to the datapath which
operations have to be carried out on which data
The controller always executes the same algorithm:
hardcoded
A traditional ASIC consists of multiple interconnected
FSMDs
DHBK 2007
228
Datapath
Controller
Control
signals
Status
signals
Data
inputs
Data
outputs
Control
inputs
Control
outputs
2.4 Cu trc FSMD
DHBK 2007
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2.4 Cu trc FSMD
Datapath design
Datapath
Temporary storage: registers, register files, FIFOs,
Functional units: arithmetic and logic units, shifters
Connections: busses, multiplexors, tri-state bus drivers
DHBK 2007
230
=
=
2
1 i
i
x sum
Task:
sum = 0
FOR i = 1 TO 2
sum = sum + x
i

ENDFOR
y = sum
Algorithm:
Processing
Control
Datapath construction rules:
each variable and constant corresponds to a register
each operator corresponds to a functional unit
connect outputs of registers to input of functional
units; when multiple outputs connect to the same input:
MUX or bus with tristate drivers
connect output of functional units to input
of registers; when multiple outputs connect to the same
input: MUX or bus with tristate drivers
2.4 Cu trc FSMD
Datapath design
DHBK 2007
231
sum = 0
FOR i = 1 TO 2
sum = sum + x
i

ENDFOR
y = sum
Algorithm:
Variables: sum
Reset
Load
Clk
Register
SUM
0
1
2
Wait
100
Add
Operators: add
x
i

Connections
Add2
010
Output
001
Add1
010
Start=1
y
0
Start
Output order:
Reset,Load,
Out
210
2.4 Cu trc FSMD
Datapath design
DHBK 2007
232
Task: count the number of 1s in a word
Data = Inport || OCnt = 0 || Mask = 1
WHILE Data <> 0 DO
Temp = Data AND Mask
OCnt = OCnt + Temp || Data = Data >> 1
ENDWHILE
Outport = OCnt
Algorithm:
All instructions on a single line are executed concurrently:
maximum speed, but highest cost

Trading-off speed for area is explained in the section on
Synthesis techniques

All hardware components work in parallel. Implementing
hardware is hence not writing a sequential software
program and implementing this directly in hardware. Above
algorithm is a concurrent description!
2.4 Cu trc FSMD
Datapath design
DHBK 2007
233
Data = Inport; OCnt = 0; Mask = 1
WHILE Data <> 0 DO
OCnt = OCnt + Temp; Data = Data >> 1
ENDWHILE
Outport = OCnt
0
1
2
3
4
5
Comp
x00000
Update
010100
Load
111x00
s=1
Temp
x00010
z=0
Out
x00001
z=1
s=0
s
Data
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
OCnt
R
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
Mask
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
Temp
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
<>0
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
AND
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
Add
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
>>1
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
1 0
Inport
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
zero
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
Outport
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
Wait
x01x00
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
Output order:
543210
DHBK 2007
234
Possible optimisations:
When the life time of 2 variables is non-overlapping, both can
be stored in the same register: register sharing
When two operations are not executed concurrently, they can
be assigned to the same functional unit: functional unit
sharing
When two connections are not used concurrently, they can be
shared: connection sharing
When two registers are not concurrently read from resp.
writen to, they can be combined into a single register file:
register port sharing
Operations that could be executed concurrently, may also be
executed sequentially, facilitating the four previous
optimisations
2.4 Cu trc FSMD
Datapath design
DHBK 2007
235
Temporary storage
External input
External output
Result switching network
Generic structure of the datapath:
Functional units
Operand switching network
2.4 Cu trc FSMD
Datapath design
DHBK 2007
236
Typical datapath:
R
L
C
S
1 0
WA
WE
RA
1

RE
1

RA
2

RE
2

R
L
COE RFOE
1
RFOE
2
ROE
AOE SOE
OOE
> = <
Counter
Register
File
2
3

Register
Comparator ALU Barrel
shifter
Outport
Inport
F
Sh
D
2.4 Cu trc FSMD
Datapath design
DHBK 2007
237
In the datapath of previous slide a few decisions have
been taken:
Only 1 i.o. 2 result busses ALU and Barrel shifter cannot
be used concurrently
Only 2 i.o. 4 operand busses e.g. Compare and ALU work
on the same set of data
9 registers with only 2 write ports and 3 read ports
Inport can only feed the register file
2.4 Cu trc FSMD
Datapath design
DHBK 2007
238
OOE SOE D SH0 F0
RF
OE2
RE2 RA0 SH1 SH2 AOE F1 F2 ROE L R RA1 RA2
Barrel
shifter
ALU
Register
Register File
Read Port 2
Instruction format
RF
OE1
RE1 RA0 RA1 WA1 R RA2 WE WA0 WA2 S COE C L
Register File
Read Port 1
Register
File
Write Port
Counter
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31
32-bit instruction word
For reasons of simplicity, clarity and correctness, it is
possible to assign a mnemonic to a certain bit pattern
(e.g. ADD): assembly instruction
2.4 Cu trc FSMD
Datapath design
DHBK 2007
239
The size of the instruction word may be reduced, since
several operations cannot be executed concurrently
Either Register File Read Port 2, either Register Read Port
connects to the 1st Operand Bus (-1)
Either Register File Read Port 1, either Counter Read Port
connects to the 2nd Operand Bus (-1)
ALU & Shift cannot occur concurrently: 1 bit needed to
select the operator and 4 bits control the operator (-2)
When the ALU operator is active, its output may immediately
be placed on the result bus; idem for the Barrel shifter (-2)
For the counter the Count and Load operations are
exclusive (-1)
Additional limitations to concurrency may be
introduced at the cost of increased execution time
2.4 Cu trc FSMD
Datapath design
DHBK 2007
240
Design freedom
Type Fixed To be designed speed cost design
time
custom
proc.
fixed
algo
- - custom
DP
custom
Ctrl
|| ++ ||
soft IP fixed
algo
DP - DP
ext.
custom
Ctrl
| + |
ASIP algo
class
DP Ctrl DP
ext.
Ctrl
ext.
+ | +
Proc any
algo
DP Ctrl - -
++
-
|| ++
A compiler performs the same tasks as synthesis tools
(e.g. assign variables without overlapping life time to
the same register) but with less degrees of freedom,
since the hardware is fixed
2.4 Cu trc FSMD
Datapath design
DHBK 2007
241
The controller has been designed each time using the
design method for FSMs as discussed before
For a large number of states this is a tedious job
Next slides present alternative design methods, that lead
to a faster design process in several cases
2.4 Cu trc FSMD
Controller design
DHBK 2007
242
D
Clk
Q
S*=F(S,I)

Next
State
Combi-
nato-
rial
Logic
O=H(S,I)

Output
Combi-
nato-
rial
Logic
D
Clk
Q
D
Clk
Q
Standard FSM
2.4 Cu trc FSMD
Controller design
DHBK 2007
243
State
Reg
Next
state
logic
Out-
put
logic
CI
CI
SS
SS
Current
State
Next
State
Control
Input (CI)
Control
Output (CO)
Control
Signals (CS)
Status
Signals (SS)
Redrawn
Size State Reg:
log
2
n( for n states
for straightforward
and
minimum-bit-change;
n for n states for
one-hot
CS
CO
2.4 Cu trc FSMD
Controller design
DHBK 2007
244
State
Reg
Next
state
logic
Out-
put
logic
CI
CI
SS
SS
Current
State
Next
State
CS
CO
R
L
C
S
1 0
WA
WE
RA
1

RE
1

RA
2

RE
2

R
L
COE RFOE
1
RFOE
2
ROE
AOE SOE
OOE
> = <
Counter
Register
File
2
3

Register
Comparator ALU
Barrel
shifter
Outport
F
Sh
D
Critical path delay:
Find the longest combinatorial path from clock
to clock
RFOE
2
RFOE
1

State
Reg
Next
state
logic
Out-
put
logic
CI
CI
SS
SS
Current
State
Next
State
CS
CO
R
L
C
S
1 0
WA
WE
RA
1

RE
1

RA
2

RE
2

R
L
COE ROE
AOE SOE
OOE
> = <
Counter
Register
File
2
3

Register
Comparator ALU
Barrel
shifter
Outport
F
Sh
D
ClkOutStateReg + OutputLogic + AddressToOutRegFile +
BusDriver + BarrelShifter +BusDriver +Mux +
SetupInPortRegFile
2.4 Cu trc FSMD
Controller design
DHBK 2007
245
State
Reg
Next
state
logic
Out-
put
logic
CI
CI
SS
SS
Current
State
Next
State
CI
CO
CS SS
Modification 1
log
2
n
n
dec.
Properties:
* simple
design and small
next state and
output logic of
one-hot
* small number of
flip-flops of
straightforward
and minimum-
bit-change
One-hot
State
reg
CS
CO
2.4 Cu trc FSMD
Controller design
DHBK 2007
246
Modification 2
Often the state diagram shows an unconditional sequence of
states, but for a few exceptions
E.g.
Wait
100
Add2
010
Output
001
Add1
010
Start=1
0
2.4 Cu trc FSMD
Controller design
DHBK 2007
247
State
Reg
Next
state
logic
Out-
put
logic
CI
CI
SS
SS
Current
State
Next
State
CI CO
CS SS
MUX
INC
Next
State
Logic
Modification 2
CS
CO
2.4 Cu trc FSMD
Controller design
DHBK 2007
248
Advantage of modification 2:
The next state logic is very simple:
for unconditional next state: select the INC
only for conditional next state the hardware should generate the
next state
Implementation of the INC:
ripple carry chain of Half Adders
INC and State Reg together form a synchronous counter
2.4 Cu trc FSMD
Controller design
DHBK 2007
249
Modification 3
Often the state diagram contains a part that is repeated several
times subroutine
s0
s3
s4
s1
s2
s0
s1
s2
s3
s4
s5
s6
7 states
5 states

Only at run-time
it is known
which will be
the next
state following
the end of a
subroutine
stack
2.4 Cu trc FSMD
Controller design
DHBK 2007
250
State
Reg
Next
state
logic
Out-
put
logic
CI
CI
SS
SS
Current
State
Next
State
CI CO
CS SS
MUX
Stack
Modification 3
Push/
Pop
Return
State
Next
State
Logic
CS
CO
2.4 Cu trc FSMD
Controller design
DHBK 2007
251
Log
2
n
n
Dec
Next
state
logic
Out-
put
logic
CI
CI
SS
SS
Current
State
Next
State
CI CO
CS SS
MUX
Stack
Combination
Push/
Pop
State
Reg
INC
Assumption: Return state = Jump state + 1
CS
CO
2.4 Cu trc FSMD
Controller design
DHBK 2007
252
Implementation of the next state logic and the output
logic
Either construct via Karnaugh a minimal AND-OR
implementation
Either put the truth table in a ROM-table (this method is
called microprogrammed control)
2.4 Cu trc FSMD
Controller design
DHBK 2007
253
ROM
table
CI SS
Current
State
Next
State
CI CO
CS SS
MUX
Stack
ROM table
Push/
Pop
State
Reg
INC
CS
CO
2.4 Cu trc FSMD
Controller design
DHBK 2007
254
Be careful about timing!
Example:
ReadFromExternal(A);
|| sum := 0;
WHILE A <> 1
sum := sum + A;
|| ReadFromExternal(A);
Each iteration of the
WHILE loop (body, test
and decision) should be
executed in just one
clock cycle!!
A sum
LA LS
RS
Comp Add
C=1 when A<>1
Comp
A
C
No 3-state
drivers: each
bus only has
one source
2.4 Cu trc FSMD
Controller design
DHBK 2007
255
Can the controller be state based?
Example:
|| sum := 0;
WHILE A <> 1
sum := sum + A;
A sum
LA LS
RS
Comp Add
C=1 when A<>1
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
Animate sequence
A=5,2,1 sum=7
A=? Sum=?
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
5
?
?
C=?
A=? Sum=0
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
5
?
?
C=?
A=5 Sum=0
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
5
5
5
C=1
Reset is asynchronous
A=5 Sum=0
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
2
5
5
C=1
A=2 Sum=5
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
2
7
7
C=1
A=2 Sum=5
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
1
7
7
C=1
A=1 Sum=7
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
1
8
8
C=0
A=1 Sum=7
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
?
8
8
C=0
A=? Sum=8
LA LS
RS
Comp Add
s0
LA=1
RS=1
LS=0
s1
LA=1
RS=0
LS=1
C=1
C=0
?
?
?
C=?
One count too much
sum=8 i.o. 7
2.4 Cu trc FSMD
Controller design
DHBK 2007
256
Can the controller be input based?
Example:
|| sum := 0;
WHILE A <> 1
sum := sum + A;
Animate sequence
A=5,2,1 sum=7
Reset is asynchronous
A sum
LA LS
RS
Comp Add
C=1 when A<>1
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
A=? Sum=?
LA LS
RS
Comp Add
C=?
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
5 ?
?
A=? Sum=0
LA LS
RS
Comp Add
C=?
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
5 ?
?
A=5 Sum=0
LA
LS
RS
Comp Add
C=1
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
5 5
5
A=5 Sum=0
LA LS
RS
Comp Add
C=1
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
2 5
5
A=2 Sum=5
LA LS
RS
Comp Add
C=1
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
2 7
7
A=2 Sum=5
LA LS
RS
Comp Add
C=1
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
1 7
7
A=1 Sum=7
LA LS
RS
Comp Add
C=0
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
1 8
8
A=1 Sum=7
LA LS
RS
Comp Add
C=0
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
? 8
8
A=1 Sum=7
LA LS
RS
Comp Add
C=0
s0
LA=1
RS=1
LS=0
s1
RS=0
C=1
LA=1
LS=1
C=0
LA=0
LS=0
? 8
8
Result is correct.
Always check timing!
2.4 Cu trc FSMD
Controller design
DHBK 2007
257
2.4 Cu trc FSMD
State-action table
The specification of an FSMD could be done using the
traditional next state & output table
However, for large designs, this becomes not so
practical
Next slide shows the next state & output table for the
one counting application
WHILE Data <> 0 DO
ENDWHILE
Outport = OCnt
DHBK 2007
258
Next state and output table
Present
state
Next state
(Start, Status)
Data
path
output
Data path variables
00 01 10 11 Outport Data OCount Temp Mask
S
0
S
0
S
0
S
1
S
1
Z X X X X
S
1
S
2
S
2
S
2
S
2
Z Inport X X X
S
2
S
3
S
3
S
3
S
3
Z Data 0 X X
S
3
S
4
S
4
S
4
S
4
Z Data OCount X 1
S
4
S
5
S
5
S
5
S
5
Z Data OCount Data
AND
Mask
Mask
S
5
S
6
S
6
S
6
S
6
Z Data OCount
+Temp
X Mask
S
6
S
4
S
7
S
4
S
7
Z Data >>
1
OCount X Mask
S
7
S
0
S
0
S
0
S
0
Ocount Data Ocount X X
2.4 Cu trc FSMD
State-action table
DHBK 2007
259
The next state and output table do not offer a good
overview
often the next state is only dependent on a few of the inputs
often, the data path variables do not change
Hence, the same information as in the next state and
output table is presented in a more condensed form: the
state action table (See next slide)
2.4 Cu trc FSMD
State-action table
DHBK 2007
260
Present
state
Next state Control and data path
actions
Condition State Condition Actions
S
0
Start=0
Start=1
S
0
S
1
Output=Z
S
1
S
2
Data=Inport
S
2
S
3
Ocount=0
S
3
S
4
Mask=1
S
4
S
5
Temp=Data
AND Mask
S
5
S
6
Ocount=
Ocount+
Temp
S
6
Data <> 0
Data = 0
S
4
S
7
Data >> 1
S
7
S
0
Output=
OCount
2.4 Cu trc FSMD
State-action table
DHBK 2007
261
2.4 Cu trc FSMD
Algorithmic-state-machine chart
An algorithmic-state-machine chart (ASM chart) is an
alternative visualization method for the state action
table
It shows loops, conditions and next states in a way
which is easier to understand for a human being
Each row in the state action table translates to an ASM
block
ASM blocks are constructed out of three types of
elements: state boxes, decision boxes and condition
boxes
DHBK 2007
262
Unconditional
variable
assignment
State name State encoding
State box
Decision box
Condition
1 0
Condition box
Conditional
variable
assignment
2.4 Cu trc FSMD
DHBK 2007
263
Done = 0
s
0

Start = 0
0
Data = Inport
Example of an ASM block
1
2.4 Cu trc FSMD
DHBK 2007
264
An ASM block has to obey following rule:
each input combination should lead to exactly one next state
Example 1 of an invalid ASM block:
Cond1 Cond2
1 0 0 1
s
0

s
1
s
2

When Cond2=1
there are two
next states
2.4 Cu trc FSMD
DHBK 2007
265
Example 2 of an invalid ASM block:
Cond1
Cond2
0
1
s
0

s
1
s
2

0
1
When Cond1=0
and Cond2=0
there is no
next state
2.4 Cu trc FSMD
DHBK 2007
266
An ASM chart representing a state-based or Moore type
FSMD has no condition boxes, since all outputs only
depend on the state; all assignments to variables are
done in state boxes
An ASM chart representing an input-based or Mealy
type FSMD has state boxes as well as condition boxes;
variable assignments that only depend on the state are
done within the state boxes; variable assignments that
depend on input conditions are done in condition boxes
2.4 Cu trc FSMD
DHBK 2007
267
Start=1
s
0

0
Data=Inport
OCount=0
1
s
1

Data
LSB

s
2

Ocount=Ocount+1
1
s
3

0
Data=Data>>1
s
4

Data<>0
1
Output=OCount
0
s
5

State based (Moore)
DHBK 2007
268
Start=1
s
0

0
Data=Inport
OCount=0
1
s
1

Data
LSB

s
2

Output=OCount
0
s
3

Input based (Mealy)
Data<>0
1
Data=Date>>1
1
Ocount=Ocount+1
0
Only 4 states instead
of the 6 for a state
based approach
DHBK 2007
269
Chng 4. Ngn ng m t phn cng
VHDL
4.1 Gii thiu v VHDL
4.2 Tn hiu v cc kiu d liu
4.3 Cc php ton s hc v logic
4.4 Cc lnh song song v tun t
4.5 Cc cu trc tun t
4.6 Chng trnh con

DHBK 2007
270
4.1 Gii thiu v VHDL
VHDL = VHSIC Hardware Description Language
VHSIC = Very High Speed Integrated Circuit
L ngn ng lp trnh dng m t hot ng ca h
thng s
c quy nh trong chun IEEE 1076 t nm 1983
Cc ngn ng m t phn cng khc:
Verilog
Abel
DHBK 2007
271
library IEEE; -- Su dung thu vien chuan IEEE
use IEEE.STD_LOGIC_1164.ALL; --Su dung tat ca cac thanh phan trong goi STD_LOGIC_1164

entity hex2led is
Port ( HEX : in std_logic_vector(3 downto 0);
LED : out std_logic_vector(6 downto 0));
end hex2led;
-- Khai bao hoat dong cua hex2Led
architecture Behavioral of hex2led is

begin
with HEX SELect
LED<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0

end Behavioral;

DHBK 2007
272
4.1 Gii thiu v VHDL
V d 1
Thit k mch Test vi 3 u vo 8-bit (In1, In2, In3)
v hai u ra 1 bit (Out1, Out2). Out1=1 khi In1=In2
v Out2=1 khi In1 = In3

In1
In2
In3
Test
Out1
Out2
Compare
A
B
EQ
Compare
A
B
EQ
Test l mt khi gm 2 bn copy ca khi compare
DHBK 2007
273
A
B
EQ
Compare
4.1 Gii thiu v VHDL
V d 1
A[0]
B[0]
A[1]
B[1]
A[7]
B[7]
EQ
XNOR
AND
Thit k khi compare dng mch t hp
DHBK 2007
274
4.1 Gii thiu v VHDL
V d 1
Thit k khi compare dng VHDL
- -Eight bit comparator
entity Compare is
port( A,B: in bit_vector(0 to 7);
EQ: out bit);
end Compare;

architecture Behav1 of Compare is
begin
EQ <= 1 when (A=B) else 0;
end Behav1;
Entity xc nh giao din
vi bn ngoi ca khi cn thit k
u vo v ra c gi l port
Architecture miu t hot ng
v cu trc bn trong ca
khi cn thit k
Ch :
-Mt entity c th c nhiu architecture, mi architecture l mt
cch th hin khc nhau ca cng mt chc nng
- Cc Ports l vector c chiu: vo (in), ra (out), hoc c vo c ra (inout)
DHBK 2007
275
4.1 Gii thiu v VHDL
Component v Instantiation
Biu din Test bng VHDL

entity Test is
port( In1,In2,In3: in bit_vector(0 to 7);
Out1,Out2: out bit);
end Test;

architecture Struct1 of Test is
component Comparator is
port( X,Y: in bit_vector(0 to 7);
Z: out bit);
end component;
begin
Compare1: Comparator port map (X=>In1, Y=>In2, Z=>Out1);
Compare2: Comparator port map (X=>In1,Y=>In3,Z=>Out2);
end Struct1;
2 bn copy ca cng mt
component
Comparator
Ch :
- Hai bn comparator chy song song vi nhau !!!
- y l architecture miu t cu trc ca entity Test
DHBK 2007
276
4.1 Gii thiu v VHDL
Cu hnh (Configuration)
Khi mt entity c nhiu architectures, ta s x dng
architecture no?
Lm th no gn Components vi Entities?
-- Configuration information: architecture selection
-- and component-entity binding

configuration Build1 of Test is
for Struct1
for Compare1: Comparator use entity Compare(Behav1)
port map (A => X, B => Y, EQ => Z);
end for;
for others: Comparator use entity Compare(Behav1)
port map (A => X, B => Y, EQ => Z);
end for;
end for;
end Build1;
DHBK 2007
277
4.1 Gii thiu v VHDL
Khai bo Entity v Architecture
ENTITY:

entity Entity_name is
port(Signal_name: in Signal_type;
Signal_name: out Signal_type);
end Entity_name;
ARCHITECTURE:

architecture Architecture_name of Entity_name is
Khai bo cc tn hiu cc b;
Khai bo cc components;
begin
Cc cu lnh;
end Architecture_name;
DHBK 2007
278
4.1 Gii thiu v VHDL
Khai bo component
COMPONENT:
component Component_name is
port( Signal_name: in Signal_type;
Signal_name: out Signal_type);
end component;
Khai bo copy ca COMPONENT :

Instance_name: Component_name
port map (Signal_list);

Hoc cch th 2, copy trc tip:

Instance_name: Entity_name(Architecture_name)
DHBK 2007
279
4.1 Gii thiu v VHDL
Khai bo cu hnh
CONFIGURATION:

configuration Config_name of Entity_name is
for Architecture_name
for Instance_name: Component_name use entity
Entity_name(Architecture_name)
end for;
end for;
end Config_name;
DHBK 2007
280
4.1 Gii thiu v VHDL
V d 2
Biu din cng AND bng VHDL
A
B
C
Y
-- 3-input AND gate

entity AND3 is
port ( A,B,C: in bit;
Y: out bit);
end AND3;

architecture RTL of AND3 is
begin
Y <= 1 when ((A=1) and (B=1) and (C=1)) else 0;
end RTL;
DHBK 2007
281
4.1 Gii thiu v VHDL
V d 2
Biu din cng OR bng VHDL

A
B
C
Y
-- 3-input OR gate

entity OR3 is
port ( A,B,C: in bit;
Y: out bit);
end OR3;

architecture RTL of OR3 is
begin
Y <= 0 when ((A=0) and (B=0) and (C=0)) else 1;
end RTL;
DHBK 2007
282
4.1 Gii thiu v VHDL
V d 2
Biu din cng INV bng VHDL
-- INV gate

entity INV is
port ( A: in bit;
Y: out bit);
end INV;

architecture RTL of INV is
begin
Y <= 1 when (A=0) else 0;
end RTL;
A
Y
DHBK 2007
283
4.1 Gii thiu v VHDL
V d 3
Thit k b MUX 2-1 dng VHDL
A
S
B
Y
entity MUX21 is
port ( A,B,S: in bit;
Y: out bit);
end MUX21;
architecture Behav of MUX21 is
begin
Y <= A when (S=1) else B;
end Behav;
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architecture Struct of MUX21 is
signal U,V,W : bit;
component AND2
port ( X,Y: in bit;
Z: out bit);
end component;
component OR2
port ( X,Y: in bit;
Z: out bit);
end component;
component INV
port ( X: in bit;
Z: out bit);
end component;
begin
Gate1: INV port map (X=>S,Z=>U);
Gate2: AND2 port map (X=>A,Y=>S,Z=>W);
Gate3: AND2 port map (X=>U,Y=>B,Z=>V);
Gate4: OR2 port map (X=>W,Y=>V,Z=>Y);
end Struct;
4.1 Gii thiu v VHDL
V d 3

A
S
B
Y
A
S
B
Y
U
V
W
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4.1 Gii thiu v VHDL
V d 3
Gi s ta mun s dng cc cng AND, OR v INV
v d 2 trong MUX21
configuration Use3InputGates of MUX21 is
for Behav
end for;
for Struct
for Gate1:INV use entity INV(RTL)
port map (A=>X,Y=>Z);
end for;
for All:AND2 use entity AND3(RTL)
port map (A=>X,B=>Y,C=>1,Y=>Z);
end for;
for Gate4:OR2 use entity OR3(RTL)
port map (A=>X,B=>Y,C=>0,Y=>Z);
end for;
end for;
end Use3InputGates;
Entities
A
B
C
Y
A
Y
Components
X

Y
Z
X
Z
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4.1 Gii thiu v VHDL
To Testbench
Testbench l entity dng m phng v kim tra thit
k
MUX21
A
B
Y
S
entity Testbench is
end Testbench;
Testbench khng c port
architecture BehavTest of Testbench is
Signal In1,In2,Select,Out : bit;
begin
mux21_copy: entity MUX21(Behav) port map (In1, In2, Select, Out);
Thu: process is
begin
In1<=0;In2<=1;Select<=0; wait for 20 ns;
Select<=1; wait for 20 ns;
In1<=1;In2<=0; wait for 20 ns;
...
end process;
end BehavTest;
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4.1 Gii thiu v VHDL
S dng li
Thng thng, cc b phn ca thit k ny c th c
dng li trong cc thit k khc
Cc sn phm cng nghip thng bao gm 95% b
phn dng li v ch c 5% l phi thit k mi
VHDL khuyn khch dng li bng khi nim
Packages
Mt Package cha cc nh ngha v hng s, khai
bo component, cc kiu d liu ca ngi s dng, cc
chng trnh con vit bng VHDL
Package c ct trong Library: library thc cht
l mt th mc
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4.1 Gii thiu v VHDL
S dng li
Package interface declaration:

package Package_name is
-- constants
-- user defined types
-- component declarations
-- sub programs
end Package_name;
How to use a package?

use Library_name.Package_name.all;

U1: entity Package_name.Entity_name(Architecture_name);
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4.2 Tn hiu v cc kiu d liu:
Cc kiu d liu c nh ngha
package Standard is
type Bit is (0,1);
type Boolean is (False, True);
type Character is (--ASCII set);
type Integer is range implementation_defined;
type Real is range implementation_defined;
type Bit_vector is (--array of bits);
type String is (--array of characters);
type Time is range implementation_defined;
end Standard;
Bit, Boolean v Character l kiu d liu lit k
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V d v khai bo cc kiu s nguyn:
type Year is range 0 to 99;
type Memory_address is range 65535 downto 0;
V d v khai bo cc kiu s thc
type Probability is range 0.0 to 1.0;
type Input_level is range -5.0 to 5.0;
Khai bo bit_vector, gi tr c t trong du nhy kp
constant State1: bit_vector(4 downto 0) := 00100;
Kiu chui String l mt chui k t characters; gi tr ca n
c t trong du nhy kp
constant Error_message: string
:= Unknown error: ask your poor sysop for help;
MSB, bit 4
LSB
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ARCHITECTURE test OF test IS
BEGIN
PROCESS(X)
VARIABLE a : INTEGER;
BEGIN
a := 1; --Ok 1
a := -1; --Ok 2
a := 1.0; --error 3
END PROCESS;
END test;
ARCHITECTURE test OF test IS
SIGNAL a : REAL;
BEGIN
a <= 1.0; --Ok 1
a <= 1; --error 2
a <= -1.0E10; --Ok 3
a <= 1.5E-20; --Ok 4
a <= 5.3 ns; --error 5
END test;
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Kiu Time l kiu vt l:
type Time is range implementation_defined
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
Primary unit:
resolution limit
Secondary units
c s dng rt nhiu trong chy m phng
wait for 20 ns;
constant Sample_period: time := 2 ms;
constant Clock_period: time := 50 ns;
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Cc kiu d liu ca ngi s dng
Ngi s dng c th nh ngha kiu vt l nh sau:
type Length is range 0 to 1E9
units
um;
mm = 1000 um;
m = 1000 mm;
km = 1000 m;
mil = 254 um;
inch = 1000 mil;
foot = 12 inch;
yard = 3 foot;
end units;
Primary unit:
resolution limit
Metric secondary units
Imperial secondary units
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Kiu lit k ca ngi s dng
Ngi s dng c th nh ngha ku lit k nh sau:

type FSM_states is (reset, wait, input, calculate, output);
constant reset: bit_vector := 10000;
constant wait: bit_vector := 01000;
constant input: bit_vector := 00100;
constant calculate: bit_vector := 00010;
constant output: bit_vector := 00001;
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PACKAGE example IS
TYPE current IS RANGE 0 TO 1000000000
UNITS
na; --nano amps
ua = 1000 na; --micro amps
ma = 1000 ua; --milli amps
a = 1000 ma; --amps
END UNITS;
TYPE load_factor IS (small, med, big );
END example;

USE WORK.example.ALL;
ENTITY delay_calc IS
PORT ( out_current : OUT current;
load : IN load_factor;
delay : OUT time);
END delay_calc;
ARCHITECTURE delay_calc OF delay_calc IS
BEGIN
delay <= 10 ns WHEN (load = small) ELSE
delay <= 20 ns WHEN (load = med) ELSE
delay <= 30 ns WHEN (load = big) ELSE
delay <= 10 ns;
out_current <= 100 ua WHEN (load = small)ELSE
out_current <= 1 ma WHEN (load = med) ELSE
out_current <= 10 ma WHEN (load = big) ELSE
out_current <= 100 ua;
END delay_calc;
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Kiu mng array
type 1D_array is array (1 to 10) of integer;
type 2D_array is array (5 downto 0, 1 to 10) of real;

TYPE data_bus IS ARRAY(0 TO 31) OF BIT;
VARIABLE X: data_bus;
VARIABLE Y: BIT;
Y := X(0);
Y := X(15);
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Kiu bn ghi record
TYPE optype IS ( add, sub, mpy, div, jmp );

TYPE instruction IS
RECORD
opcode : optype;
src : INTEGER;
dst : INTEGER;
END RECORD;
PROCESS(X)
VARIABLE inst : instruction;
VARIABLE source, dest : INTEGER;
VARIABLE operator : optype;
BEGIN
source := inst.src; --Ok line 1
dest := inst.src; --Ok line 2
source := inst.opcode; --error line 3
operator := inst.opcode; --Ok line 4
inst.src := dest; --Ok line 5
inst.dst := dest; --Ok line 6
inst := (add, dest, 2); --Ok line 7
inst := (source); --error line 8
END PROCESS;
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Standard logic
library IEEE;
use IEEE.Std_logic_1164.All;

type std_logic is (
U, -- uninitialized e.g. after power-up
X, -- strongly driven unknown e.g. after setup violation
0, -- strongly driven logic zero
1, -- strongly driven logic one
Z, -- high impedance e.g. not driven at all
W, -- weakly driven unknown
L, -- weakly driven logic zero
H, -- weakly driven logic one
-); -- dont care
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE memory IS
CONSTANT width : INTEGER := 3;
CONSTANT memsize : INTEGER := 7;
TYPE data_out IS ARRAY(0 TO width) OF std_logic;
TYPE mem_data IS ARRAY(0 TO memsize) OF data_out;
END memory;

LIBRARY IEEE;
USE WORK.memory.ALL;
ENTITY rom IS
PORT( addr : IN INTEGER;
data : OUT data_out;
cs : IN std_logic);
END rom;
Standard logic
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ARCHITECTURE basic OF rom IS
CONSTANT z_state : data_out := (Z, Z, Z, Z);
CONSTANT x_state : data_out := (X, X, X, X);
CONSTANT rom_data : mem_data :=
( ( 0, 0, 0, 0),
( 0, 0, 0, 1),
( 0, 0, 1, 0),
( 0, 0, 1, 1),
( 0, 1, 0, 0),
( 0, 1, 0, 1),
( 0, 1, 1, 0),
( 0, 1, 1, 1) );
BEGIN
ASSERT addr <= memsize
REPORT addr out of range
SEVERITY ERROR;
data <= rom_data(addr) AFTER 10 ns WHEN cs = 1 ELSE
data <= z_state AFTER 20 ns WHEN cs = 0 ELSE
data <= x_state AFTER 10 ns;
END basic;

Standard logic
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Gn tn hiu
Gn theo v tr, khng gn theo ch s ca mng
signal Down: std_logic_vector (3 downto 0);
signal Up: std_logic_vector (0 to 3);

Up <= Down;

Phng n no sau y l phng n ng?
Up(0)

Up(1)

Up(2)

Up(3)
Down(3)

Down(2)

Down(1)

Down(0)
OR
Up(0)

Up(1)

Up(2)

Up(3)
Down(0)

Down(1)

Down(2)

Down(3)
Tng ng theo v tr
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Gn tn hiu
C th gn bin cho mt phn ca mng
Ch chiu (to hoc downto) phi ging nhau trong cc
php khai bo
signal Bus: std_logic_vector (7 downto 0);
signal A: std_logic_vector (0 to 3);

Cu lnh no sau y ng?
Bus(0 to 3) <= A;
Bus <= A;
Bus(3 downto 0) <= A;
Bus(5 downto 4) <= A(0 to 1);
Chiu bus khng ging nh khai bo
Kch thc mng khc nhau
OK! Bus(3) is driven by A(0)
OK! Bus(5) is driven by A(0)
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Gn tn hiu
C th kt hp hai mng khc nhau
signal Byte_bus: std_logic_vector(7 downto 0);
signal Nibble_busA, Nibble_busB: std_logic_vector(3 downto 0);

Byte_bus <= Nibble_busA & Nibble_busB;
Byte_bus(7)
Byte_bus(6)
Byte_bus(5)
Byte_bus(4)
Byte_bus(3)
Byte_bus(2)
Byte_bus(1)
Byte_bus(0)
Nibble_busA(3)
Nibble_busA(2)
Nibble_busA(1)
Nibble_busA(0)
Nibble_busB(3)
Nibble_busB(2)
Nibble_busB(1)
Nibble_busB(0)
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Gn tn hiu
Not supported by all synthesis tools!!
signal X,Y,Z,T: std_logic_vector(3 downto 0);
signal A,B,C: std_logic;

X <= (A,B,C,C); -- correspondence by position
Y <= (3 => A, 1 downto 0 => C, 2 => B);
Z <= (3 => A, 2 => B, others => C);
T <= (others => 0); -- initialization irrespective of width of T
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Tham s dng chung (Generic)
entity General_mux is
generic (width : integer);
port ( Input : in std_logic_vector (width - 1 downto 0);
Select : in integer range 0 to width - 1;
Output : out std_logic);
end General_mux;
Dng truyn tham s t entity ti cc bn copy ca n
Cc bn copy c th c cc gi tr tham s khc nhau
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LIBRARY IEEE;

ENTITY test IS
GENERIC(rise, fall : TIME; load : INTEGER);
PORT ( ina, inb, inc, ind : IN std_logic;
out1, out2 : OUT std_logic);
END test;

ARCHITECTURE test_arch OF test IS
COMPONENT AND2
GENERIC(rise, fall : TIME; load : INTEGER);
PORT ( a, b : IN std_logic;
c : OUT std_logic);
END COMPONENT;
BEGIN
U1: AND2 GENERIC MAP(10 ns, 12 ns, 3 )
PORT MAP (ina, inb, out1 );
U2: AND2 GENERIC MAP(9 ns, 11 ns, 5 )
PORT MAP (inc, ind, out2 );
END test_arch;
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LIBRARY IEEE;
ENTITY test IS
GENERIC(rise, fall : TIME;
GENERIC(load : INTEGER);
PORT ( ina, inb, inc, ind : IN std_logic;
PORT ( out1, out2 : OUT std_logic);
END test;
ARCHITECTURE test_arch OF test IS
COMPONENT and2
GENERIC(rise, fall : TIME := 10 NS;
GENERIC(load : INTEGER := 0);
PORT ( a, b : IN std_logic;
PORT ( c : OUT std_logic);
END COMPONENT;
BEGIN
U1: and2 GENERIC MAP(10 ns, 12 ns, 3 )
PORT MAP (ina, inb, out1 );
U2: and2 PORT MAP (inc, ind, out2 );
END test_arch;

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Thuc tnh (attributes)
TYPE state IS (0 TO 7);

4 thuc tnh (attributes) c nh ngha sn

_ TLEFT, which returns the left bound of a type or subtype
_ TRIGHT, which returns the right bound of a type or subtype
_ THIGH, which returns the upper bound of a type or subtype
_ TLOW, which returns the lower bound of a type or subtype

PROCESS(x)
SUBTYPE smallreal IS REAL RANGE -1.0E6 TO 1.0E6;
VARIABLE q : real;
BEGIN
q := smallrealLEFT; -- use of left returns 1.0E6
END PROCESS;

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Thuc tnh (attributes)
PROCESS(a)
TYPE bit4 IS ARRAY(0 TO 3) of BIT;
TYPE bit_strange IS ARRAY(10 TO 20) OF BIT;
VARIABLE len1, len2 : INTEGER;
BEGIN
len1 := bit4LENGTH; -- returns 4
len2 := bit_strangeLENGTH; -- returns 11
END PROCESS;
Xem VHDL programming by example bit chi tit hn v thuc tnh
DHBK 2007
310
4.3 Cc php ton s hc v logic:
Cc php ton logic
Cc php ton logic gm: not, and, or, xor, nand, nor
Th t u tin:
not c thc hin u tin
Cc lnh cn li c cng mc u tin
Cc php ton logic c dng cho cc kiu d liu sau
: bit, bit_vector, boolean, std_logic, std_logic_vector,
std_ulogic, std_ulogic_vector
Cc php ton logic c th c dng vi mng:
Cc mng phi c cng kch thc
Cc phn t ca mng tng ng theo v tr
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Cc php ton logic
library IEEE;
use IEEE.Std_Logic_1164.All;

entity Gate is
port( A,B,C: in std_logic;
Z: out std_logic);
end Gate;

architecture Logical of Gate is
begin
Z <= A and not(B or C);
end Logical;
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Cc php ton logic
library IEEE;

entity Gate is
generic(width : integer range 0 to 31);
port( A,B,C: in std_logic_vector(width-1 downto 0);
Z: out std_logic_vector(width-1 downto 0));
end Gate;

architecture Logical of Gate is
begin
Z <= A and not(B or C);
end Logical;
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Cc php ton s hc v logic:
Cc php ton so snh
Cc php ton so snh gm: <, <=, =>, >, =, /=
Kt qu ca php so snh l kiu boolean
Hai ton hng phi c cng kiu d li
Php ton so snh c th c dng cho mng
Mng c th c kch thc khc nhau!
Cc phn t ca mng s c so snh tng bit, t tri sang
phi
Bit vector c th c so snh nu nh c cng di v khi
so snh gi tr ca bit vector s c i sang s nguyn
khng du so snh
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Cc php ton so snh
library IEEE

entity Compare is
port( A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(0 to 4);
Z: out boolean);
end Compare;

architecture Relational of Compare is
begin
Z <= TRUE when A<B else FALSE;
end Relational;

entity Testbench
end entity Testbench;

architecture Build1 of Testbench is
signal A: std_logic_vector(3 downto 0) := 1110;
signal B: std_logic_vector(0 to 4) := 10111;
signal Z: boolean;
begin
DUT: entity Compare(Relational)
port map (A => A, B => B, Z => Z);
end Build1;
What is the
value of Z?
TRUE?
FALSE?
1110
is compared to
1011
by bit position
from left to
right;
in the 2nd
position
A(2) > B(1)
hence (A<B)
is FALSE
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Cc php ton s hc
Cc php ton s hc gm: +, -, *, /, ** (exponential),
abs (absolute value), mod (modulus), rem (remainder)
Cc php ton ny dng cho kiu s nguyn v s thc
(tr mod and rem khng dng cho s thc), khng dng
cho kiu bit vector
C hai ton hng phi c cng kiu d liu v c th c
di gi tr khc nhau
Mt bin kiu vt l (v d: time) c th nhn vi mt
s nguyn v mt s thc, kt qu s vn l kiu vt l
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Cc php ton s hc
entity Add is
port ( A,B: in integer range 0 to 7;
Z: out integer range 0 to 14);
end Add;

architecture Behav of Add is
begin
Z <= A + B;
end Behav;
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4.4 Cc lnh song song v tun t :
Cc lnh song song
Tt c cc lnh trong architecture u c thc hin
ng thi (song song) ging nh trong phn cng, cc
cng logic hot ng ng thi
entity Concurrent is
port ( A,B,C,D: in std_logic;
Y,Z: out std_logic);
end Concurrent;

architecture Struct of Concurrent is
begin
NAND1: entity NAND2 port map (A,B,Y);
NAND2: entity NAND2 port map (C,D,Z);
end Struct;
A
B
C
D
Y
Z
Schematic:
Mch s hot ng th no nu nh khai bo NAND1 sau NAND2?
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port ( A,B,C,D: in std_logic;
end Concurrent;

begin
NAND2: entity NAND2 port map (C,D,Z);
NAND1: entity NAND2 port map (A,B,Y);
end Struct;
A
B
C
D
Y
Z
Schematic:
Mch vn hot ng nh c!!!
Cc lnh song song
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Cc lnh song song
A
B
D
Z
Schematic:
T1
port ( A,B, D: in std_logic;
Z: out std_logic);
end Concurrent;

signal T1: std_logic;
begin
NAND2: entity NAND2 port map (T1,D,Z);
NAND1: entity NAND2 port map (A,B,T1);
end Struct;
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Process
Nhiu khi phng trnh t hp trong mt cu lnh rt
phc tp, v d:
entity Complex is
port( A,B,C,D,E,F,G,H,I,J:
in std_logic;
end Complex;

architecture Struct of Complex is
begin
Y <= ((A nand B) nand (C nand D))
when (S = 1) else
((E nand F) nand (G nand H));
Z <= I nand J;
end Struct;
A
B
C
D
E
F
G
H
S
Y
I
J
Z
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Process
V vy ngi ta a ra khi nim process:
Mt process hot ng nh mt cu lnh v c thc hin
ng thi vi cc cu lnh khc
Bn trong mt process, cc lnh c thc hin tun t theo
th t t trn xung di. iu ny gip cho vic chia nh
mt lnh rt phc tp thnh cc lnh n gin hn.
truyn d liu gia cc lnh trong mt process chng ta
c th dng cc bin tm thi variables. Cc bin ny khng
nht thit phi l mt tn hiu vt l no.
process s c thc hin li mi khi c mt s kin (event)
xy ra i vi mt tn hiu (signal) no trong danh sch tn
hiu nhy cm (sensitivity list).
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Process
C php khai bo Process:

Process_name: process (sensitivity_list) is
-- variable declarations;
begin
-- sequential commands
end process;
C php khai bo bin:

variable Variable_name: type;
C php gn gi cho mt bin:

Variable_name := expression;
Gn bin :=
Gn tn hiu <=
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Process
entity Complex is
port( A,B,C,D,E,F,G,H,I,J:
in std_logic;
end Complex;

architecture Struct of Complex is
begin
Y_process: process (A,B,C,D,E,F,G,H,S) is
variable T1,T2: std_logic;
begin
if (S=1) then
T1 := A nand B;
T2 := C nand D;
else
T1 := E nand F;
T2 := G nand H;
end if;
Y <= T1 nand T2;
end process;
Z <= I nand J;
end Struct;
A
B
C
D
E
F
G
H
S
Y
I
J
Z
T1 and T2 have no
physical meaning since
each refers to 2 different
physical wires
T1 T2
Sensitivity list
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324
Xt v d sau:
Example: process (A,B,M) is
begin
Y <= A;
M <= B;
Z <= M;
end process;
1. Gi thit B c gi tr mi B
2. Process Example c thc hin. Cc tn hiu ra c ghi nh:
Y <= A; M <= B; Z <= M;
Gi tr M c !!! M ch nhn
gi tr mi cui process
3. Process Example tm dng
Y, M v Z nhn cc gi tr mi Y, M, Z.
4. V M trong sensitivity list, process Example li c thc hin
5. Process Example thc hin: Y <= A; M <= B; Z <= M;
6. Y, M and Z nhn gi tr mi Y, M, Z.
7. Khng c tn hiu no trong sensitivity list thay i, process dng
Process
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4.5 Cc cu trc tun t
Cc cu trc tun t ch c s dng trong process v
chng trnh con!!!
Cc cu trc tun t bao gm: IF, CASE, FOR, NEXT,
EXIT, WAIT, ASSERT
IF statement:

if condition then
-- sequential statements
else
end if;
multiple IF statements:

if condition1 then
elsif condition2 then
elsif condition3 then
else
end if;
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4.5 Cc cu trc tun t
case Expression is
when Value_1 =>
when Value_2 =>
-- etc.
end case;
Example: process (A,B,C,X) is
begin
case X is
when 0 to 4 =>
Z <= B;
when 5 =>
Z <= C;
when 7 | 9 =>
Z <= A;
when others =>
Z <= 0;
end case;
end process;
Yu cu:
1. Tt c cc trng hp
phi c xc nh
2. Gi tr value phi l hng s
v phi bit khi thit k
3. Gi tr phi c cng kiu vi
expression
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4.5 Cc cu trc tun t
TYPE vectype IS ARRAY(0 TO 1) OF BIT;
VARIABLE bit_vec : vectype;

CASE bit_vec IS
WHEN 00 =>
RETURN 0;
WHEN 01 =>
RETURN 1;
WHEN 10 =>
RETURN 2;
WHEN 11 =>
RETURN 3;
END CASE;
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4.5 Cc cu trc tun t
for I in 0 to 3 loop
end loop;
1. Khng c khai bo bin dng trong vng for v khng
c gn gi tr cho bin
Ch :
FOR i IN 1 to 10 LOOP
i_squared(i) := i * i;
END LOOP;

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4.5 Cc cu trc tun t
entity General_mux is
generic (width : integer);
port ( Input : in std_logic_vector (width - 1 downto 0);
Select : in integer range 0 to width - 1;
Output : out std_logic);
end General_mux;

architecture Behav of General_mux is
begin
Selector: process (Input, Select) is
begin
for I in 0 to width-1 loop
if Select=I then
Output <= Input(I);
end if;
end loop;
end process;
end Behav;
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4.5 Cc cu trc tun t
PROCESS(A, B)
CONSTANT max_limit : INTEGER := 255;
BEGIN
FOR i IN 0 TO max_limit LOOP
IF (done(i) = TRUE) THEN
NEXT;
ELSE
done(i) := TRUE;
END IF;
q(i) <= a(i) AND b(i);
END LOOP;
END PROCESS;

Cu trc NEXT c dng b qua vng lp hin ti nhy ti
vng lp tip theo
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331
4.5 Cc cu trc tun t
Cu trc EXIT c dng thot ra khi vng lp for
PROCESS(a)
variable int_a : integer;
BEGIN
int_a := a;
FOR i IN 0 TO max_limit LOOP
IF (int_a <= 0) THEN -- less than or
EXIT; -- equal to
ELSE
int_a := int_a -1;
q(i) <= 3.1416 / REAL(int_a * i); -- signal
END IF; -- assign
END LOOP;
y <= q;
END PROCESS;
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4.5 Cc cu trc tun t
PROCESS
BEGIN
WAIT UNTIL clock = 1 AND clockEVENT;
q <= d;
END PROCESS;
PROCESS
BEGIN
WAIT ON a; -- 1.
.
WAIT ON b; -- 2.
.
END PROCESS;
WAIT FOR 10 ns;
WAIT FOR ( a * ( b + c ));
DHBK 2007
333
4.5 Cc cu trc tun t
Bin (Variables)
Variable ch c s dng trong process hoc chng
trnh con
Gi tr ca variable c cp nht ngay lp tc trong
khi gi tr ca tn hiu signal s c cp nht khi
process kt thc
Bin v tn hiu c th c gn gi tr cho nhau
Bin ch c dng tm thi trong process, nu gi tr
ca n mun c truy cp ngoi process ta phi gn
gi tr cho mt tn hiu
DHBK 2007
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LIBRARY IEEE;
USE IEEE.std_logic_1164ALL;

ENTITY mux IS
PORT (I0, I1, I2, I3, A, B : IN std_logic;
Q : OUT std_logic);
END mux;

ARCHITECTURE mux_behave OF mux IS
SIGNAL sel : INTEGER RANGE 0 TO 3;
BEGIN
B : PROCESS(A, B, I0, I1, I2, I3)
BEGIN
sel <= 0;
IF (A = 1) THEN sel <= sel + 1; END IF;
IF (B = 1) THEN sel <= sel + 2; END IF;
CASE sel IS
WHEN 0 =>
Q <= I0;
WHEN 1 =>
Q <= I1;
WHEN 2 =>
Q <= I2;
WHEN 3 =>
Q <= I3;
END CASE;
END PROCESS;
END mux_behave;
Tm ch sai trong on m !
4.5 Cc cu trc tun t
Bin (Variables)
DHBK 2007
335

4.5 Cc cu trc tun t
Biu din sn ln ca xung nhp

Tm chc nng ca entity What

entity What is
port (D,Clk: in std_logic;
Q: out std_logic);
end What;

architecture RTL of What is
begin
process (D, Clk) is
begin
if (Clk=1) then
Q <= D;
end if;
end process;
end RTL;
With a latch, not with a D-flip-flop!!
When a Clk-event occurs and Clk is low, nothing happens
When a Clk-event occurs and Clk is high, the D input is copied
to the Q output
When a D-event occurs and Clk is high, the D input is copied to
the Q output => hence a latch: when Clk is high, Q follows D
Since there is no ELSE part
the previous Q value has
to be remembered for the case
where Clk=0.
The synthesis tool will hence
infer a latch instead of just
combinatorial logic!!!
Beware of unintended latches
when ELSE parts are omitted
DHBK 2007
336

Cch 1: WAIT UNTIL

entity DFlipFlop is
Q: out std_logic);
end DFlipFlop;

architecture RTL of DFlipFlop is
begin
process is
begin
wait until Clkevent and Clk=1;
Q <= D;
end process;
end RTL;
This is not synthesisable

4.5 Cc cu trc tun t

DHBK 2007
337

Cch 2: Sensitivity list

entity DFlipFlop is
Q: out std_logic);
end entity DFlipFlop;

architecture RTL of DFlipFlop is
begin
process (D,Clk) is
begin
if (Clkevent and Clk=1) then
Q <= D;
end if;
end process;
end architecture RTL;

4.5 Cc cu trc tun t

DHBK 2007
338
4.5 Cc cu trc tun t
Biu din Finite State Machine
Wait
00
Up1
01
Up2
10
Up3
11
Down3
11
Down2
10
Down1
01
Start=0
Start=1
Up=0
Start=1
Up=1
Up Start
Next
state
logic
Out
put
logic
State
Reg
Reset
Output
NextState
CurrentState
DHBK 2007
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Wait
00
Up1
01
Up2
10
Up3
11
Down3
11
Down2
10
Down1
01
Start=0
Start=1
Up=0
Start=1
Up=1
entity FSM is
port ( Start, Up, Reset, Clk: in std_logic;
Output: out std_logic_vector(0 to 1));
end FSM;

architecture Behav of FSM is
type FSM_States is (Wait,Up1,Up2,Up3,Down1,Down2,Down3);
signal CurrentState, NextState : FSM_States;
begin
OutputLogic:
process(CurrentState) is
end process;
NextStateLogic:
process(CurrentState,Start,Up) is

end process;
StateRegister:
process(NextState,Clk,Reset) is

end process;
end Behav;
4.5 Cc cu trc tun t
DHBK 2007
340
Wait
00
Up1
01
Up2
10
Up3
11
Down3
11
Down2
10
Down1
01
Start=0
Start=1
Up=0
Start=1
Up=1
OutputLogic:
process(CurrentState) is
begin
case CurrentState is
when Wait =>
Output <= 00;
when Up1|Down1 =>
Output <= 01;
when Up2|Down2 =>
Output <= 10;
when Up3|Down3 =>
Output <= 11;
end case;
end process;
4.5 Cc cu trc tun t
DHBK 2007
341
Wait
00
Up1
01
Up2
10
Up3
11
Down3
11
Down2
10
Down1
01
Start=0
Start=1
Up=0
Start=1
Up=1
NextStateLogic:
process(CurrentState,Start,Up) is
begin
case CurrentState is
when Wait =>
if (Start=0) then
NextState <= Wait;
elsif (Up=1) then
NextState <= Up1;
else
NextState <= Down3;
end if;
when Up1 =>
NextState <= Up2;
when Up2 =>
NextState <= Up3;
when Up3|Down1 =>
NextState <= Wait;
when Down3 =>
NextState <= Down2;
when Down2 =>
NextState <= Down1;
end case;
end process;
4.5 Cc cu trc tun t
DHBK 2007
342
Wait
00
Up1
01
Up2
10
Up3
11
Down3
11
Down2
10
Down1
01
Start=0
Start=1
Up=0
Start=1
Up=1
StateRegister:
process(NextState,Clk,Reset) is
begin
if Reset=1 then
CurrentState <= Wait;
elseif (Clkevent and Clk=1) then
CurrentState <= NextState;
end if;
end process;
4.5 Cc cu trc tun t
DHBK 2007
343
4.6 Chng trnh con
Gm 2 loi: th tc (procedure) v hm (function)
Th tc: c th tr v nhiu gi tr, c th c cc bin s
l cc tn hiu vo, ra hoc vo\ra
Hm: ch tr v mt gi tr v tt c cc bin s ch c
th l tn hiu vo
Th tc v hm c 2 loi: song song v tun t. Th tc
hoc hm song song c t ngoi process v th tc
hoc hm tun t ch c t trong process
Cc lnh trong chng trnh con c thc hin tun t
ging nh process
DHBK 2007
344
4.6 Chng trnh con
ENTITY convert IS
PORT(I1 : IN log8; --line 2
O1 : OUT INTEGER); --line 3
END convert;
ARCHITECTURE behave OF convert IS
FUNCTION vector_to_int(S : log8) --line 4
RETURN INTEGER is --line 5
VARIABLE result : INTEGER := 0; --line 6
BEGIN
FOR i IN 0 TO 7 LOOP --line 7
result := result * 2; --line 8
IF S(i) = 1 THEN --line 9
result := result + 1; --line 10
END IF;
END LOOP;
RETURN result; --line 11
END vector_to_int;
BEGIN
O1 <= vector_to_int(I1); --line 12
END behave;
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4.6 Chng trnh con
V d khai bo th tc:

procedure increment_reg (variable reg : inout word_32; constant
incr : in integer := 1);

V d gi th tc:

increment_reg(index_reg, offset2); -- add value to index_reg
increment_reg(prog_counter); -- add 1 (default) to prog_counter

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