PVP_bk3i1_k50

MC LC :

Ngy nay cng ngh vi in t tr thnh m t lnh v c pht tri n v c r t nhi u cc nc trn th gii ch trng pht trin.Ti sao n li c ch trng n vy,xt v phm vi ng dng ta thy h Nhng c lin quan,nh hng n nhiu lnh vc trong i sng. Trong sinh hot ca con ngi,n lm cho cuc sng c a con ngi ngy cng ti n nghi,thoi mi.s xut hin hng lot cc thit b phc v nhu cu i sng ca con ngi khng ch tng v s lng m cn tng v tnh nng,cht l ng v an ton nh my git,t lnh,l vi sng Trong sn xut,n lm tng nng sut lao ng,gi m sc lao ng c a con ng i,thay con ngi hot ng nhng ni c iu kin ht sc khc nhitV n lin quan n cc ng dng cng ngh cao nh v tr Vi tm quan trng ca cng ngh vi in t.N xng ng l lnh v c mang t m chi n lc trong s pht trin ca cc nc trn th gii.Nc ta cng khng ngo i l ,vi c xc nh c tm quan trng .Nh nc cng u tin trong u t,vic hc,nghin cu.Nhiu c s v trung tm nghin cu v ang hot ng ,pht trin. Vi sinh vin trng k thut th y l nghnh hc y tim nng.Nhiu cuc thi, nhi u cng trnh nghin cu khoa hc phc v cho vic hc v nghin c u ra i,nhm m c ch pht trin s hc hi,s sng to,t duy,gn lin vi thc tin. Theo yu cu ca m hc cng nh s dng thnh tho cng ngh FPGA em quyt nh chn ti : Thit k b x l hnh nh qung co trn nn LED matrix s dng FPGA. Ni dung ti : Tm hiu v LED matrix Tm hiu v FPGA Tm hiu phn mm h tr thit k xilinx ISE Thit k h thng V y l trong khun kh bi tp ln, nn em ch thit k trn m hnh th nghim, s dng ngn ng VHDL m hnh ha h thng phn c ng . Em xin chn thnh cm n thy L HI SM hng dn chi ti t v FPGA v ph ng php thi t k m hnh ha phn cng. H Ni, ngy 30-10-2009 Sinh vin thc hin : Phm Vn Phong

LI M U

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CHNG I T VN V NHIM V CA N

CHNG 1 :

I t vn Trong thi i ngy nay, khoa hc cng ngh ngy cng pht tri n v c ng dng rt nhiu trong thc t. Trong th cc lnh vc nh gi tr, dch v qu ng co khuch trng sn phm thu ht s ch ca cc doanh nghi p cng nh c nhn ngy cng pht trin mnh m. lm cho sn phm hoc hnh nh cng ty thu ht s ch , quan tm ca khch hng th dch v qung co phi tht n tng, chong ngp, bt mt gii quyt vn ny th c rt nhiu phng n, nhng hi n nay phng n m c cc gii kinh doanh s dng hiu qu nht l dng b ng led matrix. Vi nhng x l hnh nh sng ng, mu sc n tng l s la ch n hng u cho cc nh kinh doanh. Do , thit k h thng bng i n t ph c v nhu c u qu ng co, khuch trng hnh nh ca hng, doanh nghip, cng ty l rt cn thit. II Nhim v ca n Vi s la chn ti ny, trc tin em cn phi tm hiu chi ti t v LED matrix cng nh cc phng php qut LED, hin th x l hnh nhSau tm hi u cc phng php ng dng FPGA gii quyt bi ton t ra. V gi i h n c a ti ch thc hin m phng v hiu cch thc hot ng, phng php lp trnh s dng FPGA cng vi thi gian thc hin t nn em ch gi i quyt bi ton d i dng m hnh, hi vng khi c thi gian v iu kin th em c th trin khai ng dng thc t.

CHNG II C S L THUYT

CHNG 2 :

I - LED Matrix Da trn nguyn tc nh qut mn hnh,ta c th thc hin vic hi n th ma tr n n bng cch qut theo hang v qut theo ct.Mi Led trn ma tr n Led c th coi nh m t im nh.a ch ca mi im nh ny c xc nh ng thi bi m ch gi i m hang v gii m ct,im nh ny s c xc nh nh d liu a ra t b i i u khin. Nh vy ti mi thi im ch c trng thi ca mt im nh xc nh.Tuy nhin khi xc nh a ch v trng thi ca im nh tip theo th cc im nh cn l i s chuy n v trng thi tt.V th hin th c ton b hnh nh m ta mu n th ta ph i qut ma trn nhiu ln vi tc qut rt ln,ln hn nhiu ln thi gian k p tt c a n.Mt ngi ch nhn bit c ti a 24 hnh/s do nu tc qut ln m t ngi s khng nhn bit c s gin on hay l nhp nhy ca n Led(nh l a c m gic mt). Mt iu cng quan trng y l iu chnh sang ca Led,thong thng Led sng bnh thng in p 2-3V,dng in t 20-30mA. m bo Led sng bnh th ng th yu cu mch thit k phi p ng 2 iu kin trn. S khi :

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thc hin c qut hang v qut ct th ma trn Led c thit kt nh sau:

Trng thi ca mt Led s c quyt nh bi tn hi u i n p i vo ng th i c 2 chn. Led sng th ta phi cp in p ph hp vo chn dng ca Led(chn Anot),cn chn catot th ni t.n tt khi ta khng cp ngun cho Led hoc 2 u anot v catot cung mc in p. Ta c s mch nguyn l ca Led 8x8:

CHNG 3 :

II FPGA Field-programmable gate array (FPGA) l vi mach dng cu trc mng phn t logic m ngi dng c th lp trnh c. (Ch field y mun ch n kh nng ti lp trnh bn ngoi ca ngi s dng, khng ph thuc vo dy chuyn sn xut phc tp ca nh my bn dn). Vi mch FPGA c cu thnh t cc b phn: Cc khi logic c bn lp trnh c (logic block) H thng mch lin kt lp trnh c Khi vo/ra (IO Pads) Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l... FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC, nhng nu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k trn th vin logic th FPGA khng t c mc ti u nh nhng loi ny, v hn ch trong kh nng thc hin nhng tc v c bit phc tp, tuy vy FPGA u vit h n ch c th ti cu trc li khi ang s dng, cng on thit k n gi n do v y chi ph gi m, rt ngn thi gian a sn phm vo s dng. Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trc mng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn cc im: tc v ti lp trnh c a FPGA thc hin n gin hn; kh nng lp trnh linh ng hn; v khc bit quan

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trng nht l kin trc ca FPGA cho php n c kh nng ch a kh i l ng l n cng logic (logic gate), so vi cc vi mch bn dn lp trnh c c trc n. Thit k hay lp trnh cho FPGA c thc hin ch yu bng cc ngn ng m t phn cng HDL nh VHDL, Verilog, AHDL, cc hng sn xut FPGA ln nh Xilinx, Altera thng cung cp cc gi phn mm v thit b ph tr cho qu trnh thi t k , cng c mt s cc hng th ba cung cp cc gi ph n m m ki u ny nh Synopsys, Synplify... Cc gi phn mm ny c kh nng thc hin tt c cc bc ca ton b quy trnh thit k IC chun vi u vo l m thit k trn HDL (cn gi l m RTL). 1) Kin trc FPGA Cu trc tng th ca mt FPGA c minh ha hnh sau.

Khi logic FPGA

Phn t chnh ca FPGA l cc khi logic ( logic block). Khi logic c cu thnh t LUT v mt phn t nh ng b flip-flop, LUT (Look up table) l khi logic c th thc hin bt k hm logic no t 4 u vo, kt qu c a hm ny ty vo m c ch m gi ra ngoi khi logic trc tip hay thng qua phn t nh flip-flop. Trong ti liu hng dn ca cc dng FPGA ca Xilinx cn s d ng khi ni m SLICE, 1 Slice to thnh t gm 4 khi logic, s lng cc Slices thay i t vi nghn n vi chc nghn ty theo loi FPGA. Nu nhn cu trc tng th ca mng LUT th ngoi 4 u vo k trn cn h tr thm 2 u vo b xung t cc khi logic phn b trc v sau n nng t ng s u vo c a LUT ln 6 chn. Cu trc ny l nhm tng tc cc b s hc logic. thumb|200px|Khi chuyn mch ca FPGA Mng lin kt trong FPGA c cu thnh t cc ng kt ni theo hai phng ngang v ng, ty theo tng lo i FPGA m cc ng kt ni c chia thnh cc nhm khc nhau, v d trong XC4000 c a Xilinx c 3 loi kt ni: ngn, di v rt di. Cc ng kt ni c n i v i nhau thng qua cc khi chuyn mch lp trnh c (programable switch), trong mt khi chuyn mch cha mt s lng nt chuyn lp trnh c m bo cho cc dng lin k t ph c t p khc nhau. Ngoi cc khi logic ty theo cc loi FPGA khc nhau m c cc phn t tch h p thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex 4,5 c a Xilinx c cha nhn x l PowerPC, hay trong Atmel FPSLIC tch hp nhn ARV, hay cho nhng ng dng x l tn hiu s DSP trong FPGA c tch hp cc DSP Slide l b nhn

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cng tc cao, thc hin hm A*B+C, v d dng Virtex c a Xilinx ch a t vi ch c n hng trm DSP slices vi A, B, C 18-bit. 2) ngn ng VHDL Thit k hay lp trnh cho FPGA c thc hin ch yu bng cc ngn ng m t phn cng HDL nh VHDL, Verilog, AHDL.. .Em quyt nh chn ngn ng VHDL lp trnh cho FPGA. VHDL (VHSIC Hardware Description Laguage) l mt ngn ng c dng m t cc h thng phn cng in t s. N c chng trnh quc gia v cc mch tch hp tc rt cao - VHSIC (Very High Speed Integrated Circuits) do chnh ph M khi xng vo u nhng nm 1980. Cc cng ty tham gia chng trnh VHSIC nhn thy rng h cn phi c mt cng c no thit k cc gin u vo cho cc IC chuyn dng c ln, v h xut vic lp ra mt ngn ng m t phn cng dng m t cu trc v chc nng ca cc mch tch hp (cn c gi l IC - Integrated Circuits). K t , VHDL ra i v c pht trin, ri sau c Hip hi cc k s in v in t - IEEE (Institude of Electrical and Electronic Engineers) chp nhn coi nh l tiu chun ti M. Phin bn u tin l Tiu chun IEEE 1076-1987 (cn c gi l VHDL-87). Phin bn ny c b sung sa i nm 1993 thnh IEEE 1076-1993 (cn c gi l VHDL-93). * M t cu trc Mt h thng in t s c th c m t thnh cc khi - cn gi l module vi cc u vo v u ra. Cc gi tr in u ra c mi quan h vi cc gi tr trn cc u vo. Hnh 2.16a biu din mt v d nh vy. Khi F c hai u vo A v B, v c mt u ra Y. S dng ngn ng VHDL m t khi F, th ta gi khi F l mt thc th (entity) thit k, v cc u vo v u ra l cc cng (port). C mt cch m t chc nng ca khi F, l chng ta m t cc khi con (sub-module) thnh phn ca n. Mi mt khi con c gi l mt tp hp (instance) ca mt s thc th, v cc cng ca cc tp hp c ni li bng cc ng tn hiu (signal). Hnh di m t khi F l mt tp hp gm cc thc th G, H v I. Kiu m t ny c gi l m t cu trc (structural). Cc thc th G, H v I cng c m t theo cu trc tng t nh vy.

(a) Khi F c hai u vo v mt u ra; (b) Khi F gm c 3 thc th G, H, I * M t hot ng

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Trong nhiu trng hp, vic m t cu trc khng tng ng vi vic m t hot ng. Ngi ta thng dng cch m t hot ng theo kiu t di ln da vo m t cu trc. V d, khi chng ta thit k h thng in t th khng cn phI m t c th cu trc bn trong ca tng con IC m ch cn m t theo chc nng ca cc khi ca h thng m thi. Trng hp ny c gi l m t chc nng (fuctional) hoc m t hot ng (behavioural). minh ho cho iu ny, chng ta gi s rng chc nng ca thc th F trong Hnh 2.16a l mt mch OR o. Khi m t hot ng ca F ta c th bini theo i s Boolean nh sau: Y = A.+ .B i vi cc mch c chc nng hot ng phc tp hn, th khng th bin din theo cc chc nng u vo c. Trong cc h thng c phn hi ngc, u ra thng l cc hm chc nng theo thi gian. Ngn ng VHDL cho php gii quyt vn ny bng cch m t hot ng theo khun dng chng trnh lp trnh. * M t s kin ri rc theo thi gian Khi chc nng hot ng v cu trc ca khi c ch nh r, th ngi ta c th m phng khi bng cch kch hot theo m t hot ng ca n. iu ny c th thc hin c bng cch m phng qu trnh hot ng c ri rc thnh cc bc theo thi gian. Ti mt vi thi im m phng, khi u vo c kch hot bng cch thay i gi tr trn cng u vo. Khi ny phn ng li bng cch thc hin m lnh theo m t hot ng ca n c gn v to ra cc gi tr mi a n ng tn hiu gi ti cc cng u ra ca n ti cc thi im m phng tip theo sau. Vic ny c gi l k hoch giao tc (scheluding a transaction) trn tn hiu . Nu gi tr mi khc gi tr trc c trn ng tn hiu, th s c mt s kin (event) xy ra, v cc khi khc vi cc u vo c kt ni vi ng tn hiu c th s c kch hot. Qu trnh m phng bt u vi mt pha c gi l pha khi ng (initialisatoin phase), v sau cc qu trnh c thc hin lp li hai giai on trong mt chu k m phng (simulation cycle). Trong pha khi ng, tt c cc tn hiu c cung cp sn cc gi tr khi ng, thi gian m phng c a v 0, v mi mt chng trnh hot ng ca mt khi c kch hot. Trong giai on u tin ca chu k m phng, thi gian m phng c nng Qu trnh m phng bt u vi mt pha c gi l pha khi ng (initialisatoin phase), v sau cc qu trnh c thc hin lp li hai giai on trong mt chu k m phng (simulation cycle). Trong pha khi ng, tt c cc tn hiu c cung cp sn cc gi tr khi ng, thi gian m phng c a v 0, v mi mt chng trnh hot ng ca mt khi c kch hot. Trong giai on u tin ca chu k m phng, thi gian m phng c nng ln thnh thi gian sm nht ti thi im m giao tc c thc hin. Tt c cc giao tc c a vo ti thi im ny u c kch hot, v iu ny c th gy ra mt s s kin no . Trong gian on th hai ca chu k m phng, tt c cc khi phn ng li i vi cc s kin va xy ra trong giai on mt s kch hot chng trnh hot ng ca chng. Cc chng trnh thng l k hoch giao tc trn cc tn hiu u ra ca chng. Khi tt c cc chng trnh kt thc hot ng, chu k m phng c lp li. Nu khng c thm giao tc no th qu trnh m phng hon thnh.

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Mc ch ca vic m phng l bit thm thng tin v s thay i trong h thng ti tng thi im. Vic ny c th thc hin c gim st bi chng trnh gim st m phng (simulation monitor). Chng trnh ny nhm mc ch ghi li qu trnh hot ng theo tng thi im ti cc im dng vo vic phn tch v sau. * C php v ng ngha: Hot ng ca mt module c th c m t theo dng ngn ng lp trnh. Trong mc ny s gii thiu v c php v ng ngha ca cc khi bo trong ngn ng VHDL. + Cc biu thc v ton t Cc biu thc trong VHDL hon ton tng t nh cc biu thc trong cc ngn ng lp trnh khc. Mt biu thc l mt cng thc kt hp cc a thc vi cc ton t. Cc a thc bao gm tn cc i s, k hiu bng ch, cc hm gi v cc du ngoc ca biu thc. Cc ton t c lit k trong Bng di theo th t u tin. u tin cao nht **; abs; not; u tin gim dn *; /; mod; rem; u tin gim dn + (sign); -(sign) u tin gim dn +; -; &; u tin gim dn =; /=; <; <=; >; >=; u tin thp nht And; or; nand; nor; xor; Cc ton t logic and, or, nand, nor, xor v not hot ng trn cc gi tr kiu bit hoc l boolean, v trn cc mng 1 chiu ca cc kiu . i vi cc ton hng mng (array), s hot ng tun theo cc phn t tng ng ca tng mng, thng ln ca mng c cng ln vi kt qu. i vi cc ton hng bit v boolean, cc ton t and, or, nand v nor l cc ton t ngn mch (short-circuit), do chng ch u tin hn so vi ton hng bn phi ca chng nu ton hng bn tri khng xc nh c kt qu. Do and v nand ch u tin hn so vi ton hng bn phi nu ton hng bn tri l true hoc 1, cn or v nor ch u tin hn ton hng bn phi nu ton hng bn tri l false hoc 0. Cc ton t quan h =, /=, <, <=, > v >= phi c cc ton hng hai u cng kiu, v thng cho cc kt qu theo kiu boolean. Cc ton t bng (= v /=) c th c cc ton hng theo bt k kiu no. i vi cc ton t so snh, hai gi tr bng nhau nu tt c cc phn t tng ng ca chng bng nhau. Cc ton t du (+, -), cc ton t cng (+) v tr (-) c cch s dng ca chng trn cc ton hng dng s. Ton t kt ni (&) lm vic trn cc mng mt chiu thnh dng mt mng mi vi ni dung ca ton hng bn phi k tip ton hng tri. N c th mc ni mt phn t n vo mt mng hoc hai phn t c lp thnh mt mng mi. Cc ton t nhn (*) v chia (/) lm vic vi cc s nguyn, s du phy ng v cc kiu n v vt l. Cc ton t chia ly phn nguyn (mod- modulus) v chia ly phn d (rem - remainder) ch lm vic vi kiu s nguyn. Ton t gi tr tuyt i (abs) ch lm vic vi bt k kiu s no. Cui cng ton t m (**) c th lm vic vi kiu s nguyn v ton hng tri ca kiu s du phy ng, nhng phi c mt s nguyn ton hng phi, cn ton hng phi m c gi tr m ch c php nu ton hng tri l mt s du phy ng dng s. + Cc khai bo tun t VHDL cung cp mt cng c hiu qu cho vic kim tra trng thi ca cc i tng v iu khin lung hot ng ca cc m hnh l cc php gn.

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Php gn bin Nh cc ngn ng lp trnh khc, mt bin c gn mt gi tr mi bng cch s dng php khai bo gn. Khai bo bin trong process c phm vi ch trong process . Bin c th khai bo trong chng trnh con. Khai bo bin bn ngoi process hoc chng trnh con th gi l shared variable. Cc bin ny c th cp nht v c nhiu process. Lu tn hiu khng c khai bo trong process. Cc pht biu gn tn hiu xut hin trong process c gi l pht biu gn tn hiu tun t, k c pht biu gn bin, thc hin tun t c lp vi vic xut hin cc s kin trn mi tn hiu trong biu thc bn phi, khc vi vic thc thi ca cc pht biu gn tn hiu ng thi trong phn trc. Khai bo bin (bt u bng t variable) khai bo bin khc vi tn hiu l n lun c gn gi tr ngay tc khc v php gn tn hiu l := t hp k hiu, n c gn gi tr sau khong delay ( xc nh do ngi s dng hoc mc nhin l khong delta) v php gn iu khin vic gn gi tr cho bin <= t hp symbol. C php l: khai bo gn bin : ch := biu thc; Trong trng hp n gin nht, ch ca php gn l mt tn i tng, v gi tr ca biu thc c gn theo tn i tng. i tng v gi tr phi c cng mt kiu. Khai bo If (nu) Khai bo If cho php la chn cc khai bo kch hot, ph thuc vo mt hoc nhiu iu kin. C php nh sau: khai bo if : if iu kin then chui cc khai bo { elsif iu kin then chui cc khai bo [ else chui cc khai bo } end if; Cc iu kin l cc biu thc tr v gi tr boolean. Cc iu kin c nh gi l ng khi c mt gi tr c tr v true. Ngc li th mnh else c thc hin, v khai bo ca n c kch hot. Khai bo Case Dng ca pht biu case l: case expression is when choices=> sequential -statement branch 1# when choices=> sequential -statement branch 2# --c th c nhiu nhnh {when others=> sequential-statement}last branch end case; Pht biu case la chn mt trong nhng nhnh cho vic thc thi da trn gi tr ca biu thc. Gi tr biu thc phi thuc kiu tru tng hoc kiu mng mt chiu. S chn la c th c th hin nh gi tr n, vng gi tr bi vic s dng du | hoc

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s dng mnh khc. Tt c cc gi tr c th c ca biu thc phi c th hin trong pht biu case ng 1 ln. Cc mnh khc c th c s dng bao qut tt c cc gi tr, v nu c, phi l nhnh cui cng trong pht biu case. Cc khai bo vng lp VHDL cung cp kiu khai bo vng lp c bn c th s dng cc vng lp while v for ging nh trong cc ngn ng lp trnh khc. Mt pht biu lp c s dng lp li mt lot cc cu lnh tun t. C php ca pht biu lp l: [loop-label:] iteration-scheme loop sequential-statements end loop [loop-lebel]; C 3 kiu s lp. u tin l s lp c dng: for identifier in range Mt th d cho s lp ny l: FACTORAL:=1; for NUMBER in 2 to N loop FACTORAL :=FACTORAL*NUMBER; end loop; Khai bo Null (rng) Khai bo null khng c hiu qu. N c th c s dng biu din trng thi r rng l khng c hnh ng no c yu cu trong trng hp . Ngi ta thng s dng n trong cc khai bo case, trong tt c cc gi tr c th ca biu thc la chn phi c lit k chn, nhng i vi mt vi la chn th khng yu cu hnh ng no. V d nh sau: case controller_command is when forward => engage_motor_forward; when reverse => engage_motor_reverse; when idle => null; end case; *Chng trnh con Ging nh cc ngn ng lp trnh khc, VHDL cung cp cng c thc hin chng trnh con linh hot di dng cc th tc v cc hm. VHDL cng cung cp mt kiu ng gi mnh i vi tp cc m t v cc i tng a vo cc n v dng module. Cc ng gi cng cung cp mt tiu chun v tnh tru tng d liu v thng tin n.

CHNG III THIT K H THNG S DNG PHN MM XILINX ISE

CHNG 4 :

I-Tng quan phn mn Xilinx ISE Xilinx ISE (Integrated Software Environment) l mt b phn mm thi t k ca Xilinx , cho php ta thc hin cc h thng nhng c a Xilinx t khu thi t k ban u (thng qua VHDL, Verilog HDL, ABEL hoc l v Schematic) cho n khu cu i cng l np thit k ca mnh ln FPGA. bt u mt thit k, ta phi to m t project m i trong ISE thng qua cng c qun l ISE Project Navigator. Sau ISE Project Navigator s qun l tt c cc qu trnh thit k trong trong project .

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Quy trnh thit kt trong ISE bao gm cc qu trnh sau : Design Entry -> Synthesis -> Implementation -> Verification -> Device Configuration. * Design Entry : y l bc u tin trong qu trnh thit k ca ISE. Trong sut qu trnh design entry, ta s thit k nhng file ngun (Source File) theo nh ng yu c u ban u (nhng m t chc nng ca h thng m ta cn phi thi t k ). b c ny, ta s dng nhng ngn ng m t phn cng nh : VHDL, Verilog HDL, Abel ho c d ng Schematic thit k . Chng ta c th dng nhiu ngn ng khc nhau trong cng m t thit k. V d nh : thit k cc module chc nng bng Verilog HDL, sau dng dng schematic (s khi) thit k h thng chnh. * Synthesis : Sau khi thit k h thng v thc hin nhng m phng ki m tra chc nng logic ca h thng, chng ta phi chy synthesis chuyn i nh ng file ngun c vit bng VHDL,Verilog HDL, thnh file netlist. Nh ng file netlist ny cn thit a vo qu trnh Implementation. * Implementation : Qu trnh ny s chuyn i thit k mc logic thnh cc file nh dng vt l c th download xung FPGA. Sau khi chy Synthesis, chng ta s c nhng file netlist, qu trnh Implementation s chuyn i nhng file netlist thnh nhng file cu hnh vt l c th da vo linh kin FPGA c th m ta ang s dng, do qu trnh ny i hi chng ta phi ch r linh kin FPGA no ang c s dng. * Verification: Sau khi chy bc Implementation, chng ta s c th m phng thi t k ca mnh mt cch chnh xc hn. V qu trnh m ph ng b c Design Entry ch c th m phng chc nng ca mch ch n cha th m ph ng th i gian (timing), timing ty thuc vo linh kin vt l c th . * Device Configuration: y l bc cui cng trong sut qu trnh thi t k . b c ny cc file nh dng cu hnh s c dng to ra nhng file bitstream n p xung chip FPGA .

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CHNG 5 :
1.

II -Thit k chng trnh iu khin LED matrix S khi

1.1 B gii m: B gii m cn c gi l b phn knh, n c n ng ra, s ng ra ny ph thuc vo s m bit la chn ng vo. Mi quan h gi a n v m l . Trong b gi i m c thm m t ng Enable cho php b gii m hot ng hay ngng ho t ng. Khi E=0 th t t c cc ng ra u mang gi tr 0. Khi E=1 th b gi i m s ho t ng, n s l a ch n ng ra no a d liu n ty thu c vo cc ng vo l a ch n m. V d m t b gii m 3 sang 8. Nu ng vo a ch l 101 th th ng ra c la chn a d li u ra ( ln mc cao), trong khi tt c cc ng ra cn l i u khng c l a ch n (tch cc mc thp). Mt b gii m thng dng rt nhiu thnh phn v chng ta mun ti m i th i i m ch c mt thnh phn c cho php hot ng m thi. V d trong m t h thng nh ln s dng nhiu con chip nh, ti mi thi im ch c m t con chip nh c tch cc cho php hot ng m thi. Mt ng ra c a b gi i m s c n i n m t ng vo tch cc trong mi con chip. Mt a ch c to ra t b gi i m s lm tch c c mt con chip nh tng ng. Bng chn tr, s mch v k hiu logic ca b gi i m 3 sang 8 c biu din trong hnh di. Mt b gii m kch c ln c th s dng mt vi cc b gii m nh hn. V d trong hnh di s dng 7 b gii m 1 sang 2 xy dng b gii m 3 sang 8.

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Mt b gii m 3 sang 8 (a) Bng chn tr; (b) s mch; (c) k hiu logic.

Hnh 2. : Mt b gii m 3 sang 8 c xy dng t 7 b gii m 1 sang 2. on m VHDL c vit theo cu trc Behavioral cho b gii m 3 sang 8. Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; ENTITY Decoder IS PORT( E: IN std_logic; A: IN std_logic_vector(2 DOWNTO 0); Y: OUT std_logic_vector(7 DOWNTO 0); END Decoder; ARCHITECTURE Behavioral OF Decoder IS BEGIN PROCESS (E, A)

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BEGIN IF (E='0') THEN -- khong hoat dong Y<= (OTHERS => '0') ; ELSE -- decoder hoat dong CASE A IS -- lua chon ngo ra WHEN "000" => Y <= "00000001"; -- ngo ra la Y0 WHEN "001" => Y <= "00000010"; -- ngo ra la Y1 WHEN "010" => Y <= "00000100"; -- ngo ra la Y2 WHEN "011" => Y <= "00001000"; -- ngo ra la Y3 WHEN "100" => Y <= "00010000"; -- ngo ra la Y4 WHEN "101" => Y <= "00100000"; -- ngo ra la Y5 WHEN "110" => Y <= "01000000"; -- ngo ra la Y6 WHEN "111" => Y <= "10000000"; -- ngo ra la Y7 WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; END Behavioral; dng xung m phng bng xilinx ISE:

1.2 B m B m ba trng thi l b c ba trng thi: 0, 1 v trng thi th ba c bi u th b ng Z. Gi tr ca Z c trng cho trng thi tr khng cao. B m ba tr ng thi c dng kt ni mt vi dch v trn cng mt bus. Mt bus c m t hay nhi u ng dy truyn tn hiu. Nu hai hay nhiu dch v c kt ni mt cch trc tip n mt bus m khng s dng b m ba trng thi, th nhng tn hiu ny s b sai l c trong bus . Trong b m ba trng thi c s dng chn E (enable) iu khin hot ng ca n. Khi E=0, b m ba trng thi khng c tch cc v ng ra y trng thi tr khng

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cao. Khi E=1, b m c cho php hot ng v ng vo d s a c d li u c a n n ng ra y. Mt mch ch vi mt cng logic th khng th to ra trng thi tr khng cao c. Do cung cp trng thi tr khng cao, mch m ba trng thi s dng hai con transistor CMOS c bit kt ni vi cc cng logic nh trong hnh d i. Vic c thm hai con transistor h CMOS ny, chng ta cn phi c mt mch i u khi n chng hot ng lin kt vi nhau to thnh mt b m ba trng thi. B ng chn tr c a mch iu khin c cho trong hnh (c). Khi E=0, c hai con transistor CMOS u tt, y trng thi tr khng cao. Khi E=1 v d=0, nu chng ta mun y=0 th nMOS dn v pMOS tt, lc ny ng ra y s b ko xung thp; nu chng ta mun y=1 th nMOS tt v pMOS dn, lc ny ng ra y s b y ln mc cao do y c ni ln ngun. Mch c hai ng vo E v d nn b ng chn tr s c 4 cp gi tr l 00, 01, 10, 11. Da vo cc gi tr ny c ng thm cch gi i thch v hot ng ca cc con transistor CMOS ta c th hon thnh bng chn tr nh hnh 2.26(c).

B m ba trng thi (a) bng chn tr; (b) k hiu logic; (c) bng chn tr cho vic phn chia iu khin cho mch m ba trng thi; (d) s mch. on m VHDL vit theo cu trc Behavioral cho b m ba trng thi. LIBRARY Ieee; USE IEEE.std_logic_1164.ALL; ENTITY dem_3_trang_thai IS PORT ( E: IN std_logic; d: IN std_logic_vector(7 DOWNTO 0); Y: OUT std_logic_vector(7 DOWNTO 0)); END dem_3_trang_thai; ARCHITECTURE Behavioral OF dem_3_trang_thai IS BEGIN PROGRESS (E, d) BEGIN IF (E = '1') THEN Y <= d;

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ELSE Y<= (OTHERS => 'Z'); END IF; END PROGRESS; END Behavioral; dng th m phng bng xilinx ISE :

CHNG 6 :

2. CODE VHDL iu khin LED matrix :

LIBRARY ieee; LIBRARY std_developerskit; USE ieee.std_logic_1164.all; USE std.textio.all; USE IEEE.std_logic_arith.all; USE std_developerskit.std_iopak.all; entity tb is end tb; ARCHITECTURE a OF tb IS CONSTANT DATA_WIDTH : INTEGER :=8; CONSTANT IMAGE_WIDTH : INTEGER := 198; CONSTANT ROW_NUMBER : INTEGER := 135; CONSTANT CLOCK_PERIOD : TIME := 50 ns; CONSTANT F_FACTORS_PART : INTEGER := 15; -- float part width, 10-E4 accuracy CONSTANT INT_FACTORS_PART: INTEGER := 3; -- integer part with, from -5 to +4 range (-4.999999 to 3.999999) CONSTANT FACTORS_WIDTH : integer := (f_factors_part + int_factors_part); -- full factor width

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constant crgb2ycbcr601_a11 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000010000011011111"; -- 0.256789 constant crgb2ycbcr601_a12 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000100000010000110"; -- 0.504129 constant crgb2ycbcr601_a13 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000000110010001000"; -- 0.0979 constant crgb2ycbcr601_a21 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"111110110100000111"; -- -0.148223 constant crgb2ycbcr601_a22 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"111101101011000001"; -- -0.290992 constant crgb2ycbcr601_a23 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000011100000111000"; -- 0.439215 constant crgb2ycbcr601_a31 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000011100000111000"; -- 0.439215 constant crgb2ycbcr601_a32 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"111101000011101100"; -- -0.367789 constant crgb2ycbcr601_a33 : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"111111011011011100"; -- -0.071426 constant crgb2ycbcr601_b1x : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000000000000000000"; -- 0 constant crgb2ycbcr601_b2x : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000000000000000000"; -- 0 constant crgb2ycbcr601_b3x : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000000000000000000"; -- 0 constant crgb2ycbcr601_b1y : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"000010000000000000"; -- 16 constant crgb2ycbcr601_b2y : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"010000000000000000"; -- 128 constant crgb2ycbcr601_b3y : SIGNED(FACTORS_WIDTH-1 DOWNTO 0) := b"010000000000000000"; -- 128 SIGNAL clk : STD_LOGIC; SIGNAL rstn : STD_LOGIC; SIGNAL x1,x2,x3 : UNSIGNED(DATA_WIDTH-1 DOWNTO 0); SIGNAL x1bv,x2bv,x3bv : BIT_VECTOR(DATA_WIDTH-1 DOWNTO 0); SIGNAL y1,y2,y3 : UNSIGNED(DATA_WIDTH-1 DOWNTO 0); SIGNAL y1c,y2c,y3c : SIGNED(INT_FACTORS_PART-1 DOWNTO 0); SIGNAL y1bv,y2bv,y3bv : BIT_VECTOR(DATA_WIDTH-1 DOWNTO 0); SIGNAL DATA_ENA : STD_LOGIC; SIGNAL DOUT_RDY : STD_LOGIC; BEGIN READ_DATA: PROCESS(CLK, RSTN) FILE file_in : ASCII_TEXT IS "X.txt"; VARIABLE digits_str1 : string(1 to 3); VARIABLE digits_str2 : string(1 to 3); VARIABLE digits_str3 : string(1 to 3); BEGIN if RSTN = '0' THEN

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DATA_ENA <= '0'; elsif rising_edge(clk) then if NOT endfile(file_in) THEN fscan (file_in, "%x %x %x", digits_str1, digits_str2, digits_str3); if digits_str1(1) /= NUL then x1bv <= From_HexString (digits_str1); x2bv <= From_HexString (digits_str2); x3bv <= From_HexString (digits_str3); end if; DATA_ENA <= '1'; ELSE DATA_ENA <= '0'; END IF; END IF; END PROCESS READ_DATA; WRITE_RESULT: PROCESS(CLK, RSTN) FILE file_out : ASCII_TEXT IS OUT "Y.txt"; VARIABLE digit_out1 : string(1 to 2):=(others=>'0'); VARIABLE digit_out2 : string(1 to 2):=(others=>'0'); VARIABLE digit_out3 : string(1 to 2):=(others=>'0'); VARIABLE i,k : INTEGER; BEGIN if RSTN = '0' THEN i := 0;k:=1; elsif rising_edge(clk) then if DOUT_RDY = '1' then if k<=ROW_NUMBER then i:=i+1; digit_out1 :=To_string(y1bv,"%2x"); digit_out2 :=To_string(y2bv,"%2x"); digit_out3 :=To_string(y3bv,"%2x"); fprint(file_out,"%s %s %s ", digit_out1, digit_out2, digit_out3); end if; if i = IMAGE_WIDTH then i := 0; k:=k+1; fprint(file_out,"\n"); end if; end if; end if; END PROCESS WRITE_RESULT; x1 <= UNSIGNED(TO_STDLOGICVECTOR(x1bv)); x2 <= UNSIGNED(TO_STDLOGICVECTOR(x2bv)); x3 <= UNSIGNED(TO_STDLOGICVECTOR(x3bv)); y1bv<=To_Bitvector(STD_LOGIC_VECTOR(y1)); y2bv<=To_Bitvector(STD_LOGIC_VECTOR(y2)); y3bv<=To_Bitvector(STD_LOGIC_VECTOR(y3)); mult : entity work.multiplier3x3(a)

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GENERIC MAP( DATA_WIDTH, F_FACTORS_PART, INT_FACTORS_PART ) PORT MAP( clk => clk, rstn => rstn, data_ena => DATA_ENA, dout_rdy => DOUT_RDY, x1 => x1, x2 => x2, x3 => x3, a11 => crgb2ycbcr601_a11, a12 => crgb2ycbcr601_a12, a13 => crgb2ycbcr601_a13, a21 => crgb2ycbcr601_a21, a22 => crgb2ycbcr601_a22, a23 => crgb2ycbcr601_a23, a31 => crgb2ycbcr601_a31, a32 => crgb2ycbcr601_a32, a33 => crgb2ycbcr601_a33, b1x => crgb2ycbcr601_b1x, b2x => crgb2ycbcr601_b2x, b3x => crgb2ycbcr601_b3x, b1y => crgb2ycbcr601_b1y, b2y => crgb2ycbcr601_b2y, b3y => crgb2ycbcr601_b3y, y1c => y1c, y2c => y2c, y3c => y3c, y1 => y1, y2 => y2, y3 => y3 ); CLOCK : PROCESS BEGIN clk <= '1' ; wait for CLOCK_PERIOD/2; clk <= '0' ; wait for CLOCK_PERIOD/2 ; END PROCESS CLOCK; RESET : PROCESS BEGIN rstn<='0'; wait for 10*CLOCK_PERIOD; rstn<='1';

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wait ; END PROCESS RESET; END a;

CHNG 7 :

III - Kt lun Qua qu trnh thc hin ti : Thit k b x l hnh nh qung co trn nn LED matrix s dng FPGA, t vic nghin cu h thng LED matrix, cu to kt ni cc phn t n cu trc cch thit k lp trnh cho FPGA v s dng thnh tho phn mm Xilinx ISE gip em cng c kin th c v rt ra c nhi u bi h c qu v FPGA. Do vic thc hin ti ch trong phm vi bi tp ln nn em ch thi t k m phng di dng m hnh nh, nn khng th hin ht c tng cng nh ph m vi ng dng rng ln ca ti, nu sau ny c c hi pht tri n em s c gng lm c nhiu hn na, c bit phi c sn phm thc t. Em xin chn thnh cm n th y L HI SM trang b kin thc c bn em c th hon thnh bi tp ny.