--------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 09:59:57 11/18/2008 -- Design Name: addsub -- Module Name: addsub1.

vhd -- Project Name: addsub -- Target Device: -- Tool versions: -- Description: --- VHDL Test Bench Created by ISE for module: addsub --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY addsub1_vhd IS END addsub1_vhd; ARCHITECTURE behavior OF addsub1_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT addsub PORT( ha : IN std_logic; hb : IN std_logic; fa : IN std_logic; fb : IN std_logic; fci : IN std_logic;

hx : IN std_logic; hy : IN std_logic; fx : IN std_logic; fy : IN std_logic; fbi : IN std_logic; hsum : OUT std_logic; hcarry : OUT std_logic; fsum : OUT std_logic; fco : OUT std_logic; hd : OUT std_logic; hbo : OUT std_logic; fd1 : OUT std_logic; fbo : OUT std_logic ); END COMPONENT; --Inputs SIGNAL ha : std_logic := '0'; SIGNAL hb : std_logic := '0'; SIGNAL fa : std_logic := '0'; SIGNAL fb : std_logic := '0'; SIGNAL fci : std_logic := '0'; SIGNAL hx : std_logic := '0'; SIGNAL hy : std_logic := '0'; SIGNAL fx : std_logic := '0'; SIGNAL fy : std_logic := '0'; SIGNAL fbi : std_logic := '0'; --Outputs SIGNAL hsum : std_logic; SIGNAL hcarry : std_logic; SIGNAL fsum : std_logic; SIGNAL fco : std_logic; SIGNAL hd : std_logic; SIGNAL hbo : std_logic; SIGNAL fd1 : std_logic; SIGNAL fbo : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: addsub PORT MAP( ha => ha, hb => hb, hsum => hsum, hcarry => hcarry,

fa => fa, fb => fb, fci => fci, fsum => fsum, fco => fco, hx => hx, hy => hy, hd => hd, hbo => hbo, fx => fx, fy => fy, fbi => fbi, fd1 => fd1, fbo => fbo ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; -- Place stimulus here ha <= '1' after 100 ns; hb <= '1' after 200 ns; fa <= '1' after 300 ns; fb <= '1' after 400 ns; fci <= '1' after 200 ns; hx <= '1' after 400 ns; hy <= '1' after 600 ns; fx <= '1' after 300 ns; fy <= '1' after 200 ns; fbi <= '1' after 200 ns;

wait; -- will wait forever END PROCESS; END;