Digital Integrated Circuits: A Design Perspective

EE141 Digital Integrated Circuits
2nd
Introduction
1
Digital Integrated
Circuits
A Design Perspective
Introduction
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
July 30, 2002
2nd
Introduction
2
What is this book all about?
Introduction to digital integrated circuits.
CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Programmable logic arrays. Design
methodologies.
What will you learn?
Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability
2nd
Introduction
3
Digital Integrated Circuits
Introduction: Issues in digital design
The CMOS inverter
Combinational logic structures
Sequential logic gates
Design methodologies
Interconnect: R, L and C
Timing
Arithmetic building blocks
Memories and array structures
2nd
Introduction
4
Introduction
Why is designing
digital ICs different
today than it was
before?
Will it change in
future?
2nd
Introduction
5
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
2nd
Introduction
6
ENIAC - The first electronic computer (1946)
2nd
Introduction
7
The Transistor Revolution
First transistor
Bell Labs, 1948
2nd
Introduction
8
The First Integrated Circuits
Bipolar logic
1960s
ECL 3-input Gate
Motorola 1966
2nd
Introduction
9
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
2nd
Introduction
10
Intel Pentium (IV) microprocessor
2nd
Introduction
11
Moores Law
In 1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
2nd
Introduction
12
Moores Law
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
9
5
9
1
9
6
0
1
9
6
1
1
9
6
2
1
9
6
3
1
9
6
4
1
9
6
5
1
9
6
6
1
9
6
7
1
9
6
8
1
9
6
9
1
9
7
0
1
9
7
1
1
9
7
2
1
9
7
3
1
9
7
4
1
9
7
5
L
O
G
2

O
F

T
H
E

N
U
M
B
E
R

O
F
C
O
M
P
O
N
E
N
T
S

P
E
R

I
N
T
E
G
R
A
T
E
D

F
U
N
C
T
I
O
N
Electronics, April 19, 1965.
2nd
Introduction
13
Evolution in Complexity
2nd
Introduction
14
Transistor Counts
1,000,000
100,000
10,000
1,000
10
100
1
1975 1980 1985 1990 1995 2000 2005 2010
8086
80286
i386
i486
Pentium

Pentium
Pro
K
1 Billion
Transistors
Source: Intel
Projected
Pentium

II

Pentium

III

Courtesy, Intel
2nd
Introduction
15
Moores law in Microprocessors
4004
8008
8080
8085
8086
286
386
486
Pentium proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010
Year
T
r
a
n
s
i
s
t
o
r
s

(
M
T
)

2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 years
Courtesy, Intel
2nd
Introduction
16
Die Size Growth
4004
8008
8080
8085
8086
286
386
486
Pentium proc
P6
1
10
100
1970 1980 1990 2000 2010
Year
D
i
e

s
i
z
e

(
m
m
)

~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moores Law
Courtesy, Intel
2nd
Introduction
17
Frequency
P6
Pentium proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
F
r
e
q
u
e
n
c
y

(
M
h
z
)

Lead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel
2nd
Introduction
18
Power Dissipation
P6
Pentium proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
P
o
w
e
r

(
W
a
t
t
s
)

Lead Microprocessors power continues to increase
Courtesy, Intel
2nd
Introduction
19
Power will be a major problem
5KW
18KW
1.5KW
500W
4004
8008
8080
8085
8086
286
386
486
Pentium proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Year
P
o
w
e
r

(
W
a
t
t
s
)

Power delivery and dissipation will be prohibitive
Courtesy, Intel
2nd
Introduction
20
Power density
4004
8008
8080
8085
8086
286
386
486
Pentium proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
P
o
w
e
r

D
e
n
s
i
t
y

(
W
/
c
m
2
)

Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Power density too high to keep junctions at low temp
Courtesy, Intel
2nd
Introduction
21
Not Only Microprocessors
Digital Cellular Market
(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
Power
Management
Small
Signal RF
Power
RF
(data from Texas Instruments)

Cell
Phone
2nd
Introduction
22
Challenges in Digital Design
Microscopic Problems
Ultra-high speed design
Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution.

Everything Looks a Little Different
Macroscopic Issues
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
etc.

and Theres a Lot of Them!
DSM 1/DSM
?
2nd
Introduction
23
Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2
0
0
3

1
9
8
1

1
9
8
3

1
9
8
5

1
9
8
7

1
9
8
9

1
9
9
1

1
9
9
3

1
9
9
5

1
9
9
7

1
9
9
9

2
0
0
1

2
0
0
5

2
0
0
7

2
0
0
9

10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
x
x x
x
x x
x
21%/Yr. compound
Productivity growth rate
x
58%/Yr. compounded
Complexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
L
o
g
i
c

T
r
a
n
s
i
s
t
o
r

p
e
r

C
h
i
p

(
M
)

0.01
0.1
1
10
100
1,000
10,000
100,000
P
r
o
d
u
c
t
i
v
i
t
y

(
K
)

T
r
a
n
s
.
/
S
t
a
f
f

-

M
o
.

Source: Sematech
Complexity outpaces design productivity
C
o
m
p
l
e
x
i
t
y

Courtesy, ITRS Roadmap
2nd
Introduction
24
Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But
How to design chips with more and more functions?
Design engineering population does not double every
two years
Hence, a need for more efficient design methods
Exploit different levels of abstraction
2nd
Introduction
25
Design Abstraction Levels
n+ n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
2nd
Introduction
26
Design Metrics
How to evaluate performance of a
digital circuit (gate, block, )?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
2nd
Introduction
27
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area
2nd
Introduction
28
NRE Cost is Increasing
2nd
Introduction
29
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12 (30cm)
2nd
Introduction
30
Cost per Transistor
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
cost:
-per-transistor
Fabrication capital cost per transistor (Moores law)
2nd
Introduction
31
Yield
% 100
per wafer chips of number Total
per wafer chips good of No.
= Y
yield Die per wafer Dies
cost Wafer
cost Die
=
( )
area die 2
diameter wafer
area die
diameter/2 wafer
per wafer Dies
2
t
=
2nd
Introduction
32
Defects
o
|
.
|
\
|
o

+ =
area die area unit per defects
1 yield die
o is approximately 3
4
area) (die cost die f =
2nd
Introduction
33
Some Examples (1994)
Chip Metal
layers
Line
width
Wafer
cost
Def./
cm
2
Area
mm
2
Dies/
wafer
Yield Die
cost
386DX
2 0.90 $900 1.0 43 360 71% $4
486 DX2
3 0.80 $1200 1.0 81 181 54% $12
Power PC
601
4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100
3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha
3 0.70 $1500 1.2 234 53 19% $149
Super Sparc
3 0.70 $1700 1.6 256 48 13% $272
Pentium
3 0.80 $1500 1.5 296 40 9% $417
2nd
Introduction
34
Reliability
Noise in Digital Integrated Circuits
i ( t )
Inductive coupling Capacitive coupling Power and ground
noise
v ( t ) V
DD
2nd
Introduction
35
DC Operation
Voltage Transfer Characteristic
V(x)
V(y)
V
OH
V
OL
V
M

V
OH
V
OL
f
V(y)=V(x)
Switching Threshold
Nominal Voltage Levels
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)
2nd
Introduction
36
Mapping between analog and digital signals
V
IL
V
IH
V
in
Slope = -1
Slope = -1
V
OL
V
OH
V
out
0 V
OL
V
IL
V
IH
V
OH
Undefined
Region
1
2nd
Introduction
37
Definition of Noise Margins
Noise margin high
Noise margin low
V
IH
V
IL
Undefined
Region
"1"
"0"
V
OH
V
OL
NM
H
NM
L
Gate Output
Gate Input
2nd
Introduction
38
Noise Budget
Allocates gross noise margin to
expected sources of noise
Sources: supply noise, cross talk,
interference, offset
Differentiate between fixed and
proportional noise sources
2nd
Introduction
39
Key Reliability Properties
Absolute noise margin values are deceptive
a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)
Noise immunity is the more important metric
the capability to suppress noise sources
Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the
receiver;
2nd
Introduction
40
Regenerative Property
Regenerative Non-Regenerative
2nd
Introduction
41
Regenerative Property
A chain of inverters
v
0
v
1
v
2
v
3
v
4
v
5
v
6
Simulated response
2nd
Introduction
42
Fan-in and Fan-out
N
Fan-out N
Fan-in M
M
2nd
Introduction
43
The Ideal Gate
R
i
=
R
o
= 0
Fanout =
NM
H
= NM
L
= V
DD
/2
g =
V
in
V
out
2nd
Introduction
44
An Old-time Inverter
NM
H
V
in
(V)
V
out
(V)
NM
L
V
M
0.0
1.0
2.0
3.0
4.0
5.0
1.0 2.0 3.0 4.0 5.0
2nd
Introduction
45
Delay Definitions
2nd
Introduction
46
Ring Oscillator
T = 2 t
p
N
2nd
Introduction
47
A First-Order RC Network
v
out
v
in C
R
t
p
= ln (2) t = 0.69 RC
Important model matches delay of inverter
2nd
Introduction
48
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = V
supply
i(t)

Peak power:
P
peak
= V
supply
i
peak

Average power:
( )
} }
+ +
= =
T t
t
T t
t
supply
supply
ave
dt t i
T
V
dt t p
T
P ) (
1
2nd
Introduction
49
Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = P
av
t
p

Energy-Delay Product (EDP) =
quality metric of gate = E t
p

2nd
Introduction
50
A First-Order RC Network
V
dd
V
out
i
supply
C
L
E
0->1
= C
L
V
dd
2
PMOS
NETWORK
NMOS
A
1
A
N
NETWORK
E
0 1
P t ( ) dt
0
T
}
V
dd
i
supply
t ( ) dt
0
T
}
V
dd
C
L
dV
out
0
Vdd
}
C
L
V
dd
-
2
= = = =
E
cap
P
cap
t ( ) dt
0
T
}
V
out
i
cap
t ( )dt
0
T
}
C
L
V
out
dV
out
0
Vdd
}
1
2
--- C
L
V
dd
-
2
= = = =
v
out
v
in C
L
R
2nd
Introduction
51
Summary
Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
Some interesting challenges ahead
Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
Understanding the design metrics that govern
digital design is crucial
Cost, reliability, speed, power and energy
dissipation

Digital Integrated Circuits: A Design Perspective

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