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Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Low Gate Charge to Minimize Switching Losses PbFree Packages are Available
V(BR)DSS 24 V
ID MAX 85 A
Applications
NChannel D
Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt
Single Pulse DraintoSource Avalanche Energy TJ = 25C, VDD = 30 V, VGS = 10 V, IL = 13 Apk, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8 from case for 10 s)
Y WW 85N02R G
ORDERING INFORMATION
TL 260 C
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surfacemounted on FR4 board using 1 sqin pad, 1 oz Cu. 2. Surfacemounted on FR4 board using the minimum recommended pad size.
NTD85N02R
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter JunctiontoCase (Drain) JunctiontoTAB (Drain) JunctiontoAmbient Steady State (Note 1) JunctiontoAmbient Steady State (Note 2) 1. Surfacemounted on FR4 board using 1 sqin pad, 1 oz Cu. 2. Surfacemounted on FR4 board using the minimum recommended pad size. Symbol RqJC RqJCTAB RqJA RqJA Value 1.6 3.5 52 100 Unit C/W
GatetoSource Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient DraintoSource on Resistance
IGSS
VDS = 0 V, VGS = 20 V
1.0
1.5 4
2.0
V mV/C
ID = 20 A ID = 20 A
4.8 6.5 38
5.2 mW S
Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge GatetoSource Charge GatetoDrain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 4) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time
gFS
VDS = 10 V, ID = 15 A
CISS COSS CRSS QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 10 V, VDS = 10 V; ID = 10 A VGS = 5.0 V, VDS = 10 V; ID = 10 A VGS = 0 V, f = 1.0 MHz, VDS = 20 V
6.3 77 25 12 ns
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures.
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NTD85N02R
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Parameter DRAINSOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, IS = 30 A TJ = 25C TJ = 125C 0.81 0.65 37.5 VGS = 0 V, dIS/dt = 100 A/ms, IS = 20 A 16.8 20.7 27 nC ns 1.0 V Symbol Test Condition Min Typ Max Unit
Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge PACKAGE PARASITIC VALUES Source Inductance Drain Inductance, DPAK Drain Inductance, IPAK* Gate Inductance Gate Resistance *Assume standoff of 110 mils.
tRR ta tb QRR
LS LD LD LG RG TA = 25C
nH
ORDERING INFORMATION
Device NTD85N02R NTD85N02RG NTD85N02R001 NTD85N02R1G NTD85N02RT4 NTD85N02RT4G Package DPAK DPAK (PbFree) IPAK IPAK (PbFree) DPAK DPAK (PbFree) 2500 / Tape & Reel 800 / Tape & Reel 75 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NTD85N02R
6V
4.4 V 5V
80
3.2 V 3V
40
0.010 TJ = 125C 0.006 TJ = 25C TJ = 55C 0.002 0 40 80 120 160 ID, DRAIN CURRENT (AMPS)
0.010
TJ = 125C TJ = 25C
VGS = 0 V
TJ = 150C
1000
TJ = 125C
10
15
20
25
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NTD85N02R
POWER MOSFET SWITCHING
VGS , GATETOSOURCE VOLTAGE (VOLTS) 4800 TJ = 25C C, CAPACITANCE (pF) 4000 3200 2400 1600 Coss 800 0 10 VDS = 0 V VGS = 0 V 5 VGS 0 VDS 5 10 15 20 Crss Ciss Crss Ciss 6 QT VGS 4 Q1 Q2
VGS = 0 V
t, TIME (ns)
100
tr td(off)
10
TJ = 25C 0 0.2 0.4 0.6 0.8 VSD, SOURCETODRAIN VOLTAGE (VOLTS) 1.0
100
10 ms 100 ms 1 ms
10
VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10
10 ms dc
0.1
100
Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com
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NTD85N02R
10 Normalized to RqJC at Steady State
0.1
0.01 0.00001
0.0001
0.001
0.1
10
Normalized to RqJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board
0.1
0.01 0.00001
0.0001
0.001
0.01
10
100
1000
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NTD85N02R
PACKAGE DIMENSIONS
T B V R
4
SEATING PLANE
C E
A S
1 2 3
Z H U
F L D 2 PL
DIM A B C D E F H J L R S U V Z
0.13 (0.005)
SOLDERING FOOTPRINT*
6.20 0.244 3.0 0.118
2.58 0.101
5.80 0.228
1.6 0.063
6.172 0.243
SCALE 3:1
mm inches
*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NTD85N02R
PACKAGE DIMENSIONS
B V R
4
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93
Z A
3
S T
SEATING PLANE
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTD85N02R/D