---------------------------------------------------------------------------------- Company:

-- Engineer:
--- Create Date:
08:44:58 10/10/2011
-- Design Name:
-- Module Name:
sum_res - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
entity sum_res is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
SR: in STD_LOGIC;
F: out STD_LOGIC_VECTOR (3 downto 0);
CO: out STD_LOGIC
);
end sum_res;
architecture sum_res of sum_res is
component FA
port (
x,y,Ci: in std_logic;
Co,S: out std_logic
);
end component;
signal c: std_logic_vector (4 downto 0);
signal d: std_logic_vector (3 downto 0);
begin
c(0)<=SR;
d(0)<=B(0)
d(1)<=B(1)
d(2)<=B(2)
d(3)<=B(3)

xor
xor
xor
xor

SR;
SR;
SR;
SR;

FA0:FA
port map (
x=>A(0),
y=>d(0),
Ci=>C(0),
Co=>C(1),
S=>F(0)
);

FA1: FA
port map (
x=>A(1),
y=>d(1),
Ci=>C(1),
Co=>C(2),
S=>F(1)
);
FA2: FA
port map (
x=>A(2),
y=>d(2),
Ci=>C(2),
Co=>C(3),
S=>F(2)
);
FA3: FA
port map (
x=>A(3),
y=>d(3),
Ci=>C(3),
Co=>C(4),
S=>F(3)
);
CO<= C(4);
end sum_res;