ARITHMETIC AND

LOGIC IN COMPUTER
SYSTEMS



Credits to:
Mi Lu,
Texas A&M university

ARITHMETIC AND LOGIC IN

COMPUTER SYSTEMS
:

( )
.

,,
( ).

.

(,, .)
, ,
.
VLSI(32nm
)
-

 1

)Conventional

Radic Number System

d i {0,1.... , r 1 }
0in1

, r (radix)
,

1) bits ?
: log 2 1
2) conventional
radix system?
:

(r),
.
n-1

-
., ,
.
:
-
(diminished radix compliment)
(radix compliment)


RNS(Residue Number System)
LNS(Logarithmic Number System)


,
MSB

Diminished Radix
Compliment
(r-1),

, :
N

Radix Compliment
r

 4 Bit

Signed-Digit
, ,
. , r>1 :

:
non-redudant( ),
( , ,
). .

Singed Digit,
continued
!
signed digit
.
-3 (=-3 , n=4, r=2, (
)=0 ) :

Floating point
numbers
( ,
)
(fixed-point).
,

,

.,
, mantissa()
exponent(E)

Normalization
,
,
MSB(Most Significant Bit) mantissa
0.

, mantissa string k bits

Residue Number
System(RNS)

=(x1,x2....xn) xi>1 .
mi=(m1,m2...mn) .
xi :

x i = X mod
mi

9 RNS :

RNS (104)
mi .
, tradeoff
mi

Logarithmic Number
System(LNS)
- ,
r.
( Lx) n bit
k bits , LNS
:
, :

RNS: RNS
.,
2 RNS
1
.
LNS: ,

.
. LNS
Hidden Markov Models( viterby)

.
:
Time complexity ( ):
.
g
NAND NOR

Area complexity( ) :
( 1 layer).
1 g
NAND NOR.

Time and area

Complexities

Half Adder

Full Adder

Single bit full adder

Single bit AOI(AndOR- invert) adder


, ai bi =d i borrow-out(
carry) bit l .i

,
.
hardware(
) A- +(-)

Subtractor circuit

 1scomplement
Negation Circuit with enable

 2s
complement
2 ,
0 1 1 0
1. , hardware 1's
complement circuit
.

 2s
complement no2

:

,continued

,continued
:

( 2)
( 1).

Full 1bit adder/

subtractor with enable-M

Full 1bit
adder/subtractor

,
=0 =1.
.

Overflow

,overflow() carry MSB

(
) 1.
overflow,
. ( )
overflow 2's complement 2 ( )
n bits .

 overflow

Ripple Carry Adders

adders
n bits carry out LSB
carry in bit .
, overflow.

Ripple Carry
schematic

Ones complemet
addition
+ :
1) :
2.
2) :

,
1.' end-arround carry(Cn
)
3) (||>||)
end-arround Carry,

end-arround carry

Ones complemet
addition

4) , ||<||( end arround carry)

:

mod 2^n ( 1) ,
||-||-1, ||-||.
, implement end arround
carry
, FA 1's complement

Sign- Magnitude
addition

Sign- Magnitude
addition
Pre-Complement(P): 1

Post-Complement(Q): 1
, ||>=||
:
2
(||>=||)
||<|

Sign- Magnitude
addition

High Speed AddersConditional Sum

Addition

,
. Conditional Sum Addition
- bits ,
carry bit ,
.

2 bit
carry-in 0. carry in
1,
:

Conditional Sum
Addition

Circuit of Conditional
Sum

Carry Completion
Sensing Addition
(CCSA)

rippley carry adders ,

carry LSB
MSB( - -
FA MSB carry-out
CCSA's
.
CCSA's 2 carrys, Independent(IC)
Dependent(DC). , IC carry
() bit
carry,
DC IC / DC
bit.

CCSA addition
IC carry

carry IC
DC carry.
:
1: IC carry
2: DC carry
3: 2 IC DC carrys
mod2( carry
2 )

CCSA circuit

CCSA complexities

Carry Look-Ahead
Adition(CLA)

,
CLA
carrys. ,
1)Carry-Lookahead adder
2)Carry- Blockahead adder

Carry lookahead adder

2 n bits.
Carry generation G i= A iBi Carry
propagation function P i= A i exor B i
H carry generation
carry i, carry propagation
carry in bit i carry in
bit i+1.

CLA

To C i1 C i

Carry Look-Ahead
Adder schematic

Carry-Save
adders(CSA)
2,
.

carry-out
, .
carry ( bits
)

CSA algorithm

CSA circuit

CSA vs CLA

Bit-partitioned multiple
addition
, -,
bit .
bits 1
( ROM PLA).,
(
left shift).
.

Bit partitioned addition

of 2 7-digit numbers
7 4 bit

Bit partitioned Adder




.
,
64 bit .


.

 Links

LNS VHDL ALGORITHMS :

http://www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary/
RNS VHDL ALGORITHMS:
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.5398
C++ of VHDL for the transformation of parallel algorithms:
http://www.eda.org/VIUF_proc/Fall95/ANDERSON_R95B.PDF
VHDL carry look-ahead adder( ):
http://www.altera.com/support/examples/vhdl/v_cl_addr.html
Performance Analysis of fast adders using VHDL:
http://www.computer.org/portal/web/csdl/doi/10.1109/ARTCom.2009.132

VHDL codes

VHDL
.

vhdl
.
,
.
, ( ) .

Carry Look-Ahead
adder
vhdl 8bit Carry
look Ahead Adder. carry, ,
P G.
AND-OR 2

carry.

CLA VHDL
implementation
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY c_l_addr IS
PORT
(
x_in
: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
y_in
: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum
: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_out : OUT STD_LOGIC
);
END c_l_addr;
ARCHITECTURE behavioral OF c_l_addr IS
SIGNAL
SIGNAL
SIGNAL
SIGNAL

h_sum
: STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_generate : STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_propagate : STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_in_internal : STD_LOGIC_VECTOR(7 DOWNTO 1);

CLA VHDL
implementation
BEGIN
h_sum <= x_in XOR y_in;
carry_generate <= x_in AND y_in;
carry_propagate <= x_in OR y_in;
PROCESS (carry_generate,carry_propagate,carry_in_internal)
BEGIN
carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND carry_in);
inst: FOR i IN 1 TO 6 LOOP
carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND
carry_in_internal(i));
END LOOP;
carry_out <= carry_generate(7) OR (carry_propagate(7) AND carry_in_internal(7));
END PROCESS;
sum(0) <= h_sum(0) XOR carry_in;
sum(7 DOWNTO 1) <= h_sum(7 DOWNTO 1) XOR carry_in_internal(7 DOWNTO 1);
END behavioral;

Ripple Carry Adder

Ripple
Carry Adder
. altera,
full_add.vhd,
.,

,
Ripple Carry Adder

Ripple Carry Adder

VHDL Example
LIBRARY altera;
USE altera.maxplus2.carry;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY WORK;
USE WORK.usr_def.ALL;
ENTITY f_add8 IS
PORT(
x_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
c_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
c_out : OUT STD_LOGIC);
END f_add8;

Ripple Carry Adder

VHDL Example
ARCHITECTURE struct OF f_add8 IS
SIGNAL im : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL imi : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
c0 : full_add
PORT MAP (x_in(0),y_in(0),c_in,sum(0),im(0));
c01 : carry
PORT MAP (im(0),imi(0));
c : FOR i IN 1 TO 6 GENERATE
c1to6: full_add PORT MAP (x_in(i),y_in(i),
imi(i-1),sum(i),im(i));
c11to16: carry PORT MAP (im(i),imi(i));
END GENERATE;
c7 : full_add PORT MAP (x_in(7),y_in(7),
imi(6),sum(7),c_out);
END struct;

Full Adder VHDL

ripple carry adder (full
adder) VHDL :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY full_add IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c_in : IN STD_LOGIC;
sum : OUT STD_LOGIC;
c_out : OUT STD_LOGIC);
END full_add;
ARCHITECTURE behv OF full_add IS
BEGIN
sum <= a XOR b XOR c_in;
c_out <= (a AND b) OR (c_in AND (a OR b));
END behv;

Conditional Sum
Adder VHDL code
adder 2
16 bits Conditional Sum addition.
,
4 .
1: conditional sums carries i-
bits .
2: bits (level 2 bits)
1 . , bits 1
2. carry
carry
2

Conditional Sum
Adder VHDL code
3: , carrys 3
2 .
4: 2,3.
.
(16bit)
.

Conditional Sum
Adder VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Adder_CS_16bit is
port (a, b: in std_logic_vector(15 downto 0);
cin: in std_logic;
sum: out std_logic_vector(15 downto 0);
cout: out std_logic);
end Adder_CS_16bit;
architecture behavioral of Adder_CS_16bit is
signal s10: std_logic_vector(15 downto 0) := "0000000000000000";
signal s11: std_logic_vector(15 downto 0) := "0000000000000000";
signal c10: std_logic_vector(15 downto 0) := "0000000000000000";
signal c11: std_logic_vector(15 downto 0) := "0000000000000000";
signal s20: std_logic_vector(15 downto 0) := "0000000000000000";
signal s21: std_logic_vector(15 downto 0) := "0000000000000000";
signal c20: std_logic_vector(15 downto 0) := "0000000000000000";
signal c21: std_logic_vector(15 downto 0) := "0000000000000000";
signal s30: std_logic_vector(15 downto 0) := "0000000000000000";
signal s31: std_logic_vector(15 downto 0) := "0000000000000000";
signal c30: std_logic_vector(15 downto 0) := "0000000000000000";
signal c31: std_logic_vector(15 downto 0) := "0000000000000000";
signal s40: std_logic_vector(15 downto 0) := "0000000000000000";
signal s41: std_logic_vector(15 downto 0) := "0000000000000000";
signal c40: std_logic_vector(15 downto 0) := "0000000000000000";
signal c41: std_logic_vector(15 downto 0) := "0000000000000000";
signal P: std_logic := '0';
signal G: std_logic := '0';

Conditional Sum
Adder VHDL code
begin
-- - 1
process (a, b)
begin
P <= a(0) xor b(0);
G <= a(0) and b(0);
end process;
process (a, b, P, G, cin)
begin
s10(0) <= P xor cin;
c10(0) <= G or (P and cin);
for i in 1 to a'length - 1 loop
s10(i) <= a(i) xor b(i);
c10(i) <= a(i) and b(i);
c11(i) <= a(i) or b(i);
end loop;
end process;
process (s10)
begin
s11 <= not s10;
end process;

Conditional Sum
Adder VHDL code
-- 2
process (s10, s11, c10, c11)
begin
s20(0) <= s10(0);
if c10(0) = '1' then
s20(1) <= s11(1);
c20(1) <= c11(1);
elsif c10(0) = '0' then
s20(1) <= s10(1);
c20(1) <= c10(1);
end if;
for i in 2 to a'length - 1 loop
if (i mod 2 = 0) then
s20(i) <= s10(i);
s21(i) <= s11(i);
if c10(i) = '1' then
s20(i+1) <= s11(i+1);
c20(i+1) <= c11(i+1);
elsif c10(i) = '0' then
s20(i+1) <= s10(i+1);
c20(i+1) <= c10(i+1);
end if;

Conditional Sum
Adder VHDL code
if c11(i) = '0' then
s21(i+1) <= s10(i+1);
c21(i+1) <= c10(i+1);
elsif c11(i) = '1' then
s21(i+1) <= s11(i+1);
c21(i+1) <= c11(i+1);
end if;
end if;
end loop;
end process;
-- 3
process (s20, s21, c20, c21)
begin
s30(1 downto 0) <= s20(1 downto 0);
if c20(1) = '1' then
s30(3 downto 2) <= s21(3 downto 2);
c30(3) <= c21(3);
elsif c20(1) = '0' then
s30(3 downto 2) <= s20(3 downto 2);
c30(3) <= c20(3);
end if;

Conditional Sum
Adder VHDL code
for i in 4 to a'length - 1 loop
if (i mod 4 = 1) then
s30(i downto i-1) <= s20(i downto i-1);
s31(i downto i-1) <= s21(i downto i-1);
if c20(i) = '1' then
s30(i+2 downto i+1) <= s21(i+2 downto i+1);
c30(i+2) <= c21(i+2);
elsif c20(i) = '0' then
s30(i+2 downto i+1) <= s20(i+2 downto i+1);
c30(i+2) <= c20(i+2);
end if;
if c21(i) = '0' then
s31(i+2 downto i+1) <= s20(i+2 downto i+1);
c31(i+2) <= c20(i+2);
elsif c21(i) = '1' then
s31(i+2 downto i+1) <= s21(i+2 downto i+1);
c31(i+2) <= c21(i+2);
end if;
end if;
end loop;
end process;

Conditional Sum
Adder VHDL code
-- 4
process (s30, s31, c30, c31)
begin
s40(3 downto 0) <= s30(3 downto 0);
if c30(3) = '1' then
s40(7 downto 4) <= s31(7 downto 4);
c40(7) <= c31(7);
elsif c30(3) = '0' then
s40(7 downto 4) <= s30(7 downto 4);
c40(7) <= c30(7);
end if;
-- level - 4
process (s30, s31, c30, c31)
begin
s40(3 downto 0) <= s30(3 downto 0);
if c30(3) = '1' then
s40(7 downto 4) <= s31(7 downto 4);
c40(7) <= c31(7);
elsif c30(3) = '0' then
s40(7 downto 4) <= s30(7 downto 4);
c40(7) <= c30(7);
end if;

Conditional Sum
Adder VHDL code
c40(i+4) <= c30(i+4);
end if;
if c31(i) = '0' then
s41(i+4 downto i+1) <= s30(i+4 downto i+1);
c41(i+4) <= c30(i+4);
elsif c31(i) = '1' then
s41(i+4 downto i+1) <= s31(i+4 downto i+1);
c41(i+4) <= c31(i+4);
end if;
end if;
end loop;
end process;

Conditional Sum
Adder VHDL code
-- 5
process (s40, s41, c40, c41)
begin
sum(7 downto 0) <= s40(7 downto 0);
if c40(7) = '1' then
sum(15 downto 8) <= s41(15 downto 8);
cout <= c41(15);
elsif c40(7) = '0' then
sum(15 downto 8) <= s40(15 downto 8);
cout <= c40(15);
end if;
end process;
end behavioral;

Sequential
Multiplication

.

add-shift.

:

Signed & Unsigned

Multiplication
A B n-bit .
P=A x B
P 2n-bit.
,
P 2(n-1)+1=2n-1 bits
bit .
,
(dummy) bit bit
most significant bit 2n
bits.
bit 0, bit


.

Pencil-And-Paper
Multiplication
----------Partial Product

Partial Product AND

.

Add-And-Shift
Approach
partial product
, partial product
.
bit bit
, partial product
bit .
O indirect multiplication :

Add-And-Shift
Approach (cont.)

Register Occupation

Hardware for Sequential Multiplication

Indirect Multiplication
Schemes
1. Unsigned Number Multiplication
2. Sign-Magnitude Number Multiplication
3. Ones Complement Number Multiplication
4. Twos Complement Number Multiplication

Unsigned Number
Multiplication
H
n+1 (n bit
).
C0

C1,...,Cn

.

Sign-Magnitude Number
Multiplication
H n
.
C0

bit
FF As Bs
MSB
AX MR
.

A s Bs

Ones Complement
Number Multiplication
H n+2
.
C0

C1

.
C2 Cn
loop

Cn+1

.

Twos Complement
Number Multiplication
H n+4
.
C0
,
C1

C2
.
C3 Cn+1
loop

Cn+2 Cn+3

Robertsons Signed Number

Multiplication

pre post complemement

,
.
Robertson
.

Negative Multiplicand Times

Positive Multiplier

Negative Multiplicand Times

Negative Multiplier

Recoding
Technique
1. Non-Overlapped Multiple Bit Scanning
2. Overlapped Multiple Bit Scanning
3. Booths Algorithm
4. Canonical Multiplier Recoding

Non-Overlapped Multiple
Bit Scanning

Single Bit Scanning

Multiple Bit Scanning

Overlapped Multiple Bit

Scanning

String Property of a conventional radix

1
string
of 1s

1
beginning of string
1 0
string.
long string 1

begging of string end of
1
string 1
0

Overlapped Multiple Bit

Scanning (cont.)
,
,

string .

Recoding Triplets

Non-Overlapped Vs. Overlapped

Multiple Bit Scanning
To 0
LSB string
LSB 1

beginning of string isolated 1
O

.




.

Two-Bit Scan vs. Overlapped Three-Bit Scan

Booths
Algorithm
string property ,
B D, 2 bit B
bit D :

string of 1s 0
, dummy 0 LSB string.
O ,

.

Booths Algorithm
(cont.)
:

Booth :

2
, pre
post-complement.

Booths

Algorithm
(example)

Radix-4

Booths Algorithm Example

Canonical

Multiplier
Recoding

signed-digit (SD).
minimal SD .
canonical SD minimal SD D=dn-1d1d0
- di x di-1=0 1 i n-1.
D=dndn-1d1d0
n+1 bits dn 0.
canonical (n+1)/2 bit..

(n+1)-bit number to (n+1)-bit canonical SD number algorithm

Canonical Multiplier
Recoding (example)

Scan Pattern

Canonical Multiplier
Recoding (example)

Multiples Selection

Canonical Multiplier
Recoding (example)

Adding the Bit-Pairs Parallelly Scanned

with a CSA Tree

Parallel
Multiplication
,

.

.

.

Wallace Trees

.

.
Wallace tree slice-bit
bit bit position.

Wallace Trees (cont.)

Unsigned Array
Multiplier

Unsigned Array
Multiplier (cont.)
summands

-------------->
---------------------->
------------------------------>
-------------------------------------->
----------------------------------------------->

5 5 Multiplication Example

Partial Products

Unsigned Array
Multiplier (cont.)
H FA
Carry
Lookahead Adder


.

latch registers
FA.



.

Twos Complement
Array Multiplier
:

i 1-i 0 1 .

Twos Complement Array

Multiplier (cont.)


.

Baugh-Wooley Twos
Complement Multiplier

Baugh-Wooley Twos
Complement Multiplier(cont.)
O .
:

BW=[2(m+n) + 1]g

Baugh-Wooley Twos Complement

Multiplier(example)

Modular Structure

.

Modular
Structure(example)

Baugh-Wooley Twos
Complement Multiplier(cont.)

Additive Multiply
Modules

AMM

.

Additive Multiply
Modules(example)

Additive Multiply
Modules(example)

Sequential Division

Substract And-Shift
Approach

,
:
,
j=0,1,...,n-1, o
R(j)

, j-
R(0) ,
R(n) ,

,o

Pencil-And-Paper
Division

Pencil-And-Paper Division Example

Long Division Form

O R(0) D
.
R(0)=r0.r1r2....
D=d0.d1d2....

Q=q0.q1q2....q(n)

R(0)<D , D0
R(0)D

Restoring Division

: 0R(0)<D
D
.
T D (restoring)
To :q(j+1)=(number of
subtractions -1).

Binary Restoring
Division

R(j+1) , q(j+1)=1.
R(j+1) , q(j+1)=0.

Binary Restoring
Division Hardware

Binary Non-Restoring
Division
(restoring
addition).
:

D>0.

H
:

2R(j)=0 .

High-Radix NonRestoring Division

To : {-(r-1),,-1,1,,(r-1)} , r .
D < Rj < D
Q=.q1q2...qn
.
r=4 qj+1 {-3,-2,-1,1,2,3}
- 4D < 4R(j) < 4D

High Radix Non -Restoring

Division (cont.)


r
r ,
Q=q 0.q1q2....

SRT Division
Sweeney, Robertson & Tocher------>SRT

qj+1 {-1, 0, 1}

(D R ).

SRT Division (cont.)

Robertsons HighRadix Division

1. To R(j) .
2.
1/r.
3. .

Robertson Diagrams

Convergence
Division
To
.
.

.

.
1 .

Convergence Division
Methodologies

m:

N D
:

Convergence Division
Methodologies (cont.)
Ri :

Ri Ri = 2 Di-1

The end!