The Serial Peripheral InterIace (SPI) allows high-speed synchronous data transIer between diIIerent

devices. Devices can communicate using a master-slave scheme, and data are transIerred both to and Irom
the devices simultaneously.

PORTC, PORTD, PORTE, and PORTF each have one SPI. Notation oI these peripherals are
SPIC, SPID, SPIE, and SPIF.

MOSI (Master Out / Slave In): This pin is used Ior serial data output Irom the C8051F30x, and should
be conIigured as a digital push-pull output.

MISO (Master In / Slave Out): This pin is used Ior serial data input Irom the slave device, and should
be conIigured as an open-drain digital pin.

ATXMEGA as SPI Master
This sample demonstrates the Xmega128A1 SPI master mode
There are 4 SPI interIaces on the XMEGA. You need to speciIy SPIC, SPID, SPIE or SPIF Ior SPIx. The
value must be HARD. The SPI settings Ior the XMEGA diIIer Irom the SPI settings Ior normal AVR
chips. In order to be able to use the Iour diIIerent SPI interIaces the XMEGA uses a channel which you
need to OPEN. AIter you have opened the device, you can send/receive data using PRINT and INPUT.
The SS pin, MOSI and CLOCK pins are set to output mode automatic in master mode.

The SS pin is also made high. The SS pin is only conIigured when you have selected SSAUTO.
See datasheet Ior Alternate Pin Functions. For example Ior SPI on Port E the SS Pin is PINE.4

II you need to use a diIIerent pin Ior SS or when you need to switch the logic level yourselI Ior SS, and
thus you use the SSNONE option, you must setup the SS pin, even iI you do not use it, yourselI.
You must prevent that the SS pin will be made low in input mode since that will set the SPI into SLAVE
mode, even while it was in MASTER mode.

Config Spie Hard , Master Yes , Mode 0 , Clockdiv Clk2 , Data_order Msb , Ss Auto

ATXMEGA as SPI SLAVE

The max. SPI Clock Rate in SLAVE MODE is 32MHz/CLK4 8MHz