H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Tm t t
B n kha lu n t t nghi p g m c ba ph n ring bi t trong ph n m t l l thuy t b khuy ch i lock-in ti p theo l t ng quan chung c u trc vi i u khi n dsPic30F4011 v cu i cng l ph n th c nghi m. Chng 1 v l thuy t b khuy ch i lock-in tr c tin ta s tm hi u t i sao l i ph i dng b khuy ch i lock-in trong o l ng tn hi u nh v khi ni m b khuy ch lock-in, ti p theo l s c u t o chung c a m t b khuy ch i lock-in c i n. Cu i cng l ph n tm hi u c u t o v nguyn t c ho t ng c a b khuy ch i lock-in s v tng t . Trong chng 2 v t ng quan c u trc c a vi i u khi n dsPic30F4011 chng ta s tm hi u chung v h vi i u khi n DsPic30F ti p l c i m chung c a h vi i u khi n dsPic30F4011. Cu i cng ta s tm hi u su hn v c u trc c a vi i u khi n dsPic30F4011. Ph n cn l i c a b n kha lu n s l ph n th c nghi m, y trnh by ton b qu trnh thi t k b khuy ch i lock-in g m c ph n c ng, ph n m m v k t qu th c nghi m. Ph n c ng c cc kh i ring bi t, v i m i kh i c trnh by l thuy t v c s thi t k . Cn ph n m m c trnh by d i d ng s kh i c a c u trc chng trnh v i cc modul ring bi t. Sau khi thi t k c b khuy ch i lock-in s , ta s th nghi m m t h o cho c m bi n c nhn l b khuy ch i lockin v a ch t o. C th trong b n kha lu n s th nghi m m t h p su t MPX2300D do cng ty Motorola cung c p. o p d ng cho c m bi n

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

M CL C
M u ................................................................................................................................1 i Lock In...................................................................................2 i lock in ........................................................................2

Chng 1. B Khu ch

1.1. T ng quan v b khuy ch

1.1.1. Gi i thi u.............................................................................................................2 1.1.2. Khi ni m lock in amplifier.............................................................................6 1.1.3. C u trc chung c a b khuy ch 1.2. B khuy ch 1.3. B khuy ch i lock in ........................................................6

i lock in tng t (Analog Lock-In Amplifiers)...............................7 i lock in s (Digital Lock-In Amplifiers)..........................................9

Chng 2. Vi i u Khi n DsPic30F4011 .......................................................................11 2.1. Gi i thi u chung v h vi i u khi n Dspic ............................................................11 2.2. c i m chung c a vi i u khi n dsPic30F4011...................................................11

2.2.1. Kh i x l trung tm CPU ................................................................................11 2.2.2. B chuy n i tng t s ADC.......................................................................12

2.2.3. Cc c ng vo ra I/O Port v cc ngo i vi.........................................................12 2.2.4. B x l tn hi u s ...........................................................................................12 2.2.5. M t s c i m khc .......................................................................................13

2.3. C u trc c a vi i u khi n dsPic30F4011 ...............................................................13 2.3.1. Kh i x l trung tm CPU ................................................................................13 2.3.2. Kh i t o 2.3.2.1. Ch 2.3.2.2. Ch a ch AGU .......................................................................................17 a ch l nh .....................................................................................17 o bit a ch .................................................................................19

2.3.3. T ch c b nh v b nh chng trnh...........................................................20 2.3.3.1. Khng gian a ch chng trnh................................................................20

2.3.3.2. Truy xu t d li u t b nh chng trnh s d ng cc l nh b ng .............21

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

2.3.3.3. Truy xu t d li u t b nh chng trnh s d ng khng gian chng trnh..........................................................................................................................21 2.3.4. Cc c ng vo ra I/O Port...................................................................................23 2.3.5. Ng t v c ch ng t...........................................................................................25 2.3.6. Cc b nh th i ................................................................................................27 i tng t s ADC.......................................................................30 i A/D.....................................................................30 i A/D...............................................................30

2.3.7. B chuy n 2.3.7.1. B

m k t qu bi n

2.3.7.2. Cc b c th c hi n bi n

Chng 3. Th c Nghi m..................................................................................................33 3.1. Ph n C ng................................................................................................................33 3.1.1. Cc kh i ngu n .................................................................................................34 3.1.2. Kh i cc b l c thng th p ...............................................................................35 3.1.3. Kh i bi n 3.1.3.1. Ho t i DAC ...........................................................................................36 ng c a DAC v tnh ch t c a n ....................................................36 i DA ...........................................................38

3.1.3.2. Cc tham s c a b chuy n

3.1.3.3. Cc m ch DAC i n hnh...........................................................................39 3.1.3.4. Ghp n i ADC v i vi i u khi n................................................................41 3.1.3.5. B bi n 3.1.4. Kh i khuy ch i DAC s d ng trong kha lu n ................................................41 i tn hi u vo ..........................................................................43 i thu t ton v tnh ch t c a n ......43

3.1.4.1. Tm hi u v m t s m ch khuy ch 3.1.4.2. B khuy ch

i s d ng trong kha lu n (AD620) ...................................47

3.1.5. Kh i LCD..........................................................................................................48 3.1.6. Kh i x l trung tm .........................................................................................49 3.2. Ph n M m ................................................................................................................49 3.3. Cc k t qu th c nghi m .........................................................................................51

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

3.3.1. M ch khuy ch

i lock-in ch t o v tn hi u vo ra lock in.......................51 i lock-in v i c m bi n p su t MPX2300D............55

3.3.2.Th nghi m b khuy ch

3.3.2.1. C m bi n p su t MPX2300D....................................................................55 3.3.2.2. K t qu th nghi m .....................................................................................56 K t Lu n ............................................................................................................................59 Ph L c..............................................................................................................................60

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

B ng cc k hi u, ch vi t t t
V K ADC DAC K TT AC DC : : : : : : Vi i u khi n Chuy n Chuy n Khuy ch i tng t s (Analog digital convert) i s tng t (Digital analog convert) i thu t ton

Dng i n xoay chi u Dng i n m t chi u

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

V i s pht tri n m nh hi n nay c a vi c ng d ng cc c m bi n th vi c thi t k nh ng h o v kh o st c m bi n l r t c n thi t, n l m t thi t b khng th thi u cho b t k m t phng th nghi m no. M t h o nh y v c chnh xc cao cn c ng d ng trong y h c, chnh l nh ng my xt nghi m y sinh. Ngoi ra n cn c ngha quan tr ng t i nhi u ng d ng c n chnh xc cao trong khoa h c k thu t (v d nh: o l ng chnh xc, robotic, ....) Nhi u c m bi n c thi t k c l i ra i n p r t nh , chnh v v y vi c pht hi n s sai l ch v o i n p ra l r t kh khn. Do t ng thi t k m t h o l ng c nh y cao cho nh ng c m bi n ny l r t quan tr ng, v m t trong nh ng t ng l h o c s d ng b khuy ch i lock-in. V i nhn l m t b khuy ch i lock-in chng ta s c c m t h o sensor kh l t ng, n c th cung c p nh ng php o phn gi i cao nh ng tn hi u m t cch tng i s ch v i l n v t n s ring bi t. Vi c thi t k m t h o m c nhn l b khuy ch i lock-in c i n cng kh ph c t p v trong b khuy ch i c n c cc b tr n knh v b l c c chnh xc cao. Ngoi ra trong b khuy ch i lock-in tng t th nh h ng t vi c tri nhi t v gi ha c a cc linh ki n s gy ra s sai s l n cho h o. Nhng n u ta thi t k m t b khuy ch i lock-in s th kh thi hn nhi u. V i cng ngh s , m t vi i u khi n c th m nhi m t t vai tr l b b l c v b tr n knh c chnh xc cao. V c s ha nn s khng c hi n t ng tri nhi t v gi ha linh ki n gy sai s nh h ng t i h o.Chnh v v y m t b khuy ch i lock-in s l l a ch n thng minh nh t c a ng i s d ng. i lock-in s d a V Trong kha lu n ny em s tm hi u thi t k m t b khuy ch

trn vi i u khi n DsPic. V t hnh thnh nn m t h o n gi n v i nhn l b khuy ch i lock-in s v s th nghi m h o v i c m bi n p su t MPX2300D c a Motorola.

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Chng 1. B Khu ch
1.1. T ng quan v b khuy ch 1.1.1. Gi i thi u Trong r t nhi u ng d ng i lock in

i Lock In

o nh ng tn hi u AC r t b c th b t i vi nanovolts

ng i ta khng th s d ng php o thng th ng (s d ng cc my o v n nng ch ng h n). chnh l nguyn nhn ra i c a b khuy ch i lock in (lock-in amplifier). V y t i sao ta l i khng d dng o c nh ng tn hi u AC nh (vi nanovolts)? Ta xt cc v d sau.[8] V d 1: Cho m t tn hi u sng sine 10nV t n s 10kHz. R rng l s khuy ch i c n ph i cho ra tn hi u l n hn n. M t b khu ch i t t (low-noise) s c m t nl i vo kho ng 5nV/sqrt(Hz). N u bng thng c a b khuy ch i l 100kHz v h s khuy ch i l 1000 l n, chng ta thu c l i ra: Tn hi u l i ra: (10nV x 1000) = 10uV

Tn hi u nhi u d i r ng: (5nV x Nh v y chng ta khng c nhi u c h i

100 KHz x 1000)=1,6mV

o tn hi u ny n u chng ta khng ch n ra

t n s chng ta mong mu n.(Xem minh h a trn Hnh 1.1) V d 2: N u ta l p thm m t b l c d i thng vo b khuy ch i v i Q=100 (m t b l c c c k t t Q y c xem l h s ph m ch t c a b l c) tm thng l 10kHz, b t k tn hi u no trong vng 100Hz (10kHz/Q) xung quanh tm cng s Nhi u trong tr ng h p ny s l (5nV x c pht hi n.

100 Hz x 1000) = 50uV, v tn hi u s v n l

10uV. Nhi u l i ra v n l n hn nhi u l n tn hi u, v khng th t o ra c m t php o chnh xc. Nh v y tng h s khu ch i khng th no gip tng t s tn hi u trn n (S/N).(Xem minh h a trn Hnh 1.2) V y mu n o c tn hi u, ta ph i thi t k m t b l c c h s Q l n, nhng vi c ny l r t kh v khng kh thi.Tuy nhin m t b d nh y pha (Phase Sensitive Detector) c th c Q l n c 10000. Nn n trong tn hi u nu 2 v d trn ch cn l 10u.

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 1.1. Nhi u v tn hi u[2]

Hnh 1.2. n b tri t tiu sau khi qua b l c thng th p[2] K thu t d nh y pha (Phase-Sensitive Detection) : C th ni B d nh y pha - Phase Sensitive Detection (PSD) l tri tim c a b khuy ch i lock in, n c xem nh l m t b hon i u hay b tr n. My d tm c v n hnh b i vi c nhn ln hai tn hi u cng nhau. Phn tch sau y ch ra t i sao n cho ta nh ng tn hi u mong mu n. Hnh 1.3 ch ra v tr u b khuy ch i lock in pht hi n ra m t ng tn hi u khng t p nhi u (noise-free) hnh sin. Xc nh trong s nh Signal In. Thi t b

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

c nui v i ngu n tn hi u tham chi u (hay cn g i l tn hi u reference l d ng tn hi u hnh sin, c ci t s n).

Hnh 1.3.Tn hi u, tn hi u tham chi u v tch c a hai tn hi u[15] B d nh y pha c v n hnh b i vi c nhn hai tn hi u ny v k t q a l ta thu c tn hi u Demodulator Output nh trn hnh. T ta th y khng c s khc pha gi a tn hi u vo v tn hi u reference. Demodulator output gi d ng hnh sin, nhng t n s th g p 2 l n t n s c a tn hi u reference, m c trung bnh l dng. Hnh 1.4 cng nh hnh 1.3 nhng c s d ch pha 900 c a tn hi u reference. By gi Demodulator output v n l m t sng sin c t n s b ng hai l n t n s tn hi u reference, nhng m c trung bnh th b ng 0.

Hnh 1.4. Tn hi u, tn hi u tham chi u d ch 90o v tch c a hai tn hi u[15]

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

T -

y ta c th nhn th y m c trung bnh l: c a tn hi u vo v tn hi u reference.

T l v i tch s c a t n s bin

Lin quan t i gc pha gi a tn hi u vo v tn hi u reference.

N s c nh gi n u bin tn hi u reference c gi t i m t gi tr c nh v pha c a tn hi u reference c i u ch nh m b o m t chuy n d ch pha tng i b ng zero. Sau c th o xc nh c m c trung bnh bin tn hi u u vo. M c trung bnh t t nhin l thnh ph n DC c a l i ra c gi i bi n i u (demodulator output). l y c thnh phn m t chi u ny r t n gi n, ta ch c n cho tn hi u qua b l c thng th p. Sau khi c l c, tn hi u DC c o b ng phng php truy n th ng (dng vn k ). trn ta xt n tr ng h p tn hi u vo l m t tn hi u s ch khng c n. Nhng trong nh ng ng d ng th c t tn hi u vo lun i km v i n nhi u. n nhi u ny khng c t n s c nh ho c khng c m i quan h pha c nh. n ny cng c nhn ln v i tn hi u reference, nhng khng a ra b t k m c thay i DC no. Xt m t tn hi u vo c d ng hnh sin, tn hi u ny khng c n: Vin=Acos(t), y =2F, F l t n s tn hi u vo. Trong b khuy ch i lock in c cung c p m t tn hi u reference c cng t n s v i tn hi u vo c d ng sau: Vref = Bcos(t + ), l l ch pha gi a 2 tn hi u. N u ta nhn 2 tn hi u ny v i nhau ta c : Vout = A cos (t) . B cos (t + ) = AB cost (cos t cos - sin t sin ) = AB(cos2t cos - cos t sin t sin ) = AB(( + cos 2t)cos - sin 2t sin ) = AB((1+ cos 2t)cos - sin 2t sin ) = AB(cos + cos 2t cos - sin 2t sin ) = ABcos + AB(cos 2t cos - sin 2t sin ) = ABcos + ABcos(2t + )

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

By gi n u ta cho tn hi u ra Vout qua b l c thng th p th i u hi n nhin l thnh ph n 2t s b lo i b . V y k t qu l ta ch cn l i tn hi u DC (m t chi u). V i u d n t i Vout =ABcos t l v i bin tn hi u vo Vin. Thu t ton ny cho ta m t t ng v vi c bi n m t tn hi u AC thnh DC c gi tr b ng bin c a AC ban u nhn v i N l n. Trong nh ng hon c nh th c t , tn hi u u vo th ng i km v i nhi u n, nhng n u chng ta ci t m t b l c thng th p ph h p u ra c a tn hi u th m i tn hi u nhi u v i m i quan h pha khc nhau v v y th b t k t n s khc nhau no c th b lo i b tn hi u cu i cng. 1.1.2. Khi ni m lock in amplifier B khuy ch i lock in cn b n l thi t b v i kh nng kp. N c th khi ph c nh ng tn hi u trong s c m t c a nhi u n. Ni m t cch khc, n c th cung c p nh ng php o phn gi i cao nh ng tn hi u m t cch tng i s ch v i l n v t n s ring bi t. Tuy nhin, nh ng thi t b hi n i a ra nhi u hn hai ch c nng c b n trn. V d m t b khuy ch i lock in hi n i c th c nh ng ch c nng sau: - Thi t b khi ph c tn hi u AC - o pha - o ti ng n, nhi u. - Vn k vector - B phn tch ph -..v.v......... Chnh v tnh linh ho t ny m n c ngha r t quan tr ng trong b t k m t phng th nghi m no. 1.1.3. C u trc chung c a b khuy ch i lock in

B khuy ch i lock-in g m c cc thnh ph n chnh l : b khuy ch i tn hi u vo v ra, b l c thng d i (bandpass filter), b tr n (mixer), b l c thng th p (lowpass filter) v b pht tn hi u reference.(Hnh 1.5)

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 1.5. S

b khuy ch

i lock in [15]

C hai cch th c thi s trn. Trong phng php c i n t t c cc ch c nng c a b lock-in u c th c hi n b ng k thu t analog (tng t ). Nhng cng c m t phng php khc c th th c thi s trn, l phng php d a trn k thu t s (digital). Chnh v v y c hai cch ch t o b khuy ch i lock-in : b khuy ch i lock-in tng t v b khuy ch 1.2. B khuy ch S tng t i lock-in s s c trnh by d i y.

i lock in tng t (Analog Lock-In Amplifiers) i lock in c i n hay b khuy ch i lock-in

kh i c a m t b khuy ch c ch ra trn Hnh 1.6.

H th ng g m c m t my khuy ch i tng tn hi u u vo c n o n m t m c thch h p cho cc thao tc sau. M t b l c thng d i c dng lo i b b t k thnh ph n tn hi u no ho c t i m c DC ho c t i nh ng ha m c a tn hi u c o. Ti p n l m t my d nh y pha (Phase Sensitive Detector), cn c g i l m t b hon i u(gi i bi n i u) ng b (synchronous demodulator ) ho c b tr n (mixer). M ch ny c th c nhi u d ng, t b khuy ch i logarit n cc b nhn four quadrant. Tn hi u vo c nhn v i m t tn hi u reference c a ra t h th ng ang c o. Tn hi u reference c n c m t m t tng quan pha c nh v i tn hi u vo. V v y b khuy ch i lock-in pht ra m t sng sin reference n i t i c a chnh n nh m t vng kha pha (phase-locked-loop) kha vo tn hi u reference c a tn hi u. Trong qu trnh x l tn hi u ti p theo ta, th ng dng ch c nng knh kp. Trong tr ng h p ny tn hi u vo c tr n u v i tn hi u reference, v ngoi ra tn hi u ny cng c tr n v i tn hi u reference sau khi c d ch pha 900.

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 1.6. S

kh i b khuy ch

i lock-in tng t [8]

Ch c nng knh kp ny c tc d ng l n t i s tnh ton l n c a tn hi u vo v m i tng quan pha c a n v i tn hi u reference. Hai knh ring bi t ny th ng c g i l thnh ph n cng pha (In-Phase component) v thnh ph n vung pha (Quadrature component) ho c tng ng l I v Q. Cu i cng, u ra t nh ng b tr n (mixer) c a vo b l c thng th p c kh nng lo i b m i tn hi u khng ng b (non-coherent), l i m t tn hi u DC cu i cng t l v i bin v pha c a tn hi u vo. C m t s v n v i b khuy ch i lock-in tng t . c m t s chnh xc cao, tn hi u reference ph i c hm l ng sng hi r t th p. N ph i l m t sng hnh sin thu n khi t, b t k hm l ng sng hi no s gy ra s bi n d ng t i u ra. Nh ng my pht sng hnh sin tng t c th cng ch u t nh ng bi n i bin gy b i s bi n i c a nhi t . S tri nhi t v sai s c a cc linh ki n trong h th ng cng c th gy ra nh ng v n khc n a cho h th ng tng t . Cu i cng, c n ni thm r ng b t k m t phi tuy n no trong h s khuy ch i v pha cng c th d n n cc sai s trong tn hi u ra. Vi c kh c ph c cc v n ny khi n cho b khuy ch i lock-in tng t tr nn m t thi t b r t t v c s d ng khi i h i cc bng thng l i vo cao.

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

1.3. B khuy ch S

i lock in s (Digital Lock-In Amplifiers) i lock in s c ch ra trn Hnh 1.7

kh i c a m t b khuy ch

Hnh 1.7. B khuy ch

i lock in s [8]

Trong m t b khuy ch i lock in s , ph n l n cc qu trnh x l c th c hi n trong mi n s s d ng ph n m m v dng ph n c ng l b x l tn hi u s (DSP). Hnh 1.7 l m t b khuy ch i s i n hnh, h th ng ny cng c m t b khuy ch i fron-end nhng n c n i b i m t b l c Anti-alias Filter dng l c b t k tn hi u no c t n s l n hn n a t n s l y m u. B i u khi n tn hi u s (Digital signal controller) y c th s d ng nhi u lo i chip x l s chuyn d ng, v d nh dsPic ch ng h n (dsPic l m t chip x l s tng i m nh, t c cao). Tn hi u reference trong b khuy ch i lock in s c th c t o ra bn trong ho c bn ngoi. Trong tr ng h p tn hi u c pht sinh n i t i, nh ng i m m u ring l c a tn hi u reference c th tnh ton t i m t m c chnh xc cao, v b i v y khng c nh ng sai s th ng g p khi dng tn hi u reference nh trong cc my lock-in tng t . Tn hi u reference trong b khuy ch i lock-in s c d ch pha 900 r t n gi n b ng cch tra c u b ng ho c b ng nh ng php ton n gi n. Ti p theo tn hi u reference v tn hi u d ch pha reference c nhn v i tn hi u vo b i DSP v sinh ra ra 2 knh tn hi u,

Sinh Vin : L Tr n Tri u Tu n

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

m t knh tn hi u

ng pha I v m t knh tn hi u vung pha Q. Cu i cng nh ng knh y l b l c s FIR) thu

tn hi u ny c cho qua m t b l c thng th p s (c th c nh ng k t q a cu i cng. Do tn hi u vo c s ha b i b chuy n m r t th p.

i ADC nn s khng b m t mt. Hn

n a, v tn hi u tham chi u (reference) c tnh b ng phng php s nn c l ng ha i u quan tr ng n a l s l ch gy b i tnh phi tuy n c a h s khuy ch i v pha c a cc linh ki n tng t s b tri t tiu trong b khuy ch i lock-in s v s khng c cc sai l ch gy b i s tri nhi t ho c s gi ha c a cc linh ki n. Cu i cng b vi x l s tnh ton l n vector c a tn hi u ra v tn hi u l i vo so v i tn hi u reference qua cng th c sau : l ch pha c a

Magnitude= I 2 + Q 2

Phase = tan 1 (Q / I )

Sinh Vin : L Tr n Tri u Tu n

10

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Chng 2. Vi i u Khi n DsPic30F4011

Trong b n kha lu n ny b x l s c a m ch khuy ch i lock-in s dng m t vi i u khi n DsPic v i nhn hi u thng m i l DsPic30F4011 c a hng Microchip. Ton b n i dung chng 2 ny c l y t ti li u [6]. 2.1. Gi i thi u chung v h vi i u khi n Dspic H vi i u khi n 16 bit dsPic do cng ty cng ngh Microchip Technology Inc. s n xu t, c pht tri n trn n n h vi i u khi n 8 bit Pic. Vi i u khi n dsPic l m t chip x l m nh v i b x l 16 bit (c kh nng x l d li u c di 16 bit). V i t c tnh ton cao d a trn ki n trc RISC, k t h p cc ch c nng i u khi n ti n ch c a m t b vi i u khi n hi u nng cao 16-bit (highperformance 16-bit microcontroller), c th th c hi n ch c nng c a m t b x l tn hi u s (DSP) nn dsPIC cn c th c xem l m t b i u khi n tn hi u s (Digital Signal Controller DSC). H vi i u khi n dsPic c th tt it c x l 40 MIPS (Mega Instruction Per Second - tri u l nh trn m t giy). Ngoi ra dsPic cn c trang b b nh Flash, b nh d li u EEPROM v cc ngo i vi hi u nng cao v r t a d ng cc th vi n ph n m m cho php th c hi n cc gi i thu t nhng v i hi u su t cao m t cch d dng trong m t kho ng th i gian ng n. Chnh v v y dsPic c ng d ng r t r ng ri trong cc ng d ng x l tn hi u s , o l ng v i u khi n t ng, .v..v... H vi i u khi n dsPic c chia ra lm ba lo i ty theo m c ch c a ng i s d ng : 2.2. B i u khi n s cho i u khi n motor v bi n Power Conversion Family) B B i ngu n (DSC Motor Control &

i u khi n s cho sensor (DSC Sensor Family) i u khi n s a m c ch (DSC General Purpose Family)

c i m chung c a vi i u khi n dsPic30F4011

2.2.1. Kh i x l trung tm CPU - T p l nh c b n g m 84 l nh

Sinh Vin : L Tr n Tri u Tu n

11

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

- Ch -

nh

a ch linh ho t di d li u 16-bit

di l nh 24-bit,

- B nh chng trnh Flash 24 Kbytes - B nh RAM l n 1Kbytes

- B nh EEPROM - M ng 16 thanh ghi lm vi c 16-bit -T c lm vi c ln t i 40 MIPS i tng t s ADC i tng t - s (ADC) 10-bit l y m u t i a 1 Msps (Mega samples per second)

2.2.2. B chuy n - B chuy n +T c

+ T i a 10 knh l i vo ADC + Th c hi n bi n - Ch i c trong ch Sleep v Idle

nh n bi t i n th th p kh l p trnh

- T o Reset b ng nh n di n i n p kh l p trnh 2.2.3. Cc c ng vo ra I/O Port v cc ngo i vi - Dng ra, vo cc chn I/O l n: 25 mA

- 3 Timer 16-bit, c th ghp 2 Timer 16-bit thnh Timer 32-bit - Ch c nng Capture 16-bit - Cc b so snh/PWM 16-bit - Module SPI 3 dy (h tr ch - Module I2C, h tr ch - UART c kh nng 2.2.4. B x l tn hi u s - N p d li u song song - Hai thanh ch a 40-bit c h tr bo ho logic Frame) a ch t 7-bit m FIFO n 10-bit

a ch t ,

a ch ho, h tr b

Sinh Vin : L Tr n Tri u Tu n

12

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

- Th c hi n php nhn 2 s 17-bit trong m t chu k my - T t c cc l nh DSP u th c hi n trong m t chu k my

- D ch tri ho c ph i 16 bit trong m t chu k my 2.2.5. M t s c i m khc

- B nh Flash: ghi/xo ln t i 10.000 l n ( i u ki n cng nghi p) v trn d i 100.000 l n (thng th ng) - B nh EEPROM: ghi/xo ln t i 100.000 l n ( i u ki n cng nghi p) v trn d i 1.000.000 l n (thng th ng) - Kh nng t n p trnh d i i u khi n c a software - Watch Dog Timer m m d o v i b dao - Ch b o v firmware kh l p trnh ng RC ngu n th p trn chip.

- Kh nng t l p trnh n i ti p trn m ch i n (In Circuit Serial Programming ICSP) - C th l a ch n cc ch qu n l ngu n: Sleep ho c Idle

2.3. C u trc c a vi i u khi n dsPic30F4011 2.3.1. Kh i x l trung tm CPU CPU c a dsPic30F4011 c thi t k trn ki n trc RISC, nhn c a CPU c m t b x l l nh 24-bit v b m chng trnh Program Counter (PC) r ng 23-bit v i bit ngha th p nh t lun b ng 0, cn bt ngha cao nh t th c b qua trong su t qu trnh th c hi n chng trnh bnh th ng, ch tr khi th c hi n cc l nh c bi t. Do , b m chng trnh c th nh a ch ln t i 4 tri u t l nh c a khng gian b nh chng trnh c s d ng. Thi t b dsPIC30F ch a 16 thanh ghi lm vi c 16-bit. M i thanh ghi lm vi c c th c th lm vi c v i vai tr nh d li u, th 16 (W15) ho t a ch ho c thanh ghi a ch offset. Thanh ghi ng ng t v g i ng t. ng nh l con tr ngn x p m m cho ho t

Cc ch l nh c a dsPIC30F g m 2 l p: L p MCU v L p DSP c a l nh. Hai l p ny c k t h p ng nh t v i nhau trong ki n trc v th c hi n t m t kh i th c hi n n.

Sinh Vin : L Tr n Tri u Tu n

13

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Cc ch l nh bao g m nhi u ch bin d ch ngn ng C.

a ch v c ch t o nh m tng thch v i trnh

Khng gian d li u c th c a ch ho thnh 32K words ho c 64 Kbytes v c chia lm hai kh i, c g i l b nh d li u X v b nh d li u Y. M i kh i u c kh i t o a ch - AGU (Adress Generator Unit) ring bi t c a n. T t c cc l nh ho t ng n c ch qua b nh X, v kh i AGU quy nh s xu t hi n c a m t vng d li u th ng nh t. L p thanh ch a php nhn (Multiply-Accumulate) MAC c a l nh DSP ho t ng thng qua c hai kh i AGU c a b nh X v Y, n chia a ch d li u thnh hai ph n. M i t d li u g m 2-bytes, v t t c cc l nh c th nh a ch d li u theo bytes ho c words (t ). C hai cch truy xu t d li u trong b nh chng trnh l:

- 32 Kbytes cao c a vng nh d li u c th c s p x p trong n a th p c a khng gian chng trnh t i bin c a 16K t chng trnh b t k, c nh ngha b i thanh ghi PSVPAG 8-bit (Program Space Visibility Page). Do cc l nh c th truy c p khng gian chng trnh nh khng gian d li u, nhng c m t gi i h n l n c n thm m t chu k l nh n a. Ch c 16 bt th p c a m i t l nh c th s d ng phng th c truy c p ny. - Truy c p tr c ti p khng tuy n tnh c a cc trang 32K t n m trong khng gian chng trnh cng c th s d ng cc thanh ghi lm vi c, thng qua b ng l nh c v ghi. B ng l nh c v ghi c th c s d ng truy c p c 24 bit c a m t t l nh. Kh i X AGU (kh i AGU c a b nh X) cng h tr vi c o bit a ch trn a ch ch k t qu nh m n gi n ho t i a d li u vo ho c ra chng thch h p cho thu t ton FFT c s 2. V i t t c cc l nh, nhn c a dsPIC30F c kh nng th c hi n vi c c b nh d li u ho c b nh chng trnh, c thanh ghi lm vi c, ghi vo thanh ghi lm vi c v c b nh chng trnh m i chu k l nh. Nh v y, l nh 3 ton h ng c h tr , cho php th c hi n php tnh C = A + B trong m t chu k l nh.

Sinh Vin : L Tr n Tri u Tu n

14

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 2.1. S

kh i DsPic30F4011

Sinh Vin : L Tr n Tri u Tu n

15

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 2.2. Cc thanh ghi c a kh i x l trung tm

Sinh Vin : L Tr n Tri u Tu n

16

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Cng c DSP c tch h p vo vi x l lm tng ngha c a m t CPU m nh v thu t ton. c i m c a n l th c hi n t c cao m t php nhn hai s 17-bit, m t kh i s h c v logic (ALU) 40-bit, hai thanh ch a c kh nng bo ho 40-bit v m t b d ch hai h ng 40-bit. D li u trong thanh ch a ho c b t k m t thanh ghi lm vi c no c th c d ch tri 15 bit hay d ch tri 16 bit ch trong m t chu k l nh. Cc l nh DSP ho t ng th ng nh t v i t t c cc l nh khc v c thi t k nh m thch h p v i vi c x l th i gian th c. L p MAC c a l nh c th ng th i n p hai ton h ng d li u t b nh trong khi ang nhn hai thanh ghi W. kch ho t ch n p ng th i c a ton h ng, khng gian d li u c chia nh cho cc l nh ny v tuy n i v i cc l nh khc. Vi c ny c th c hi n r rng v r t linh ho t b ng cch dnh m t vi thanh ghi lm vi c cho m i khng gian a ch cho l p MAC c a l nh. Nhn c a vi x l khng h tr ng ng a t ng l nh, nhng m t l nh n t ng s s d ng k thu t ti n n p, truy c p v gi i m t ng ph n l nh nh m m c tiu m t l nh ch th c hi n trong m t chu k. 2.3.2. Kh i t o a ch AGU a ch c l p l X AGU v Y AGU. c d li u 16-bit cho l p MAC c a l nh DSP. Cc kh i AGU trong a ch d li u:

Nhn c a vi x l dsPIC ch a hai kh i t o Kh i Y AGU h tr dsPIC h tr 3 ki u a ch tuy n tnh. a ch vng. a ch o bit.

Ch a ch tuy n tnh v ho c khng gian chng trnh. Ch d li u 2.3.2.1. Ch a ch l nh

a ch vng c th p d ng cho khng gian d li u o bit a ch p d ng cho cc a ch khng gian

Cc ch a ch cc l nh khc nhau.

c cung c p trong l p MAC c a cc l nh th c khc nhau i cht

Sinh Vin : L Tr n Tri u Tu n

17

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

B ng 2.1. Cc ch L nh thanh ghi t p

nh

a ch c b n

c h tr

T t c cc l nh thanh ghi u s d ng tr ng a ch 13-bit tr c ti p nh a ch d li u 8192 bytes u c a b nh d li u (g n khng gian d li u). T t c cc l nh thanh ghi t p u t n d ng thanh ghi lm vi c W0, thanh ghi lm vi c trong cc l nh ny.

L nh MCU Cc l nh MCU 3 ton h ng c d ng nh sau: Ton h ng 3 = Ton h ng 1 <hm> Ton h ng 2

Trong Ton h ng 1 lun l thanh ghi lm vi c (v d : ch a ch ch c th l thanh ghi tr c ti p). Ton h ng 2 c th l thanh ghi W, l y d li u t b nh d li u, ho c 5 bit thng th ng. K t qu c nh. L nh di chuy n v tch lu c t trong c th l thanh ghi W ho c m t a ch

L nh di chuy n v cc l p DSP tch lu c a l nh lm cho s m m d o c a a ch cao hn cc l nh khc. T t c cc l nh MCU, l nh di chuy n v tch lu u h tr ch a ch , v cng h tr ch thanh ghi gin ti p v thanh ghi a ch offset. Ch : i v i l nh MOV, ch a ch c ch r trong l nh c th khc nhau gi a ngu n v ch. Tuy nhin tr ng c a 4-bit offset c a thanh ghi Wb c chia s gi a ngu n v ch. Cc l nh MAC

Sinh Vin : L Tr n Tri u Tu n

18

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

C hai ton h ng ngu n c a cc l nh DSP (CLR, ED, EDAC, MAC, MPY.N, MOVSAC v MSC) c xem nh cc l nh MAC, t n d ng cc l nh c n gi n ho c a ch a ch nh m cho php ng i s d ng c th i u khi n con tr d li u thng qua cc b ng thanh ghi gin ti p. Hai thanh ghi ti n n p ton h ng ngu n ph i l m t trong cc thanh ghi sau: {W8, W9, W10, W11}. V i c d li u, W8 v W9 lun tng tc tr c ti p v i X AGU, W10 v W11 lun tng tc tr c ti p v i Y AGU. Do a ch hi u d ng c t o (tr c v sau khi hi u ch nh) ph i h p l v i a ch trong khng gian d li u X cho W8, W9 v trong khng gian d li u Y cho W10, W11. Cc l nh khc Bn c nh cc ch a ch bi n i, m t vi l nh s d ng cc h ng s c nh

d ng thay i. V d : l nh BRA (branch phn nhnh) s d ng d li u 16-bit c d u ch ra ch r nhnh tr c ti p, trong khi lnh DISI s d ng tr ng s 14-bit khng d u. Trong m t vi l nh nh ADD hay ACC, ngu n c a m t ton h ng ho c k t qu c a ra b i chnh m l nh c a n. Tuy nhin, m t vi l nh nh NOR, l i khng c ton h ng no. 2.3.2.2. Ch o bit a ch

a ch c o bit nh m lm n gi n ho d li u cho thu t ton FFT c s 2. N c h tr b i kh i AGU c a X ch cho vi c ghi d li u. Th c hi n o bt o bit a ch

a ch

c b t khi cc i u ki n sau c tho mn:

Cc bit BWM (l a ch n thanh ghi W) trong thanh ghi MODCON gi tr l n hn 15 (khng th truy c p ngn x p khi ang s d ng ch o bit a ch ) Bit BREN c Ch a ch t trong thanh ghi XBREV c s d ng l ch thanh ghi gin ti p

N u di b m c a cc bit c o l M = 2N bytes, N bit cu i cng c a b m d li u b t u c nh a ch b ng khng. Cc bit XB <t bit 14 n 0 c a thanh ghi XBREV> l g i l i m xoay (pivot point) th ng l h ng s . a ch bit c o, hay cn

Sinh Vin : L Tr n Tri u Tu n

19

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 2.3. M t v d v 2.3.3. T ch c b nh v b nh chng trnh 2.3.3.1. Khng gian Khng gian 4M t l nh. B n a ch chng trnh

o bit

a ch

a ch chng trnh c l n khng gian b nh chng

c a dsPic30F4011 c ch ra trong Hnh 2.4. B nh chng trnh c th c a ch ho b i m t gi tr 24-bit b i b m chng trnh (PC), ho c b ng l nh a ch hi u d ng (EA), ho c khng gian d li u EA khi khng gian chng trnh c s p x p v a ch ho. Ch r ng, a ch khng gian chng trnh c tng ln v i b c l 2 gi a cc t chng trnh t o ra s tng thch v i vi c a ch ho khng gian d li u. Truy c p khng gian chng trnh ng i s d ng b gi i h n trong d i 4M a ch c a t l nh (t 0x000000 t i 0x7FFFFE) v i t t c cc l nh truy c p, tr hai l nh TBLRD/TBLWT - s d ng bit 7 c a thanh ghi TBLPAG xc nh ng i s d ng ho c thi t l p c u hnh truy c p b nh .

Hnh 2.4. B n
Sinh Vin : L Tr n Tri u Tu n

khng gian b nh chng trnh

20

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

2.3.3.2. Truy xu t d li u t b nh chng trnh s d ng cc l nh b ng Ki n trc c a dsPIC cho php n p d li u r ng 24-bit t i b nh chng trnh, do cc l nh lun lun c x p hng tuy nhin ki n trc c a n c c i ti n so v i ki n trc my tnh Hadvard nn d li u cng c th c a ra trong khng gian chng trnh. C hai phng php truy c p khng gian chng trnh, l:(xem hnh 2.5) - Thng qua cc l nh c bi t v b ng ho c thng qua vi c nh a ch v s p x p l i 16K trang t khng gian chng trnh trong n a cao c a khng gian d li u. Cc l nh TBLRDL v TBLWTL cung c p phng php c v ghi tr c ti p t t ngha nh t (LS Word) t i m t a ch b t k trong khng gian chng trnh m khng c n thng qua khng gian d li u. Hai l nh TBLRDH v TBLWTH ch l phng th c m 8 bt cao c a t khng gian chng trnh c th c truy xu t nh d li u. -B m chng trnh (PC) c tng ln hai v i m i t chng trnh 24-bit. i u ny cho php cc a ch b nh chng trnh nh x tr c ti p t i a ch khng gian d li u. Do b nh chng trnh c th c xem nh hai khng gian t a ch r ng 16-bit. Cc l nh TBLRDL v TBLWTL truy c p khng gian ch a t d li u t ngha nh t (LS Data Word) v cc l nh TBLRDH, TBLWTH truy c p khng gian ch a Byte d li u nhi u ngha nh t (MS Data Byte). S trn ch ra cch EA c t o cho ho t ng b ng v truy c p khng gian d li u (PSV = 1). T i y P (t bit 23 t i bit 0) ch th t khng gian chng trnh, cn D (t bit 15 t i bit 0) ch th t khng gian d li u. 2.3.3.3. Truy xu t d li u t b nh chng trnh s d ng khng gian chng trnh 32 Kbytes cao c a khng gian d li u c th c b n ho trong b t k trang 16K t b nh chng trnh no. N cho php truy c p vo h ng s d li u c lu tr t khng gian d li u X m khng c n cc l nh c bi t (nh TBLRDL/H, TBLWTL/H). Truy xu t khng gian chng trnh thng qua khng gian d li u c th c hi n n u bt ngha th p nh t c a khng gian d li u EA c gian chng trnh c b t b ng cch x l CORCON. t v ch hi n th khng t bit PSV trong thanh ghi i u khi n nhn c a vi

Sinh Vin : L Tr n Tri u Tu n

21

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 2.5 Truy c p d li u t khng gian chng trnh Truy xu t d li u vng ny s thm vo m t chu k l nh do n p d li u vo hai b nh chng trnh l c n thi t. l nh c th c hi n,

Ch r ng ch ph n cao c a khng gian d li u c kh nng nh a ch thi lun l m t ph n c a khng gian d li u X. Do , khi m t thao tc DSP s d ng vi c b n ho khng gian chng trnh truy c p b nh thi khng gian d li u Y thng th ng s lu tr tr ng thi d li u cho thao tc DSP, cn khng gian d li u X th ng s lu gi h s c a d li u. Tuy nhin m i a ch khng gian d li u , t 0x8000 tr ln, b n ho tr c ti p vo a ch c a b nh chng trnh p ng (Hnh 2.6) ch c 16 bit th p c a t chng trnh 24 bit c s d ng lu d li u. 8 bit cao c l p trnh lo i b cc l nh khng h p l nh m gi nguyn s c m nh c a b vi x l.

Sinh Vin : L Tr n Tri u Tu n

22

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 2.6. nh x khng gian d li u vo khng gian chng trnh 2.3.4. Cc c ng vo ra I/O Port Cc c ng vo ra c a dspic40f4011 u c thi t k c Schmitt nh m c i ti n kh nng ch ng nhi u. T t c cc c ng vo ra ng c a cc c ng. u vo l m ch Trigger

u c ba thanh ghi k t h p v i nhau i u khi n tr c ti p ho t

- Thanh ghi d li u tr c ti p (TRISx) xc nh c ng l Input hay Output. N u bit d li u tr c ti p l 1, th c ng l Input v ng c l i. Cc c ng c nh ngha l Input sau khi Reset. - Thanh ghi c ng (PORT registers): d li u m t c ng I/O c truy xu t thng qua thanh ghi PORTx. c gi tr c a thanh ghi PORT c ng no s c c gi tr c a c ng . Ghi vo thanh ghi PORT c a c ng tng ng vi c xu t d li u ra c ng . - Thanh ghi LAT, k t h p v i m t c ng I/O s lo i b c cc v n c th xu t hi n khi c-thay i-ghi vo c ng . c gi tr thanh ghi LAT s tr v gi tr c gi u ra c a b ch t c ng , thay cho gi tr c ng I/O. Vi c ghi vo thanh ghi LATx cng t o ra hi u qu nh ghi vo thanh ghi PORTx. C u hnh tng t cho c ng: khi s d ng b ADC th c ng c c u hnh l l i vo tng t . i u ny s c ni k hn ph n miu t ADC.

Sinh Vin : L Tr n Tri u Tu n

23

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 2.7. Cc c ng I/O c a dsPic30F4011

Hnh 2.8. S

kh i c a m t c ng I/O dng chung v i ngo i vi khc

Sinh Vin : L Tr n Tri u Tu n

24

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

2.3.5. Ng t v c ch ng t Vi i u khi n dsPic30F4011 c t i 30 ngu n ng t v 4 b x l lo i tr (b y l i), b x l ny s cho php cc ng t theo m c u tin c s p t tr c. CPU c th c b ng vector ng t v truy n a ch c ch a trong vector ng t t i b m chng trnh. Vector ng t c truy n t bus d li u chng trnh vo trong b m chng trnh thng qua b h p knh 24-bit, l i vo c a b m chng trnh. B ng vector ng t (Interrupt Vector Table - IVT) v b ng vector ng t thay th (Alternate Interrupt Vector Table - AIVT) c t g n i m b t u b nh chng trnh (0x000004). IVT v AIVT c ch ra trong B ng 2.2. Cc thanh ghi khi n ng t v u tin ng t: i u
INT Vector Interrupt Source Number Number Highest Natural Order Priority 0 8 INT0 External Interrupt 0 1 9 IC1 Input Capture 1 2 10 OC1 Output Compare 1 3 11 T1 Timer 1 4 12 IC2 Input Capture 2 5 13 OC2 Output Compare 2 6 14 T2 Timer 2 7 15 T3 Timer 3 8 16 SPI1 9 17 U1RX UART1 Receiver 10 18 U1TX UART1 Transmitter 11 19 ADC ADC Convert Done 12 20 NVM NVM Write Complete 13 21 SI2C - I2C Slave Interrupt 14 22 MI2C I2C Master Interrupt 15 23 Input Change Interrupt 16 24 INT1 External Interrupt 1 17 25 IC7 Input Capture 7 18 26 IC8 Input Capture 8 19 27 OC3 Output Compare 3 20 28 OC4 Output Compare 4 21 29 T4 Timer4 22 30 T5 Timer5 23 31 INT2 External Interrupt 2 24 32 U2RX UART2 Receiver 25 33 U2TX UART2 Transmitter 26 34 Reserved 27 35 C1 Combined IRQ for CAN1 28 - 38 36 - 46 Reserved 39 47 PWM PWM Period Match 40 48 QEI QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA PWM Fault A 44 52 Reserved 45 - 53 53 - 61 Reserved Lowest Natural Order Priority

Cc thanh ghi 16-bit IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

T t c cc c ng t c lu trong 3 thanh ghi ny. Cc c c t tng ng b i c a ngo i vi ho c tn hi u bn ngoi v c th xo b ng ph n m m.

B ng 2.2. B ng vector ng t c a dsPIC30F3012

Sinh Vin : L Tr n Tri u Tu n

25

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Cc thanh ghi 16-bit: IEC0<15:0>, IEC1<15:0>, IEC2<15:0>: T t c cc bit i u cho

khi n cho php ng t u n m trong 3 thanh ghi ny. Cc bit ny c s d ng php ng t c l p ngo i vi v tn hi u ngoi i m c u tin ng t k t h p v i m i ng t c gi trong cc thanh ghi ny

Cc thanh ghi u tin ng t: IPC0<15:0> ... IPC10<7:0>: Ng i s d ng c th chuy n

- Nhm bit IPL<3:0>: M c u tin c a CPU hi n hnh c lu r rng trong cc bit ny. Bit IPL<3> n m trong thanh ghi CORCON, trong khi cc bit IPL<2:0> n m trong thanh ghi tr ng thi (SR) - Hai thanh ghi 16-bit INTCON1<15:0>, INTCON2<15:0>: Ch c nng i u khi n ng t ton c c c xu t pht t hai thanh ghi ny. INTCON1 ch a cc c i u khi n v tr ng thi c a b x l lo i tr . INTCON2 i u khi n tn hi u yu c u ng t v vi c b ng vector ng t thay th . Cc ngu n ng t c th c ng i s d ng s p x p m c u tin t 1 n 7 thng qua thanh ghi IPCx. M i ngu n ng t c k t h p v i m t vector ng t (b ng 2.2)

Hnh 2.9. Cc vector b y l i

Sinh Vin : L Tr n Tri u Tu n

26

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

2.3.6. Cc b

nh th i

Trong vi x l dsPIC40F4011 c t i nm b nh th i (Timer) 16-bit. Trong cc Timer c th ho t ng ring bi t, ring hai Timer 2, 3 v hai Timer 4, 5 c th k t h p v i nhau tr thnh m t Timer 32 bit. V c u trc cc Timer ny khc nhau v hai Timer 2 v 3 v hai Timer 4 v 5 c th k t h p cn Timer 1 th khng. Timer 1 c c u trc ki u A (Hnh 2.10), Timer 2,4 ki u B v Timer 3,5 ki u C. V ho t ng cc Timer c ho t ng g n gi ng nhau do ta s tm hi u v Timer 1, cc Timer cn l i l tng t . Timer 1 c th ho t ng v i ngu n t o dao ng t n s th p 32KHz, v ch khng ng b v i ngu n t o dao ng ngoi. c i m ring bi t c a Timer 1 l c th dng trong cc ng d ng th i gian th c. Ph n ti p theo s m t chi ti t cch thi t l p v s d ng Timer 1 v i ba ch Timer 16-bit: trong ch ny, timer s tng sau m i chu k l nh :

n khi gi tr c a

timer b ng gi tr c a thanh ghi chu k PR1 (Period Register) th s reset v 0 v ti p t c m. - Counter ng b 16-bit: trong ch ny, timer s tng m i s n ln c a c a xung nh p ngoi m c ng b v i pha c a cc xung nh p trong. Timer tng n gi tr n m trong thanh ghi PR1 th d ng v reset timer v 0 r i ti p t c m ln. - Counter khng ng b 16-bit: khi ho t ng trong ch ny, timer s tng d n sau m i s n ln c a xung nh p bn ngoi tc ng vo. Timer s tng d n n khi gi tr c a n b ng thanh ghi PR1 th b reset v 0 r i l i ti p t c m ln. H s chia t n c a b Xung nh p nh th i

u vo (Fosc/4 ho c xung nh p ngoi) a vo Timer 16-bit v c th

c chia t n s theo cc t l sau: 1:1, 1:8, 1:64, 1:256 c xc nh b i cc bit TCKPS<1:0> c a thanh ghi TxCON. H s chia t n ny (prescaler) c th b xo khi x y ra m t trong cc i u ki n sau: Ghi vo TMR Ghi vo thanh ghi TxCON (tr vi c ghi vo bit TxCON)

Reset thi t b , nh POR v BOR

Sinh Vin : L Tr n Tri u Tu n

27

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

DsPic30F4011 c 5 thanh ghi i u khi n Timer T1CON..T5CON. Cc thanh ghi ny c chia ra lm 2 ki u. T1CON thu c ki u A, T2CON v T4CON thu c ki u B, T3CON v T5CON thu c ki u C.

Hnh 2.10. S

kh i c a Timer 1

Hnh 2.11. S

kh i Timer 2

Sinh Vin : L Tr n Tri u Tu n

28

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 2.12. S

kh i Timer 3

Hnh 2.13. S

kh i Timer 2/3 - 32bit

Sinh Vin : L Tr n Tri u Tu n

29

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

(S

kh i Timer 4/5 32 bit v Timer 4,5 16 bit gi ng nh Timer 2/3 32 bit v Timer 2,3 16 bit) i tng t s ADC i tng t s 10-bit cho php

2.3.7. B chuy n

Vi i u khi n dsPic30F4011 cung c p b chuy n

bi n i tn hi u tng t u vo sang s di 10-bit. Module ny d a trn thanh ghi SAR (Successive Approximation Register thanh ghi x p x ) v cung c p t c l ym u t i a ln t i 100 ksps. ADC c a dsPic30F4011 c t i 10 knh tng t l i vo c k t h p c l y m u v gi m u. L i ra c a b l y v gi m u l l i vo c a b chuy n i t o ra k t qu bi n i. i n th tng t chu n c th l i n th ngu n cung c p (AVDD/AVSS) ho c m c i n th c a cc chn VREF+/VREF-. B bi n i ADC c a dsPIC bao g m 6 thanh ghi:

Ba thanh ghi i u khi n A/D: ADCON1, ADCON2, ADCON3 Ch c nng i u khi n ho t ng c a ADC. Thanh ghi l a ch n l i vo: ADCHS L a ch n knh vo bi n i. Thanh ghi c u hnh c ng ADPCFG C u hnh c ng tr thnh l i vo tng t ho c vo ra s . Thanh ghi l a ch n qut 2.3.7.1. B m k t qu bi n i A/D

Module ADC s d ng RAM lm b m lu k t qu bi n i A/D. C t t c 16 v tr trong RAM c s d ng lm vi c ny, l: ADCBUF0, ADCBUF1, ADCBUF2, ..., ADCBUFE, ADCBUFF. RAM ch c r ng 12-bit nhng d li u ch a trong n l i l m t trong b n d ng s 16-bit l: nguyn, nguyn c d u, phn s , v phn s c d u. 2.3.7.2. Cc b c th c hi n bi n i A/D

a) Thi t l p c u hnh cho module A/D - C u hnh cc chn l l i vo tng t , i n th chu n v vo ra s . - Ch n cc knh l i vo c n bi n i.

Sinh Vin : L Tr n Tri u Tu n

30

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Ch n xung nh p cho bi n

i. ng.

Cho php module ADC c th ho t

b) C u hnh cho ng t ADC n u c n - Xa c ng t ADIF L a ch n m c u tin ng t cho bi n ul ym u th i gian c n thi t hon thnh i i A/D c) B t d) i

e) K t thc l y m u, b t f) -

u bi n

i bi n i k t thc b i m t trong hai i u ki n sau: i ng t t ADC i bit DONE c set c k t qu t b m bi n i A/D v xa bit ADIF n u c n

Sinh Vin : L Tr n Tri u Tu n

31

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 2.14. S

kh i c b n c a ADC 10-bit

Sinh Vin : L Tr n Tri u Tu n

32

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Chng 3. Th c Nghi m
3.1. Ph n C ng Ph n c ng c em thi t k d a trn s kh i c a m t b khuy ch i lock in s (Digital Lock-In Amplifiers). Ph n c ng thi t k c nh ng kh i chnh sau y:(Hnh 3.0) - Kh i ngu n - Kh i cc b l c thng th p (lowpass filter, LP Sallen key filter) - Kh i bi n i DAC i tn hi u vo

- Kh i khuy ch - Kh i LCD

- Kh i x l s trung tm

Ngu n 5 V

Sensor Kh i X L Lowpass Filter Mn Hnh Hi n Th LCD S Trung Tm Khuy ch i dsPic30F4011 (DSP) DAC R/2R Salenkey Filter

Ngu n +12V, -12V

Hnh 3.1. S

Kh i Ph n C ng

Sinh Vin : L Tr n Tri u Tu n

33

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

3.1.1. Cc kh i ngu n Cc kh i ngu n c n thi t k cung c p ngu n cho ton b cc kh i thnh ph n c a b khuy ch i lock in. C th y ta c n c ngu n +5V c p cho kh i x l s trung tm (Vi i u khi n dsPic30F4011) v mn hnh hi n th LCD, ngu n +12V,-12V cung c p cho kh i b l c s v kh i khuy ch i tn hi u vo. S c a cc kh i ngu n ny c trnh by trn Hnh 3.2.

Hnh 3.2. Cc kh i ngu n

Sinh Vin : L Tr n Tri u Tu n

34

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

3.1.2. Kh i cc b l c thng th p Trong kha lu n ny, c n s d ng 2 b l c thng th p. M t b l c thng th p c b n v m t b l c thng th p Sallen Key Filter th a mn yu c u c t t n s t i 10kHz. S b l c thng th p Sellen Key c b n c trnh by trn hnh 3.3

Hnh 3.3. S S

b l c Sallen Key c b n

b l c Sallen Key dng trong kha lu n c trnh by trn hnh 3.4

Hnh 3.4. S d b l c Sallen Key c s d ng trong kha lu n th a mn t n s c t l 10kHz trong kha lu n ny em s d ng t C2 = 1000pF => C1 = 2C2 = 1000pF

Sinh Vin : L Tr n Tri u Tu n

35

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

=> R1 = R2 = 0.707 / (2 fo C2) = 0.707 / (2 10kHz 1000pF) = 11.2 K B l c thng th p cn l i c thi t k i analog.(xem hnh 3.5) lm trn tn hi u sau khi qua b khuy ch

Hnh 3.5. B l c thng th p low pass 3.1.3. Kh i bi n 3.1.3.1. Ho t i DAC ng c a DAC v tnh ch t c a n

Hnh 3.6. V d v b bi n

i DA 4 bt

M c ch c a b bi n i DA, nh nu, l bi n i tn hi u nh phn n bt thnh dng hay p tng ng. Hnh 3.6 l m t v d v m t b bi n i DA 4 bt n gi n. V nguyn t c b chuy n i s -tng t ti p nh n m t m s n bt song song ho c n i ti p l i vo v bi n i ra dng i n ho c i n p tng ng l i ra. Dng i n hay i n p l i ra l hm bi n thin ph h p theo m s l i vo.

Sinh Vin : L Tr n Tri u Tu n

36

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

M t b DAC hon ch nh bao g m ba ph n t c b n: i n p tham chi u n DAC c s Khu ch S i thu t ton nh bn ngoi (Vref)

kh i c a b DAC c trnh by trn Hnh 3.7

Hnh 3.7. S Nh v y i n p theo cng th c sau: u ra c a b bi n

kh i DAC i V0 s ph thu c vo m nh phn u vo

V0 = Vref (B 0 2 0 + B 1 2 1 + ... + B n 2 n )
Trong B0 l bt th p nh t v Bn l bt cao nh t c a m nh phn i n p tham chi u. DAC c s u vo v cc i n p trch ra ng v i m s u vo, Vref l

c u t o b ng nh ng chuy n m ch tng t c i u khi n b i m s i n tr chnh xc. Cc chuy n m ch tng t i u ch nh dng i n hay t i n p tham chi u v t o nn dng i n hay i n p u ra tng u vo. i thu t ton dng y chuy n i dng thnh p ng th i c

M ch khu ch ch c nng t ng m.

Sinh Vin : L Tr n Tri u Tu n

37

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

B bi n

i DAC c

c i m l

i l ng ra tng t khng lin t c,

r ir cc a

u ra ph thu c vo s bt c a b bi n i, nh ng DAC c s bt n c i n p ra cng l n v kho ng cch gi a cc n c cng nh . 3.1.3.2. Cc tham s c a b chuy n i DA

u vo l n th t ng s

- phn gi i (Solution): Lin quan n s bt c a m t DAC. N u s bt l n th s tr ng thi c a tn hi u nh phn l 2n ngha l s c 2n m c i n th (ho c dng i n) khc nhau, do c phn gi i l 1/2n. phn gi i cng b th i n th (ho c dng i n u ra) cng c d ng lin t c, cng g n v i th c t v ng c l i. - chnh xc (Accuracy): C th nh gi ch t l ng c a m t DAC b ng sai s

c a n. i l ng bi u di n sai s l l ch t i a gi a i l ng ra v m t ng th ng n i i m 0 v i i m FS (Full Scale) trn c tuy n chuy n i DA. - tuy n tnh (Linearity): tuy n tnh c a DAC cho bi t l ch i n p so v i m t ng th ng i qua nh ng i m nt c a c tuy n chuy n i. l c tnh th ng g p nh t v i DAC. ng cong c tuy n l n i u n u s thay i l ch trn l khng i d u. c m t DAC n i u, l ch ny ph i l n hn 0 cho m i n c thang. Ngoi ra m c tuy n tnh c a DAC ph i nh hn ho c b ng 1/2 LSB n tr nn n i u. Nh v y 1/2 LSB l c trng v gi i h n n i u c a m t DAC. - Phi tuy n vi sai: l i l ng cho bi t l ch gi a gi tr th c t v l t ng cho

m t n c i n p ra ng v i m i thay i c a m s vo. i l ng ny cho bi t v nh n c a ng cong c tuy n i v i DAC. - Th i gian thi t l p: i v i m t DAC l th i gian c n thi t n i n p ra t t i gi

tr t i h n sai s xung quanh gi tr di n b ng gi tr % FS.

nh. Gi i h n ny th ng l = LSB ho c bi u

Th i gian thi t l p tr c h t ph thu c vo ki u chuy n m ch, ki u i n tr v ki u khu ch i dng xy d ng b DAC. Thng th ng n c nh ngha b ng th i gian t khi i n p b t u thay i cho t i khi t t i vng gi i h n sai s cho tr c. N khng bao g m th i gian tr tnh t khi c s thay i m s u vo cho t i khi i n p ra b t u p ng.

Sinh Vin : L Tr n Tri u Tu n

38

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

3.1.3.3. Cc m ch DAC i n hnh Cc DAC c th Chuy n Chuy n c xy d ng theo m t trong nh ng ki u m ch sau: i DA theo ki u i n tr tr ng l ng i DA theo ki u m ch R-2R i DA theo ki u i n tr tr ng l ng (Weighted resistor DAC)

3.1.3.3.1. B chuy n

M ch g m m t ngu n i n p chu n Uch, cc chuy n m ch, cc i n tr c gi tr l n l t l R, R/2, R/4, ... , R/2n-1 v cc m ch khu ch i thu t ton.(Xem hnh 3.7) V i m ch nh trn, khi m t kho i n no c n i v i ngu n i n th chu n th s cung c p cho b khu ch i thu t ton (KTT) dng i n. Dng i n ny c l p v i cc kho cn l i. Nh v y c th th y ngay r ng bin

i n p ra ph thu c vo cc v tr c ng hay m kho ngha l c n i v i i n p chu n Uch hay ni cch khc ph thu c vo gi tr cc bt tng ng trong tn hi u s a vo m ch chuy n i.

Hnh 3.8. DAC theo phng php i n tr tr ng l ng M t cch t ng qut, v i m t DAC c n bt th tn hi u ra c tnh theo cng th c: Ura = U ch .

R1 n-1 n-1 n-2 n-2 (2 .B + 2 .B + ... + 21.B1 + 20.B0) R

Sinh Vin : L Tr n Tri u Tu n

39

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Trong B0 < Bn-1 c gi tr "0" ho c "1". M ch c u i m l n gi n, nhng nh c i m l chnh xc v tnh n nh c a k t qu ph thu c nhi u vo tr s tuy t i c a cc i n tr v s n nh c a chng trong cc mi tr ng khc nhau. Ngoi ra cn ph thu c vo tnh n nh v chnh xc c a ngu n i n p chu n. 3.1.3.3.2. B chuy n i DA theo ki u thang i n tr R-2R (R-2R ladder)

Hnh 3.9. DAC theo phng php m ch R-2R DAC v i thang i n tr R-2R kh c ph c c m t s nh c i m c a DAC i n tr tr ng l ng. M ch ch g m hai i n tr R v 2R m c theo hnh thang v i nhi u kho i n (m i kho i n cho m t bt) v m t ngu n i n p chu n Uch.(Xem Hnh 3.9) i l ng c n tm l dng Ith ch y vo m ch KTT khi c m t s kho i n c n i v i Uch. Theo m ch i n ta c: Ura = -Ith.Rf Xt t i chuy n m ch tng ng v i bt th i, nt tng ng trn m ch hnh thang l 2 . S d ng nh l Thevenin, khi ng chuy n m ch vo Uch th i n th tng ng Thevenin t i nt 2i s l Uch/2 v ngu n tng c n i tr l R, nh v y t i nt 2i+1 (ti n v pha m ch KTT) ta c ngu n tng ng Thevenin c tr s l Uch/4 v n i tr l R.
i

Sinh Vin : L Tr n Tri u Tu n

40

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

i n th Thevenin t i m i nt b ng m t n a tr s t i nt k c n bn tri n, v t i nt 2n-1 do c tnh c a b KTT i n th c coi b ng 0V. M t cch t ng qut, ta c cng th c tr hnh thang R-2R nh sau: tnh i n p ra c a m t DAC n bt v i i n

T nh ng k t qu trn suy ra r ng khi di chuy n v pha m ch KTT th tr s

U ra = U ch

Rt (2 n1 B n1 + 2 n 2 B n 2 + ... + 21 B 1 + 2 0 B 0 ) n 2 .R

Trong B0 < Bn-1 c gi tr "0" ho c "1". Cc DAC theo thang i n tr ph i dng s i n tr kh l n, v d n u m t DAC n bt th c n dng 2(n-1) i n tr trong khi phng php i n tr tr ng l ng ch ph i dng n thi. Nhng b l i chnh xc v tnh n nh c a tn hi u ra c m b o t t hn. 3.1.3.4. Ghp n i ADC v i vi i u khi n V nguyn t c m t b DAC c th ghp n i tng thch v i h u h t cc b V K. i v i cc b DAC 8 bt, cng vi c th m ch cn r t n gi n khi ghp n i v i cc V K, l do l cc V K u c BUS d li u l b i c a 8. i v i cc b DAC 12 hay 16 bt ta ph i s d ng cc m trung gian c s bt tng ng sau ti n hnh trao i s li u nhi u l n. 3.1.3.5. B bi n x l. S c a b bi n i c trnh by trn Hnh 3.10 i DAC s d ng trong kha lu n i DAC m ng R/2R 4 bt ghp n i v i vi

Trong kha lu n, em s d ng ki u bi n

Hnh 3.10. B bi n

i DAC 4 bit

Sinh Vin : L Tr n Tri u Tu n

41

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

4 bt c ghp n i v i 4

u ra RE0...RE3 c a vi i u khi n dsPic30F4011. t o sng sin,

i u khi n b bi n i DAC 4 bit ny em vi t chng trnh cho V K theo b ng c thi t l p nh sau:

sinTable[] = {5,6,7,8,9,9,10,10,10,10,10,9,9,8,7,6,5,4,3,2,1,1,0,0,0,0,0,1,1,2,3,4} Sau khi c chng trnh ha trn V K tn hi u ra c d ng (xem hnh 3.11)

Hnh 3.11. Tn hi u ra b bi n

i DAC 4 bt

Tn hi u ra s khng m n nh mong mu n, mu n c m n hn ta c n cho tn hi u qua m t b l c thng th p (c th y l b l c salenkey), Sau khi qua b l c salenkey tn hi u ra s c d ng nh hnh 3.12

Hnh 3.12. Tn hi u ra b bi n

i DAC 4 bt khi qua b l c

Sinh Vin : L Tr n Tri u Tu n

42

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

3.1.4. Kh i khuy ch

i tn hi u vo i thu t ton v tnh ch t c a n

3.1.4.1. Tm hi u v m t s m ch khuy ch Khu ch

i thu t ton l m t trong s nh ng linh ki n i n t th ng g p nh t trong

k thu t tng t , v th trong k thu t o l ng v i u khi n cng nghi p, khu ch i thu t ton cng c m t trong r t nhi u thi t b v h th ng. Kh nng s d ng c a cc b khu ch i thu t ton l r t v n nng, chng c p d ng trong nhi u lnh v c nh cc b khu ch i m t chi u, cc b khu ch i xoay chi u, b l c tch c c, b dao ng, b bi n i tr khng, b vi phn, b tch phn... lm n i b t tnh ch t c a m t b khu ch m t b khu ch i thu t ton l t ng: i khi khng c ph n h i m l n v cng. i thu t ton, hy xt tnh nng c a

H s khu ch

i n tr l i vo l n v cng. r ng d i thng l n v cng. H s nn ng pha CMRR l n v cng.

i n tr l i ra b ng khng Th i gian p ng b ng khng. Trn th c t , khng c b khu ch khu ch i thu t ton l t ng m ch t n t i nh ng

i thu t ton th c c tnh ch t g n v i nh ng tiu chu n nu.

Cc tham s v cc m ch ng d ng c a b khu ch i thu t ton r t nhi u, khng th nu h t trong b n kha lu n ny m y d i y ch nu ln nh ng tham s c b n, cch tnh ton v cc m ch c p d ng trong h th ng i u khi n. 3.1.4.1.1. Cc tham s c b n c a m ch khu ch S nguyn t c c a b i thu t ton

K TT c trnh by trn hnh 3.13

Sinh Vin : L Tr n Tri u Tu n

43

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 3.13. B khu ch Trn hnh 3.13 ta c cc k hi u sau: Ud i n p vo hi u

i thu t ton.

UP , IP i n p vo v dng i n vo c a thu n. UN , IN i n p vo v dng i n vo c a Ur , Ir i n p ra v dng i n ra. B khu ch i thu t ton khu ch K0 > 0. Do i n p ra: i hi u i n p Ud = UP - UN v i h s khu ch i o.

Ur = K0. Ud = K0(UP - UN) (*) i) H s khu ch i hi u K0 i hi u Ko c xc nh theo bi u th c sau

Khi khng t i h s khuy ch

K0 =

Ur Ur = Ud U p Un

j) H s khu ch

ng pha KCM o c a b khu ch i thu t ton cc i n p b ng

N u t vo c a thu n v c a nhau, ngha l:

Sinh Vin : L Tr n Tri u Tu n

44

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

UP = UN = UCM = 0 th Ud = 0. G i UCM l i n p vo ng pha. Theo bi u th c (*) ta c Ur=0. Tuy nhin, th c t khng ph i nh v y, gi a i n p ra v i n p vo ng pha c quan h t l l h s khu ch i ng pha KCM :

K CM =

U r U CM
ng pha.

KCM ni chung ph thu c vo m c i n p vo k) H s nn ng pha CMRR

Dng nh gi kh nng lm vi c c a b khu ch t ng (KCM=0)

i th c so v i b khu ch

i l

CMRR =

K0 K CM

l) Dng vo tnh L tr trung bnh c a dng vo c a thu n v dng vo c a o:

It =

IP + IN v i UP = UN = 0 2
hai c a c a b khu ch i thu t

Dng vo l ch khng l hi u cc dng vo tnh ton

I0 = IP - IN v i U P = U N = 0 Thng th ng I0 = 0,1IP. Tr s c a dng vo l ch khng thay Hi n t ng ny g i l hi n t ng tri dng l ch khng. 3.1.4.1.2. Cc s c b n c a b khu ch i thu t ton i theo nhi t .

Sinh Vin : L Tr n Tri u Tu n

45

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

i) S

khu ch

i khng

Hnh 3.14. S H s khu ch i c a m ch l

khu ch

i khng

K =

1 1 R 2 1 1 + K CMRR 0 R1 + R2

j) M ch

m c bi t c a m ch khu ch i khng o

y l tr ng h p

Hnh 3.15. S M ch c h s khu ch k) M ch khu ch i o i i b ng 1 v dng

m ch

ph i h p tr khng.

M ch khuy ch

o c trnh by trn hnh 3.16.

Sinh Vin : L Tr n Tri u Tu n

46

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 3.16. S H s khu ch i c a m ch:

m ch khu ch

K=

R2 R1

l) S

bi n

i dng i n - i n p: c trnh by trn hnh 3.17

Hnh 3.17. S

bi n

i dng i n - i n p

i n p ra c tnh theo bi u th c: UR = - R.IV 3.1.4.2. B khuy ch i s d ng trong kha lu n (AD620) i xy d ng c s d ng vi m ch AD620, s

Trong kha lu n ny b khuy ch c th c trnh by nh hnh 3.18

Sinh Vin : L Tr n Tri u Tu n

47

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 3.18. B khuy ch

i thu t ton s d ng IC AD620

AD620 l lo i IC khuy ch

i thu t ton kh t t, n c kh nng khuy ch

i tn

hi u t i 1000 l n, ty thu c vo i n tr ph i ghp. M t thng c a b khuy ch khuy ch i l 120KHz i c tnh theo cng th c:

n l i vo 9nV/ Hz , bng

G=

49,4k 49,4k 1 RG = RG G 1

Trong kha lu n RG chnh l R7.

3.1.5. Kh i LCD Trong kha lu n ny em s d ng LCD hi n th 16 k t 2 dng. Giao ti p 8 bit. LCD c tc d ng hi n th k t qu cu i cng c a bi ton. Cc chn i u khi n c a LCD c k t n i v i cc chn I/O c a vi i u khi n dsPic30F4011. LCD c ho t ng thng qua s i u khi n c a vi i u khi n (V K) dsPic30F4011. Hnh 3.19 trnh by s m ch LCD s d ng trong kha lu n.

Sinh Vin : L Tr n Tri u Tu n

48

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 3.19. LCD 16 k t 2 dng 3.1.6. Kh i x l trung tm Kh i x l trung tm trong kha lu n s d ng vi i u khi n DsPic30F4011. Kh i x l trung tm c nhi m v bi n i tn hi u vo thnh tn hi u s sau n s dng b dsp x l tn hi u cho ta k t qu cu i cng a ra LCD(g m c th c hi n cc php nhn v s d ng b l c s FIR ).. Th t th v trong V K DsPic30F4011 c tch h p b chuy n i AD nh trnh by ph n 2.3.7 trong chng 2. Cng vi c c a ng i s d ng l chng trnh ha cho V K th c hi n vi c chuy n i AD. B x l s dsp c tch h p s n trong V K DsPic30F4011 lm cho vi c thi t k cng n gi n hn, v i nh ng hm th vi n c s n do Microchip cung c p. 3.2. Ph n M m Trong kha lu n ny em s d ng ph n m m MPLab c a cng ty Microchip Technology th c hi n vi t chng trnh cho kh i x l trung tm (c th y l vi i u khi n dsPic30F4011). V em dng ngn ng C (C30) vi t chng trnh. Trong chng trnh c s d ng th vi n chu n c a Microchip cung c p (nh p30fxxx.h, p30f4011.h, dsp.h, ...). S kh i chng trnh ngu n c trnh by trn hnh 3.20.

Sinh Vin : L Tr n Tri u Tu n

49

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Modul chng trnh :

Kh i t o LCD

Kh i T o Timer

Kh i T o ADC

Kh i T o Reference signal

ref_signal x input_signal = I ref_signal_90 x input_signal=Q FIR Filter I,Q Final MAIN

Magnitude = I 2 + Q 2

Phase = tan 1 (Q / I )

Display LCD

Hnh 3.20. S

kh i chng trnh

Sinh Vin : L Tr n Tri u Tu n

50

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

3.3. Cc k t qu th c nghi m: 3.3.1. M ch khuy ch l trnh by chi ti t i lock-in ch t o v tn hi u vo ra lock in: m ch nguyn

M ch i n c thi t k trn ph n m m portel (xem hnh 3.21), s ph n ph l c

Hnh 3.21. M ch khuy ch

i lock in

Sinh Vin : L Tr n Tri u Tu n

51

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Tn hi u reference thu c sau khi s d ng b chuy n R/2R c bi u di n cc hnh 3.22 v 3.23. Tn hi u reference khi cha qua b l c sallen-key

i DA 4bit theo ki u m ng

Hnh 3.22. Tn hi u reference khi cha qua b l c sallen-key Tn hi u reference khi qua b l c sallen-key

Hnh 3.23. Tn hi u reference khi qua b l c sallen-key Tn hi u refrence ny s cung c p cho c m bi n c n kh o st. T n s c a tn hi u reference ny c th thay i c b ng cch l p trnh cho vi i u khi n.

Sinh Vin : L Tr n Tri u Tu n

52

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Tch c a tn hi u vo v tn hi u reference c trnh by trn cc hnh 3.24 v 3.25.

Hnh 3.24. Tch hai tn hi u cng pha v l ch trung bnh DC c a tn hi u thu c khi qua b l c thng th p S m ph ng trn hnh 3.24(s d ng ph n m m Micro-Cap Evaluation) cho ta th y m t php nhn gi a hai tn hi u cng pha (tn hi u vo v tn hi u tham chi u(reference)). Php nhn ny cho k t q a l m t tn hi u c t n s b ng hai l n t n s reference v c m c trung bnh trn m c 0(dng). Khi tn hi u ny qua b l c thng th p chng ta s thu c 1 m c DC t l v i tn hi u vo.

Sinh Vin : L Tr n Tri u Tu n

53

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 3.25. Tch hai tn hi u l ch pha 900 v

l ch trung bnh DC c a tn hi u thu c khi qua b l c thng th p

Hnh 3.25. cho th y tch gi a hai tn hi u (tn hi u vo v tn hi u tham chi u (reference)) khi chng khc pha nhau 900. V i php nhn ta thu c m t tn hi u c t n s b ng hai l n t n s reference nhng m c trung bnh l b ng 0. V y khi tn hi u ny qua b l c thng th p chng ta s thu c 1 m c DC b ng 0.

Sinh Vin : L Tr n Tri u Tu n

54

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh 3.26 ch ra k t qu php nhn c a tn hi u reference v tn hi u vo trong th c t khi tn hi u vo c pha t p n nhi u.

a)

b)

a) Tn hi u

Hnh 3.26. u vo v tn hi u tham chi u b)Tch c a chng i lock-in v i c m bi n p su t MPX2300D:

3.3.2.Th nghi m b khuy ch

nh gi v kh nng o c c a b khuy ch i lock-in xy d ng em th c hi n thi t k m t h o cho sensor p su t MPX2300D. 3.3.2.1. C m bi n p su t MPX2300D: - C m bi n p su t MPX2300D l m t s n ph m thng m i c a cng ty Motorola. - MPX2300D ch u ng c p l c t 0mmHg n 300mmHg v v i m i p l c1mmHg MPX2300D cho ta m t i n th ra 1uV (1uV/mmHg). - S chn c m bi n MPX2300D (xem b ng 3.1) cng v i hnh dng bn ngoi S 1 Vs chn c a c m bi n MPX2300D 2 S+ B ng 3.1. S 3 S4 GND

chn c m bi n MPX2300D

Sinh Vin : L Tr n Tri u Tu n

55

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Hnh dng bn ngoi v bn trong c m bi n c bi u di n trn hnh 3.27a v 3.27b

a)

b)

Hnh 3.27. a)Hnh dng bn ngoi MPX2300D b)Hnh dng bn trong MPX2300D 3.3.2.2. K t qu th nghi m: S h o th nghi m lock-in s s d ng c m bi n p su t c trnh by nh hnh 3.28.
Sensor MPX2300D Reference signal B Khuy ch i Lock-In

Signal Input

Tc d ng p su t

K t q a (hi n th trn LCD)

Hnh 3.28. S Hnh 3.29. ch ra cch m c cho h

u vo b khuy ch i lock-in

h o

o c m bi n MPX2300

Lock-in Amlifier

Hnh 3.29. Cch m c h

o th nghi m

Sinh Vin : L Tr n Tri u Tu n

56

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

o th c t

c trnh by trn hnh 3.30

Hnh 3.30. H

o th c t th nghi m

K t q a o th c a b lock-in s dng c m bi n p su t MPX2300D c trnh by trn b ng 3.2

p su t vo 10mmHg 15mmHg 20mmHg 25mmHg 30mmHg 40mmHg 50mmHg B ng 3.2. K t qu

K t qu 9,8uV 14,6uV 21,3uV 24,3uV 32,1uV 40,3uV 53,8uV o

Sinh Vin : L Tr n Tri u Tu n

57

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

K t q a o c bi u di n trn cc hnh 3.31 v 3.32 V(uV)

t(ms) Hnh 3.31. M i quan h gi a tn hi u ra theo th i gian

Hnh 3.32. M i quan h gi a p su t a vo v tn hi u ra

Sinh Vin : L Tr n Tri u Tu n

58

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

K t Lu n
K t qu thu c sau khi kha lu n c th c hi n: Tm hi u v c u t o v nguyn t c ho t ng c a b khuy ch i lock-in

N m v ng c u trc v l p trnh t t cho vi x l dsPic30F4011. Bi t cch s d ng Matlab thi t k m t b l c.

S dng thnh th o ph n m m v m ch in protel v orcad Hi u r v nh ng phng php bi n th c hi n m t kha lu n. Ch t o m t b khuy ch i lock-in v th nghi m v i m t sensor p su t. i ADC v DAC.

Xy d ng c cho b n thn cch lm vi c khoa h c, cch t duy c h th ng khi

nh gi k t qu thu c v h ng pht tri n c a kha lu n: C th s d ng b khuy ch lo i sensor khc nhau. B khuy ch i lock-in ang cn sai s v n nh v n cha cao. i lock-in s ch t o cho nhi u th nghi m v i nhi u

M ch v n cha c g n gng V th i gian th c hi n ti l kh ng n nn h nh gi cha th t khch quan. o cha c th nghi m nhi u, do o qua i lock-

H ng pht tri n ti p c a ti l rt g n m ch i n, tng chnh xc cho h c th thng m i ha h o.(C th s d ng h o c nhn l b khuy ch in cho nh ng c m bi n y sinh h c Bio Sensor).

Sinh Vin : L Tr n Tri u Tu n

59

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Ph L c
M ngu n chng trnh: //---Main--#include <p30f4011.h> #include <stdio.h> #include "common.h" #include "dsp.h" #include "lcd8bit.h" #include "delay.h" #include "string.h" _FOSC(CSW_FSCM_OFF & XT_PLL16); _FWDT(WDT_OFF); _FBORPOR(PBOR_OFF & MCLR_EN); _FGS(CODE_PROT_OFF); extern FIRStruct lowpassexample_psvFilter; /*Contains filter structures for FIR-LPF*/ extern FIRStruct fir_oneFilter; extern FIRStruct fir_baFilter; extern FIRStruct fir_cuoiFilter; fractional i_Ptr_sig[NUMSAMP]; fractional input_I_signal[NUMSAMP]; fractional input_Q_signal[NUMSAMP]; fractional output_I_signal[NUMSAMP]; fractional output_Q_signal[NUMSAMP]; fractional* i_Ptr; unsigned int ref_input_s90; unsigned int ref_input; unsigned int doFilterFlag; int main(void) { float nhan1,nhan2,kq1,kq2,adc;

Sinh Vin : L Tr n Tri u Tu n

60

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

float fI,fQ; float mag,phi; char sBuff[40]; TRISE = 0xFFF0; FIRDelayInit(&lowpassexample_psvFilter); FIRDelayInit(&fir_oneFilter); FIRDelayInit(&fir_baFilter); // Uart_Init(); Init_Timers(); Init_ADC(); TMR1 = 0; TMR2 = 0; TMR3 = 0; T1CONbits.TON = 1; T2CONbits.TON = 1; T3CONbits.TON = 1; while(!doFilterFlag); while (1) { if (doFilterFlag) { i_Ptr =& i_Ptr_sig[0]; adc = Fract2Float(i_Ptr_sig[0]); nhan1=Fract2Float(i_Ptr_sig[0])*ref_input; nhan2=Fract2Float(i_Ptr_sig[0])*ref_input_s90; input_I_signal[0] = Float2Fract(nhan1); input_Q_signal[0] = Float2Fract(nhan2); FIR(NUMSAMP,&output_I_signal[0],&input_I_signal[0],&fir_oneFilter); FIRDecimate(NUMSAMP,&output_I_signal[10],&input_I_signal[10],&fir_oneFilter,10); FIR(NUMSAMP,&output_Q_signal[0],&input_Q_signal[0],&fir_oneFilter);

Sinh Vin : L Tr n Tri u Tu n

61

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

FIRDecimate(NUMSAMP,&output_Q_signal[10],&input_Q_signal[10],&fir_oneFilter,1 0); FIR(NUMSAMP,&output_I_signal[0],&input_I_signal[0],&lowpassexample_psvFilter); FIRDecimate(NUMSAMP,&output_I_signal[8],&input_I_signal[8],&lowpassexample_p svFilter,8); FIR(NUMSAMP,&output_Q_signal[0],&input_Q_signal[0],&lowpassexample_psvFilter ); FIRDecimate(NUMSAMP,&output_Q_signal[8],&input_Q_signal[8],&lowpassexample_ psvFilter,8); FIRDecimate(NUMSAMP,&output_I_signal[0],&input_I_signal[0],&fir_baFilter,2); FIRDecimate(NUMSAMP,&output_Q_signal[0],&input_Q_signal[0],&fir_baFilter,2); FIR(NUMSAMP,&output_I_signal[0],&input_I_signal[0],&fir_cuoiFilter); FIR(NUMSAMP,&output_Q_signal[0],&input_Q_signal[0],&fir_cuoiFilter); fI = Fract2Float(output_I_signal[0]); fQ = Fract2Float(output_Q_signal[0]); .................................... Init_LCD(); // // lcd_cmd(lcd_homeL1); print_lcd(0x80,"TIN HIEU DO DUOC"); sprintf(sBuff," PHI = %8.4f ",phi); puts_lcd(sBuff,strlen(sBuff)); lcd_cmd(lcd_homeL2); sprintf(sBuff," MAG = %8.5f ",mag); puts_lcd(sBuff,strlen(sBuff)); // RS232XMT(sBuff); doFilterFlag = 0; } } return 0;

Sinh Vin : L Tr n Tri u Tu n

62

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

} //---Isr_Timers--#include <p30f4011.h> #include "common.h" #include "dsp.h" volatile unsigned char _sinTableIndex; extern unsigned int ref_input_s90; extern unsigned int ref_input; static unsigned char sinTable[] = {5,6,7,8,9,9,10,10,10,10,10,9,9,8,7,6,5,4,3,2,1,1,0,0 ,0,0,0,1,1,2,3,4}; static unsigned char sinTable_s90[] = {10,10,10,9,9,8,7,6,5,4,3,2,1,1,0,0,0,0,0,1,1,2,3 ,4,5,6,7,8,9,9,10,10}; void __attribute__((__interrupt__,no_auto_psv)) _T2Interrupt( void ) { _sinTableIndex++; _sinTableIndex &= 0b00011111; LATE = (sinTable[_sinTableIndex]); ref_input = (sinTable[_sinTableIndex]); ref_input_s90 = (sinTable_s90[_sinTableIndex]); IFS0bits.T2IF = 0; // Xoa co ngat } //--lcd-#include "p30f4011.h" #include "delay.h" #include "lcd8bit.h" void print_LCD(char a,char *s); void Init_LCD( void ); void lcd_cmd( char cmd ); void lcd_data( char data ) ; void puts_lcd( unsigned char *data, unsigned char count );

Sinh Vin : L Tr n Tri u Tu n

63

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

// cai dat lcd void Init_LCD( void ) { TRISB &= 0xFF00; RW_TRIS = 0; RS_TRIS = 0; E_TRIS = 0; LATB &= 0xFF00; RW = 0; RS = 0; E = 0; lcd_cmd( lcd_8bit ); lcd_cmd( lcd_normal ); lcd_cmd( lcd_on_crsr ); Delay_ms(1); } //Chuong trinh con xuat lenh o che do 8 bit void lcd_cmd( char cmd ) { DATA &= 0xFF00; DATA |= cmd; RW = 0; RS = 0; E = 1; Nop(); Nop(); Nop(); E = 0; RS = 0; Delay_ms(10); // E = hight // chuan bi RB0 - RB7 // gui lenh toi lcd // RW = low // RW = low // RS = low // E = low // che do giao tiep 8 bit // che do nhap du lieu binh thuong // bat mam hinh va con tro // cai dat 8 bit (RB0...RB7) la out con lai la in // cai dat RW la out // cai dat RS la out // cai dat E la out

Sinh Vin : L Tr n Tri u Tu n

64

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

} //Chuong trinh con xuat du lieu o che do 8 bit void lcd_data( char data ) { RW = 0; RS = 1; DATA |= data; E = 1; Nop(); Nop(); Nop(); E = 0; RS = 0; } void print_lcd(char a,char *s) // ham in ky tu tren LCD, in ky tu truc tiep { lcd_cmd(a); while(*s != 0) lcd_data(*s++); } void puts_lcd( unsigned char *data, unsigned char count ) { while ( count ) { lcd_data( *data++ ); count--; } } // // // // chuan bi RE0 - RE7 // gui du lieu toi lcd DATA &= 0xFF00; //

Delay_ms(10); // 200uS delay

Sinh Vin : L Tr n Tri u Tu n

65

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

M ch Nguyn L

Sinh Vin : L Tr n Tri u Tu n

66

H Cng Ngh - HQG H N i

Kha Lu n T t Nghi p

Ti Li u Tham Kh o
[1] Chip pak high volume presure sensor for disposable, backside pressure applications MPX2300D http://www.datasheetcatalog.com [2] [3] [4] [5] [6] [7] [8] [9] Bentham Lockin amplifers http://www.bentham.co.uk dsPIC Language Tool Libraries http://www.microchip.com dsPIC30F Family Reference Manual http://www.microchip.com dsPIC30Fs Programmer Reference Manual http://www.microchip.com dsPic30F4011/4012 http://alldatasheet.com FilterPro MFB and Sallen Key Low-Pass Filter Design Program John Bishop, Implementing Digital Lock-In Amplifiers Using the dsPIC DSC

Bruce Trump, R. Mark Stitt. http://www.focus.ti.com http://microchip.com Jerry Seams R/2R LADDER NETWORKS http://www.irctt.com

[10] Low Cost, Low Power Instrumentation Amplifier http://www.analog.com [11] Microchip Inc website http://www.microchip.com [12] Sallen-Key Low-Pass Filter http://www.ecircuitcenter.com [13] The Analog Lock-in Amplifier http://www.signalrecovery.com [14] The Digital Lock-in Amplifier http://www.signalrecovery.com [15] What is a Lock-in Amplifier? http://www.signalrecovery.com [16] Wide Bandwidth Dual JFET Input Operational Amplifier www.national.com [17] www.docu-track.com [18] Tutorial 04.01, Tutorial 05.01, Tutorial 06.01 http://www.picvietnam.com

Sinh Vin : L Tr n Tri u Tu n