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XC9572XL High Performance CPLD

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DS057 (v2.0) April 3, 2007

Product Specification cations and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for overview.

Features
5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins) - 64-pin VQFP (52 user I/O pins) - 100-pin TQFP (72 user I/O pins) - Pb-free available for all packages Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS Fast FLASH technology Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package

Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP + 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f where: MCHS = # macrocells in high-speed configuration PTHS = average number of high-speed product terms per macrocell MCLP = # macrocells in low power configuration PTLP = average number of low power product terms per macrocell f = maximum clock frequency MCTOG = average % of flip-flops toggling per clock (~12%) This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx

WARNING: Programming temperature range of TA = 0 C to +70 C

Description
The XC9572XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communi 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS057 (v2.0) April 3, 2007 Product Specification

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XC9572XL High Performance CPLD application note XAPP114, Understanding XC9500XL CPLD Power.
125 178 MHz 100 Typical ICC (mA)
h Hig Pe rfor m e anc

75

50

P Low

ow

er

104 MHz

25

0 50 100 150 200 Clock Frequency (MHz)

DS057_01_010102

Figure 1: Typical ICC vs. Frequency for XC9572XL

3 JTAG Port 1 JTAG Controller

In-System Programming Controller

54 I/O I/O I/O 18

Function Block 1 Macrocells 1 to 18

Fast CONNECT II Switch Matrix

I/O

54 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

54 18

Function Block 3 Macrocells 1 to 18

54 18

Function Block 4 Macrocells 1 to 18

DS057_02_082800

Figure 2: XC9572XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

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DS057 (v2.0) April 3, 2007 Product Specification

XC9572XL High Performance CPLD

Absolute Maximum Ratings(2)

Symbol VCC VIN VTS TSTG TJ Input voltage relative to Storage temperature Junction temperature Description Supply voltage relative to GND GND(1) output(1) Voltage applied to 3-state Value 0.5 to 4.0 0.5 to 5.5 0.5 to 5.5 65 to +150 +150 Units V V V
oC oC

(ambient)(3)

Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to 2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free packages, see XAPP427.

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0oC to 70oC Industrial TA = 40oC to +85oC Min 3.0 3.0 3.0 2.3 0 2.0 0 Max 3.6 3.6 3.6 2.7 0.80 5.5 VCCIO Units V V V V V V V

Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation Low-level input voltage High-level input voltage Output voltage

Quality and Reliability Characteristics

Symbol TDR NPE VESD Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) Parameter Min 20 10,000 2,000 Max Units Years Cycles Volts

DC Characteristic Over Recommended Operating Conditions

Symbol VOH VOL IIL IIH IIH Parameter Output high voltage for 3.3V outputs Output high voltage for 2.5V outputs Output low voltage for 3.3V outputs Output low voltage for 2.5V outputs Input leakage current I/O high-Z leakage current I/O high-Z leakage current Test Conditions IOH = 4.0 mA IOH = 500 A IOL = 8.0 mA IOL = 500 A VCC = Max; VIN = GND or VCC VCC = Max; VIN = GND or VCC VCC = Max; VCCIO = Max; VIN = GND or 3.6V VCC Min < VIN < 5.5V CIN ICC I/O capacitance Operating supply current (low power mode, active) VIN = GND; f = 1.0 MHz VIN = GND, No load; f = 1.0 MHz Min 2.4 90% VCCIO 20 (Typical) Max 0.4 0.4 10 10 10 50 10 Units V V V V A A A A pF mA

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XC9572XL High Performance CPLD

AC Characteristics
XC9572XL-5 Symbol TPD TSU TH TCO fSYSTEM TPSU TPH TPCO TOE TOD TPOE TPOD TAO TPAO TWLH TAPRPW TPLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GSR to output valid P-term S/R to output valid GCK pulse width (High or Low) Asynchronous preset/reset pulse width (High or Low) P-term clock pulse width (High or Low) Min 3.7 0 1.7 2.0 2.8 5.0 5.0 Max 5.0 3.5 178.6 5.5 4.0 4.0 7.0 7.0 10.0 10.5 XC9572XL-7 Min 4.8 0 1.6 3.2 4.0 6.5 6.5 Max 7.5 4.5 125.0 7.7 5.0 5.0 9.5 9.5 12.0 12.6 XC9572XL-10 Min 6.5 0 2.1 4.4 4.5 7.0 7.0 Max 10.0 5.8 100.0 10.2 7.0 7.0 11.0 11.0 14.5 15.3 Units ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns

VTEST

R1 Device Output R2 CL

Output Type

VCCIO 3.3V 2.5V

VTEST 3.3V 2.5V

R1 320 250

R2 360 660

CL 35 pF 35 pF

DS058_03_081500

Figure 3: AC Load Circuit

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DS057 (v2.0) April 3, 2007 Product Specification

XC9572XL High Performance CPLD

Internal Timing Parameters

XC9572XL-5 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN TPTCK TPTSR TPTTS TPDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI TLOGILP TF TPTA TSLEW Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable/disable delay Product term clock delay Product term set/reset delay Product term 3-state delay Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal logic delay Internal low power logic delay Fast CONNECT II feedback delay Incremental product term allocator delay Slew-rate limited delay 2.3 1.4 2.4 1.4 5.0 1.0 5.0 1.9 0.7 3.0 1.5 1.1 2.0 4.0 2.0 0 1.6 1.0 5.5 0.5 0.4 6.0 2.6 2.2 2.6 2.2 7.5 1.4 6.4 3.5 0.8 4.0 2.3 1.5 3.1 5.0 2.5 0 2.4 1.4 7.2 1.3 0.5 6.4 3.0 3.5 3.0 3.5 10.0 1.8 7.3 4.2 1.0 4.5 3.5 1.8 4.5 7.0 3.0 0 2.7 1.8 7.5 1.7 1.0 7.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max XC9572XL-7 Min Max XC9572XL-10 Min Max Units

Product Term Control Delays

Internal Register and Combinatorial Delays

Feedback Delays

Time Adders

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XC9572XL High Performance CPLD

XC9572XL I/O Pins(4)

Function Block Macrocell PC44 VQ44 CS48 VQ64 BScan TQ100 Order Func -tion Block Macrocell PC44 VQ44 CS48 VQ64 TQ100 BScan Order

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

1 2 3 4 5(1) 6(1) 7(1) 8 9 35 36 37 38 39(1) 40(1) 42(3) 43 44 -

39 40 41 42 43(1) 44(1) 1(1) 2 3 29 30 31 32 33(1) 34(1) 36(3) 37 38 -

D7 D4 D6 C7 C6 B7(1) B6(1) A7(1) A6 C5 F4 G5 F5 G6 G7(1) F6(1) E6(3) E7 E5 -

8 12 13 9 10 11 15(1) 18 16(1) 23 17(1) 19 20 60 58 59 61 62 63 64(1) 1 2(1) 4 5(3) 6 7 -

16 13 18 20 14 15 25 17 22(1) 28 23(1) 33 36 27(1) 29 39 30 40 87 94 91 93 95 96 3(2) 97 99(1) 1 4(1) 6 8 9(3) 11 10 12 92

213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

11 12 13 14 18 19 20 24 22 25 26 27 28 29 33 34 -

5 6 7 8 12 13 14 18 16 19 20 21 22 23 27 28 -

B5 C4 A4 B4 A3 D3 B2 B1 C2 D2 C3 E1 E2 E4 F1 G1 F2 E3 G4 -

22 31 32 24 34 25 27 39 33 40 35 36 42 38 43 46 47 44 49 45 51 48 52 50 56 57 -

41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 64 58 59 65 67 71 72 68 76 77 70 66 81 74 82 85 78 89 86 90 79

105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

Notes: 1. Global control pin. 2. GTS1 for TQ100. 3. GTS1 for PC44, VQ44, CS48, and VQ64. 4. The pin-outs are the same for Pb-free versions of packages.

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DS057 (v2.0) April 3, 2007 Product Specification

XC9572XL High Performance CPLD

XC9572XL Global, JTAG and Power Pins(1)

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 3.3V VCCIO 2.5V/3.3V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21, 41 32 10, 23, 31 VQ44 43 44 1 36 34 33 11 9 24 10 15, 35 26 4, 17, 25 CS48 B7 B6 A7 E6 F6 G7 A1 B3 G2 A2 C1, F7 G3 A5, D1, F3 VQ64 15 16 17 5 2 64 30 28 53 29 3, 37 26, 55 14, 21, 41, 54 TQ100 22 23 27 3 4 99 48 45 83 47 5, 57, 98 26, 38, 51, 88 21, 31, 44, 62, 69, 75, 84, 100 2, 7, 19, 24, 34, 43, 46, 73, 80
Notes: 1. The pin-outs are the same for Pb-free versions of packages.

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XC9572XL High Performance CPLD

Device Part Marking and Ordering Combination Information

R

Device Type Package Speed Operating Range

XC95xxxXL TQ144 7C
This line not related to device part number

Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line:

Sample package with part marking.

Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXL. Line 2 = Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C1 = CS48, C2 = CSG48.

Device Ordering and Part Marking Number XC9572XL-5PC44C XC9572XL-5VQ44C XC9572XL-5CS48C XC9572XL-5VQ64C XC9572XL-5TQ100C XC9572XL-7PC44C XC9572XL-7VQ44C XC9572XL-7CS48C XC9572XL-7VQ64C XC9572XL-7TQ100C XC9572XL-7PC44I XC9572XL-7VQ44I XC9572XL-7CS48I XC9572XL-7VQ64I XC9572XL-7TQ100I XC9572XL-10PC44C XC9572XL-10VQ44C XC9572XL-10CS48C XC9572XL-10VQ64C XC9572XL-10TQ100C XC9572XL-10PC44I XC9572XL-10VQ44I XC9572XL-10CS48I XC9572XL-10VQ64I XC9572XL-10TQ100I
Notes:

Speed (pin-to-pin delay) 5 ns 5 ns 5 ns 5 ns 5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns

Pkg. Symbol PC44 VQ44 CS48 VQ64 TQ100 PC44 VQ44 CS48 VQ64 TQ100 PC44 VQ44 CS48 VQ64 TQ100 PC44 VQ44 CS48 VQ64 TQ100 PC44 VQ44 CS48 VQ64 TQ100

No. of Pins 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin

Package Type Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP)

Operating Range(1) C C C C C C C C C C I I I I I C C C C C I I I I I

C = Commercial: TA = 0 to +70C; I = Industrial: TA = 40 to +85C

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XC9572XL High Performance CPLD Speed (pin-to-pin delay) 5 ns 5 ns 5 ns 5 ns 5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns

Device Ordering and Part Marking Number XC9572XL-5PCG44C XC9572XL-5VQG44C XC9572XL-5CSG48C XC9572XL-5VQG64C XC9572XL-5TQG100C XC9572XL-7PCG44C XC9572XL-7VQG44C XC9572XL-7CSG48C XC9572XL-7VQG64C XC9572XL-7TQG100C XC9572XL-7PCG44I XC9572XL-7VQG44I XC9572XL-7CSG48I XC9572XL-7VQG64I XC9572XL-7TQG100I XC9572XL-10PCG44C XC9572XL-10VQG44C XC9572XL-10CSG48C XC9572XL-10VQG64C XC9572XL-10TQG100C XC9572XL-10PCG44I XC9572XL-10VQG44I XC9572XL-10CSG48I XC9572XL-10VQG64I XC9572XL-10TQG100I

Pkg. Symbol PCG44 VQG44 CSG48 VQG64 TQG100 PCG44 VQG44 CSG48 VQG64 TQG100 PCG44 VQG44 CSG48 VQG64 TQG100 PCG44 VQG44 CSG48 VQG64 TQG100 PCG44 VQG44 CSG48 VQG64 TQG100

No. of Pins 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin

Package Type Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free

Operating Range(1) C C C C C C C C C C I I I I I C C C C C I I I I I

Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = 40 to +85C

Standard Example: XC9572XL -4 TQ Device Speed Grade Package Type Number of Pins Temperature Range

144

Pb-Free Example: XC9572XL -4 TQ Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range

144

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XC9572XL High Performance CPLD

Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS.

Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down. Data Sheets, Application Notes, and White Papers. Packaging

Revision History
The following table shows the revision history for this document. Date 09/28/98 08/28/01 06/20/02 05/27/03 08/21/03 07/15/04 09/15/04 04/29/05 07/15/05 03/22/06 04/03/07 Version 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Initial Xilinx release. Added VQ44 package. Updated ICC equation, page 1. Updated Component Availability table. Added additional IIH test conditions and measurements to DC Characteristics table. Updated TSOL from 260 to 220oC. Added Part Marking and updated Ordering Information. Updated Package Device Marking Pin 1 orientation. Added Pb-free documentation Added TAPRPW specification to AC Characteristics. No change to documentation. Move to Product Specification Add Warranty Disclaimer. Add programming temperature range warning on page 1. Revision

10

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DS057 (v2.0) April 3, 2007 Product Specification