CNG HC AVR

...to become the AVR Master

tm kim...

Trang ch Thng tin

Hc AVR

ng dng AVR

H tr phn mm

H tr phn cng

Tho lun

Thng tin

Bi 2 - Cu Trc AVR
( 119 Votes ) There are no translations available.

Ni dung
1. Gii thiu. 2. T chc AVR. 3. Stack. 4. Thanh ghi trng thi. 5. V d. Download v d

Cc bi cn tham kho trc

Lm quen AVR. Assembly cho AVR. AVR Studio. M phng vi Proteus.

I. Gii thiu. Bi ny tip tc bi u tin trong lot bi gii thiu v AVR, nu sau bi " Lm quen AVR " bn phn no bit cch lp trnh cho AVR bng AVRStudio th trong bi ny, chng ta s tm hiu k hn v cu trc ca AVR. Sau bi ny, bn s:
Hiu c cu trc AVR, cu trc b nh v cch thc hot ng ca chip. Hiu v Stack v cch hot ng. Bit c mt s instruction c bn truy xut b nh. Hc cc instruction r nhnh v vng lp. Chng trnh con (Subroutine) v Macro. Ci tin v d trong bi 1. Vit 1 v d minh ha cch s dng b nh v vng lp.

II. T chc ca AVR. AVR c cu trc Harvard, trong ng truyn cho b nh d liu (data memory bus) v ng truyn cho b nh chng trnh (program memory bus) c tch ring. Data memory bus ch c 8 bit v c kt ni vi hu ht cc thit b ngoi vi, vi register file. Trong khi program memory bus c rng 16 bits v ch phc v cho instruction registers. Hnh 1 m t cu trc b nh ca AVR. B nh chng trnh (Program memory): L b nh Flash lp trnh c, trong cc chip AVR c (nh AT90S1200 hay AT90S2313) b nh chng trnh ch gm

1 phn l Application Flash Section nhng trong cc chip AVR mi chng ta c thm phn Boot Flash setion. Boot section s c kho st trong cc phn sau, trong bi ny khi ni v b nh chng trnh, chng ta t hiu l Application section. Thc cht, application section bao gm 2 phn: phn cha cc instruction (m lnh cho hot ng ca chip) v phn cha cc vector ngt (interrupt vectors). Cc vector ngt nm phn u ca application section (t a ch 0x0000) v di n bao nhiu ty thuc vo loi chip. Phn cha instruction nm lin sau , chng trnh vit cho chip phi c load vo phn ny. Xem li phn u ca v d trong bi 1: .ORG 0x000 RJMP BATDAU .ORG 0x020 Trong v d ny, ngay sau khi set v tr 0x000 bng ch th (DIRECTIVE) .ORG 0x000 chng ta dng instruction RJMP nhy n v tr 0x020, nh th phn b nh chng trnh t 0x00 n 0x01F khng c s dng (v trong v d ny chng ta khng s dng cc vector ngt). Chng trnh chnh c bt u t a ch 0x020, con s 0x020 l do ngi lp trnh chn, tht ra cc vector ngt ca chip ATMEGA8 ch ko di n a ch 0x012, v vy chng trnh chnh c th c bt u t bt c v tr no sau . bit di cc vector ngt ca tng chip bn hy tham kho datasheet ca chip . V chc nng chnh ca b nh chng trnh l cha instruction, chng ta khng c nhiu c hi tc ng ln b nh ny khi lp trnh cho chip, v th i vi ngi lp trnh AVR, b nh ny khng qu quan trng. Tt c cc thanh ghi quan trng cn kho st nm trong b nh d liu ca chip.

Hnh 1. T chc b nh ca AVR. B nh d liu (data memory): y l phn cha cc thanh ghi quan trng nht ca chip, vic lp trnh cho chip phn ln l truy cp b nh ny. B nh d liu trn cc chip AVR c ln khc nhau ty theo mi chip, tuy nhin v c bn phn b nh ny c chia thnh 5 phn:

Phn 1: l phn u tin trong b nh d liu, nh m t trong hnh 1, phn ny bao gm 32 thanh ghi c tn gi l register file (RF), hay General Purpose Rgegister GPR, hoc n gin l cc Thanh ghi. Tt c cc thanh ghi ny u l cc thanh ghi 8 bits nh trong hnh 2.
Hnh 2. Thanh ghi 8 bits. Tt c cc chip trong h AVR u bao gm 32 thanh ghi Register File c a ch tuyt i t 0x0000 n 0x001F. Mi thanh ghi c th cha gi tr dng t 0 n 255 hoc cc gi tr c du t -128 n 127 hoc m ASCII ca mt k t no Cc thanh ghi ny c t tn theo th t l R0 n R31. Chng c chia thnh 2 phn, phn 1 bao gm cc thanh ghi t R0 n R15 v phn 2 l cc thanh ghi R16 n R31. Cc thanh ghi ny c cc c im sau: c truy cp trc tip trong cc instruction. Cc ton t, php ton thc hin trn cc thanh ghi ny ch cn 1 chu k xung clock. Register File c kt ni trc tip vi b x l trung tm CPU ca chip. Chng l ngun cha cc s hng trong cc php ton v cng l ch cha kt qu tr li ca php ton. minh ha, hy xt v d thc hin php cng 2 thanh ghi bng instruction ADD nh sau: ADD R1, R2 Bn thy trong dng lnh trn, 2 thanh ghi R1 v R2 c s dng trc tip vi tn ca chng, dng lnh trn khi c dch sang opcode download vo chip s c dng: 0000110000010010 trong 00001=1 tc thanh ghi R1 v 00010 = 2 ch thanh ghi R2. Sau php cng, kt qu s c lu vo thanh ghi R1. Tt c cc instruction s dng RF lm ton hng u c th truy nhp tt c cc RF mt cch trc tip trong 1 chu k xung clock, ngoi tr SBCI, SUBI, CPI, ANDI v LDI, cc instruction ny ch c th truy nhp cc thanh ghi t R16 n R31. Thanh ghi R0 l thanh ghi duy nht c s dng trong instruction LPM (Load Program Memory). Cc thanh ghi R26, R27, R28, R29, R30 v R31 ngoi chc nng thng thng cn c s dng nh cc con tr (Pointer register) trong mt s instruction truy xut gin tip. Chng ta s kho st vn con tr sau ny. Hnh 3 m t cc chc nng ph ca cc thanh ghi.

Hnh 3. Register file. Tm li 32 RF ca AVR c xem l 1 phn ca CPU, v th chng c CPU s dng trc tip v nhanh chng, gi cc thanh ghi ny, chng ta khng cn gi a ch m ch cn gi trc tip tn ca chng. RF thng c s dng nh cc ton hng (operand) ca cc php ton trong lc lp trnh. Phn 2: l phn nm ngay sau register file, phn ny bao gm 64 thanh ghi c gi l 64 thanh ghi nhp/xut (64 I/O register) hay cn gi l vng nh I/O (I/O Memory). Vng nh I/O l ca ng giao tip gia CPU v thit b ngoi vi. Tt c cc thanh ghi iu khin, trng thica thit b ngoi vi u nm y. Xem li v d trong bi 1, trong ti c cp v vic iu khin cc PORT ca AVR, mi PORT lin quan n 3 thanh ghi DDRx, PORTx v PINx, tt c 3 thanh ghi ny u nm trong vng nh I/O. Xa hn, nu mun truy xut cc thit b ngoi vi khc nh Timer, chuyn i Analog/Digital, giao tip USARTu thc hin thng qua vic iu khin cc thanh ghi trong vng nh ny. Vng nh I/O c th c truy cp nh SRAM hay nh cc thanh ghi I/O. Nu s dng instruction truy xut SRAM truy xut vng nh ny th a ch ca chng c tnh t 0x0020 n 0x005F. Nhng nu truy xut nh cc thanh ghi I/O th a ch ca chng c tnh t 0x0000 n 0x003F. Xt v d instruction OUT dng xut gi tr ra cc thanh ghi I/O, lnh ny s dng a ch kiu thanh ghi, cu trc ca lnh nh sau: OUT A, Rr, trong A l a ch ca thanh ghi trong vng nh I/O, Rr l thanh ghi RF, lnh OUT xut gi tr t thanh ghi Rr ra thanh ghi I/O c a ch l A. Gi s chng ta mun xut gi tr cha trong R6 ra thanh ghi iu khin hng ca PORTD, tc thanh ghi DDRD, a ch tnh theo vng I/O ca thanh ghi DDRD l 0x0011, nh th cu lnh ca chng ta s c dng: OUT

0x0011, R6. Tuy nhin trong 1 trng hp khc, nu mun truy xut DDRD theo dng SRAM, v d lnh STS hay LDS, th phi dng a ch tuyt i ca thanh ghi ny, tc gi tr 0x0031, khi lnh OUT trn c vit li l STS 0x0031, R6. thng nht cch s dng t ng, t by gi chng ta dng khi nim a ch I/O cho cc thanh ghi trong vng nh I/O ni n a ch khng tnh phn Register File, khi nim a ch b nh ca thanh ghi l ch a ch tuyt i ca chng trong SRAM. V d thanh ghi DDRD c a ch I/O l 0x0011 v a ch b nh ca n l 0x0031, a ch b nh = a ch I/O + 0x0020. V cc thanh ghi trong vng I/O khng c hiu theo tn gi nh cc Register file, khi lp trnh cho cc thanh ghi ny, ngi lp trnh cn nh a ch ca tng thanh ghi, y l vic tng i kh khn. Tuy nhin, trong hu ht cc phn mm lp trnh cho AVR, a ch ca tt c cc thanh ghi trong vng I/O u c nh ngha trc trong 1 file Definition, bn ch cn nh km file ny vo chng trnh ca bn l c th truy xut cc thanh ghi vi tn gi ca chng. Gi s trong v d bi 1, lp trnh cho chip Atmega8 bng AVRStudio, dng th 2 chng ta s dng INCLUDE "M8DEF.INC" load file nh ngha cho chip ATMega8, file M8DEF.INC. V vy, trong sau ny khi mun s dng thanh ghi DDRD bn ch cn gi tn ca chng, nh: OUT DDRD,R6. Phn 3: RAM tnh, ni (internal SRAM), l vng khng gian cho cha cc bin (tm thi hoc ton cc) trong lc thc thi chng trnh, vng ny tng t cc thanh RAM trong my tnh nhng c dung lng kh nh (khong vi KB, ty thuc vo loi chip). Phn 4: RAM ngoi (external SRAM), cc chip AVR cho php ngi s dng gn thm cc b nh ngoi cha bin, vng ny thc cht ch tn ti khi no ngi s dng gn thm b nh ngoi vo chip. Phn 5: EEPROM (Electrically Ereasable Programmable ROM) l mt phn quan trng ca cc chip AVR mi, v l ROM nn b nh ny khng b xa ngay c khi khng cung cp ngun nui cho chip, rt thch hp cho cc ng dng lu tr d liu. Nh trong hnh 1, phn b nh EEPROM c tch ring v c a ch tnh t 0x0000. Cu hi by gi l AVR hot ng nh th no? Hnh 4 biu din cu trong bn trong ca 1 AVR. Bn thy rng 32 thanh ghi trong Register File c kt ni trc tip vi Arithmetic Logic Unit -ALU (ALU cng c xem l CPU ca AVR) bng 2 line, v th ALU c th truy xut trc tip cng lc 2 thanh ghi RF ch trong 1 chu k xung clock (vng c khoanh trn mu trong hnh 4).

Hnh 4. Cu trc bn trong AVR. Cc instruction c cha trong b nh chng trnh Flash memory di dng cc thanh ghi 16 bit. B nh chng trnh c truy cp trong mi chu k xung clock v 1 instruction cha trong program memory s c load vo trong instruction register, instruction register tc ng v la chn register file cng nh RAM cho ALU thc thi. Trong lc thc thi chng trnh, a ch ca dng lnh ang thc thi c quyt nh bi mt b m chng trnh PC (Program counter). chnh l cch thc hot ng ca AVR. AVR c u im l hu ht cc instruction u c thc thi trong 1 chu k xung clock, v vy c th ngun clock ln nht cho AVR c th nh hn 1 s vi iu khin khc nh PIC nhng thi gian thc thi vn nhanh hn.

III. Stack. Stack c hiu nh l 1 thp d liu, d liu c cha vo stack nh thp v d liu cng c ly ra t nh. Kiu truy cp d liu ca stack gi l LIFO (Last In First Out vo sau ra trc). Hnh 5 th hin cch truy cp d liu ca stack.

Hnh 5. Stack. Khi nim v cch thc hot ng ca stack c th c p dng cho AVR, bng cch khai bo mt vng nh trong SRAM l stack ta c th s dng vng nh ny nh mt stack thc th. khai bo mt vng SRAM lm stack chng ta cn xc lp a ch u ca stack bng cch xc lp con tr stack-SP (Stack Pointer). SP l 1 con tr 16 bit bao gm 2 thanh ghi 8 bit SPL v SPH (ch L l LOW ch thanh ghi mang gi tr byte thp ca SP, v H = HIGH), SPL v SPH nm trong vng nh I/O. Gi tr gn cho thanh ghi SP s l a ch khi ng ca stack. Quay li v d bi 1, phn khi to cc iu kin u. ; KHOI TAO CC DIEU KIEN DAU LDI R16, HIGH(RAMEND) LDI R17, LOW(RAMEND) OUT SPH, R16 OUT SPL, R17 Bn dng khai bo trn mc ch l gn gi tr ca RAMEND cho con tr SP, RAMEND (tc End of Ram) l bin cha a ch ln nht ca RAM ni trong AVR, bin ny c nh ngha trong file M8DEF.INC. Nh th sau 4 dng trn, con tr SP cha gi tr cui cng ca SRAM hay ni cch khc vng stack bt u t v tr cui cng ca b nh SRAM. Nhng ti sao l v tr cui cng m khng l 1 gi tr khc. C th gii thch nh sau: stack trong AVR hot ng t trn xung, sau khi d liu c y vo stack, SP s gim gi tr v th khi ng SP v tr cui cng ca SRAM s trnh c vic mt d liu do ghi . Bn c th khi ng stack vi 1 a ch khc, tuy nhin v l do an ton, nn khi ng stack RAMEND. Hai instruction dng cho truy cp stack l PUSH v POP, trong PUSH dng y d liu vo stack v POP dng ly d liu ra khi stack. D liu c y vo v ly ra khi stack ti v tr m con tr SP tr n. V d cho chip ATMega8, RAMEND=0x045F, sau khi khi ng, con tr SP tr n v tr 0x045F trong SRAM, nu ta vit cc cu lnh sau: LDI R16, 1 PUSH R16 LDI R16, 5 PUSH R16 LDI R16, 8 PUSH R16 Khi ni dung ca stack s nh trong hnh 6.

Hnh 6. Ni dung stack trong v d. Sau mi ln PUSH d liu, SP s gim 1 n v v tr vo v tr tip theo. By gi nu ta dng POP ly d liu t stack, POP R2, th R2 s mang gi tr ca ngn nh 0x045D, tc R2=8. Trc khi instruction POP c thc hin, con tr SP c tng ln 1 n v, sau d liu s c ly ra t v tr m SP tr n trong stack. Stack trong AVR khng phi l v y, ngha l chng ta ch c th PUSH d liu vo stack 1 su nht nh no y (ph thuc vo chip). S dng stack khng ng cch i khi s lm chng trnh thc thi sai hoc tn thi gian thc thi v ch. V th khng nn s dng stack ch lu cc bin thng thng. ng dng ph bin nht ca stack l s dng trong cc chng trnh con (Subroutine), khi chng ta cn nhy t mt v tr trong chng trnh chnh n 1 chng trnh con, sau khi thc hin chng trnh con li mun quay v v tr ban u trong chng trnh chnh th Stack l phng cch ti u dng cha b m chng trnh trong trng hp ny. Xem li v d trong bi 1, trong chng trnh chnh chng ta dng lnh RCALL DELAY nhy n on chng trnh con DELAY, RCALL l lnh nhy n 1 v tr trong b nh chng trnh, trc khi nhy, PC c cng thm 1 v PUSH mt cch t ng vo stack. Cui chng trnh con DELAY, chng ta dng instruction RET, instruction ny POP d liu t stack ra PC mt cch t ng, bng cch ny chng ta c th quay li v tr trc . Chnh v cc lnh RCALL v RET s dng stack mt cch t ng nn ta phi khi ng stack ngay t u, nu khng chng trnh s thc thi sai chc nng. Tm li cn khi ng stack u chng trnh v khng nn s dng stack mt cch ty thch nu cha tht cn thit.

IV. Thanh ghi trng thi - SREG (STATUS REGISTRY). Nm trong vng nh I/O, thanh ghi SREG c a ch I/O l 0x003F v a ch b nh l 0x005F (thng y l v tr cui cng ca vng nh I/O) l mt trong s cc thanh ghi quan trng nht ca AVR, v th m ti dnh phn ny gii thiu v thanh ghi ny. Thanh ghi SREG cha 8 bit c (flag) ch trng thi ca b x l, tt c cc bit ny u b xa sau khi reset, cc bit ny cng c th c c v ghi bi chng trnh. Chc nng ca tng bit c m t nh sau:

Hnh 7. Thanh ghi trng thi.

Bit 0 C (Carry Flag: C nh): l bit nh trong cc php i s hoc logic, v d

thanh ghi R1 cha gi tr 200, R2 cha 70, chng ta thc hin php cng c nh: ADC R1, R2, sau php cng, kt qu s c lu li trong thanh ghi R1, trong khi kt qu thc l 270 m thanh ghi R1 li ch c kh nng cha ti a gi tr 255 (v c 8 bit) nn trong trng hp ny, gi tr lu li trong R1 thc cht ch l 14, ng thi c C c set ln 1 (v 270=100001110, trong 8 bit sau 00001110 =14 s c lu li trong R1).

Bit 1 Z (Zero Flag: C 0): c ny c set nu kt qu php ton i s hay

php Logic bng 0.

Bit 2 N (Negative Flag: C m): c ny c set nu kt qu php ton i s

hay php Logic l s m.

Bit 3 V (Twos complement Overflow Flag: C trn ca b 2) : hot ng ca

c ny c v s kh hiu cho bn v n lin quan n kin thc s nh phn (phn b), chng ta s cp n khi no thy cn thit.

Bit 4 S (Sign Bit: Bit du): Bit S l kt qu php XOR gia 1 c N v V, S=N
xor V.

Bit 5 H (Half Carry Flag: C nh na): c H l c nh trong 1 vi php ton

i s v php Logic, c ny hiu qu i vi cc php ton vi s BCD.

Bit 6 T (Bit Copy Storage): c s dng trong 2 Instruction BLD (Bit LoaD) v
BST (Bit STorage). Ti s gii thch chc nng Bit T trong phn gii thiu v BLD v BST.

Bit 7 I (Global Interrupt Enable) : Cho php ngt ton b): Bit ny phi c
set ln 1 nu trong chng trnh c s dng ngt. Sau khi set bit ny, bn mun kch hot loi ngt no cn set cc bit ngt ring ca ngt . Hai instruction dng

ring Set v Clear bit I l SEI v CLI. Ch : tt c cc bit trong thanh ghi SREG u c th c xa thng qua cc instruction khng ton hng CLx v set bi SEx, trong x l tn ca Bit.V d CLT l xa Bit T v SEI l set bit I. Ti ch gii thch ngn gn chc nng ca cc bit trong thanh ghi SREG, c th chc nng v cch s dng ca tng bit chng ta s tm hiu trong cc trng hp c th sau ny, ngi c c th t tm hiu thm trong cc ti liu v INSTRUCTION cho AVR. Ti cung cp thm 1 bng tm tt s nh hng ca cc php ton i s, logic ln cc Bit trong thanh ghi SREG.

Hnh 8. nh hng ca cc php ton ln SREG. IV. Macro v chng trnh con. Macro l khi nim ch mt on code nh thc hin mt cng vic no , nu c 1 on code no m bn rt hay s dng khi lp trnh th bn nn dng macro trnh vic phi vit i vit li on code . Lp trnh ASM cho AVR cho php bn s dng Macro, to 1 Macro bn s dng DIRECTIVE. .MACRO delay4 NOP NOP NOP

NOP .ENDMACRO on Macro trn c tn delay4 thc hin vic delay 4 chu k my bng 4 lnh NOP, nu trong chng trnh bn cn dng Macro ny th ch cn gi delay4 bt k dng no. [] ; code ca bn Delay4 [] ; code ca bn Mi ln tn ca Macro c gi, trnh bin dch s tm n Macro v copy ton b ni dung Macro vo v tr bn gi. Nh vy thc cht con tr chng trnh khng nhy n Macro, Macro khng lm gim dung lng chong trnh m ch lm cho vic lp trnh nh nhng hn. y chnh l khc bit ln nht ca Macro v Subroutine (chng trnh con). Chng trnh con cng l 1 on code thc hin 1 chc nng c bit no . Tuy nhin khc vi Macro, mi khi gi chng trnh con, con tr chng trnh nhy n chng trnh con thc thi chng trnh con v sau quay v chng trnh chnh. Nh th chng trnh con ch c bin dch 1 ln v c th s dng nhiu ln, n lm gim dung lng chong trnh. y l u im v cng l im khc bit ln nht gia chng trnh con v Macro. Tuy nhin cn ch l vic nhy n chng trnh con v nhy v chng trnh chnh cn vi chu k my, c th lm chm chng trnh, y l nhc im ca chng trnh con so vi macro. Chng trnh con cho AVR lun c bt u bng 1 Label, cng l tn v a ch ca chng trnh con. Chng trnh con thng c kt thc vi cu lnh RET (Return). Chng ta bit v chng trnh con qua v d ca bi 1, trong DELAY l 1 chng trnh con. gi chng trnh con t 1 v tr no trong chng trnh, chng ta c th dng lnh CALL hoc RCALL (Relative CALL) (xem li v d bi 1 v cch s dng RCALL). Mi khi cc lnh ny c gi, b m chng trnh c t ng c PUSH vo stack v khi chng trnh con kt thc bng lnh RET, b m chng trnh c POP tr ra v quay v chng trnh chnh. Lnh CALL c th gi 1 chng trnh con bt k v tr no trong khi RCALL ch gi trong khong b nh 4KB, nhng RCALL cn t chu k xung clock hn khi thc thi. Hai instruction khc c th c dng gi chng trnh con l JMP (Jump) v RJMP (Relative Jump). Khc vi cc lnh call, cc lnh jump khng cho php quay li v khng t ng PUSH b m chng trnh vo Stack, s dng cc lnh ny gi chng trnh con bn cn mt s lnh jump khc cui chng trnh con. Tm li bn nn vit 1 chng trnh con ng chun v dng CALL hoc RCALL gi chng cc chng trnh ny, ch nhng trng hp c bit hoc bn hiu rt r v chng th c th dng cc lnh jump.

V. V d minh ha.

Nu bn c v hiu n thi im ny th bn c th hiu ht hot ng ca chng trnh v d trong bi 1, tht s v d rt n gin v d hiu. Tuy nhin, bn c th ti u ha v d theo hng lm gim dung lng chng trnh v tt nhin, chng trnh s kh hiu hn cho ngi khc. Cc phn khi ng v tr b nh, stack v chng trnh con DELAY chng ta khng thay i, ch thay i phn chng trnh chnh, 1 trong nhng cch vit chng trnh chnh nh cch sau: ; CHUONG TRINH CHINH , BAI 1, VI DU 1, VERSION 2/////////////////////////////// LDI R16, $1 ;LOAD GIA TRI KHOI DONG CHO R16 MAIN: OUT PORTB, R16 ; XUAT GIA TRI TRONG R16 RA PORTB RCALL DELAY ; GOI CHUONG TRINH CON DELAY ROL R16 ; XOAY THANH GHI R16 SANG TRAI 1 VI TRI RJMP MAIN ; NEU R16 0, NHAY VE MAIN, TIEP TUC QUET ;///////////////////////////////////////////////////////////////////////////////////////// C th khng cn gii thch bn cng c th hiu on code trn, y ch l 1 trong nhng cch c th, bn hy vit li theo cch ca ring bn vi yu cu l chng trnh phi thc hin ng chc nng v ngn gn. By gi chng ta s thc hin mt v d minh ha cho nhng g chng ta hc trong bi 2 ny. Ni dung ca v d th hin trong mch in hnh 9. Hot ng ca mch in t nh sau: 1 chip ATMega8 c s dng nh mt counter, c th dng m ln v m xung, 2 button trong mch in tc ng nh 2 kicker, nhn button 1 m ln v button m xung, gi tr m nm trong khong t 0 n 9. Gi tr m c hin th trn 1 LED 7 on loi anod chung (dng chung), chip 7447 c dng gii m t gi tr BCD xut ra bi ATMega8 sang tn hiu cho LED 7 on anod chung, chng ta cn s dng 7447 v tn hiu xut ra t chip ATMega8 l dng nh phn hoc BCD , tn hiu ny khng th hin th trc tip trn cc LED 7 on, chip 7447 c nhim v chuyn 1 d liu dng digit BCD sang m ph hp cho LED 7 on. thc hin v d, trc ht bn hy v mch in nh trong hnh 9 bng phn mm Proteus (xem cch v mch in bng Proteus), mch in ch c 5 loi linh kin l chip ATMega8 (t kha mega8), 1 LED 7 on anod chung vi tn y trong Proteus l 7SEG-COM-AN-GRN (t kha 7SEG), 1 chip 7447 (t kha 7447), 1 in tr 10 v 2 button (t kha button).

Hnh 9. V d cho bi 2. S dng AVRStudio to 1 project mi vi tn gi avr2 (xem li cch to Project mi trong AVRStudio). Vit li phn code bn di vo vo file avr2.asm List 1. V d cu trc AVR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 .INCLUDE "M8DEF.INC" .CSEG. .ORG 0x0000 RJMP BATDAU .ORG 0x0020 BATDAU: ;KHOI DONG STACK POINTER LDI R17, HIGH(RAMEND) LDI R16, LOW(RAMEND) OUT SPL, R16 OUT SPH,R17 ; KHOI DONG CAC PORT CLR R16 ; XOA R16, R16=0 OUT DDRB, R16 ; DDRB=0, PORTB LA NGO NHAP LDI R16, 0xFF ; SET TAT CA CAC BIT CUA R16 LEN 1 OUT PORTB,R16 ;DDRB=0, PORTB =0xFF, KEO LEN CAC CHAN PORTB OUT DDRD, R16 ;DDRD=0xFF, PORTD LA NGO XUAT CLR R25 ;XOA R25, R25 LA THANH GHI DUNG CHUA SO DEM SER R20 ; R20 LA THANH GHI TAM CHUA GIA TRI TRUOC DO CUA PINB MAIN: IN R21,PINB ;DOC GIA TRI TU PINB, TUC TU CAC BUTTON RCALL SOSANH ;GOI CHUONG TRINH CON SOSANH OUT PORTD, R25 ;XUAT GIA TRI DEM RA PORTD SBRS R21,0 ;NEU BIT 0 CUA R21 (TUC CHAN PB0) =1 THI BO QUA DONG ;TIEP THEO RCALL TANG ;NHAY DEN CHUONG TRINH CON TANG GIA TRI DEM SBRS R21,1 ;NEU BIT 1 CUA R21 (TUC CHAN PB1) =1 THI BO QUA DONG ;TIEP THEO RCALL GIAM ;NHAY DEN CHUONG TRINH CON GIAM GIA TRI DEM MOV R20,R21 ;LUU LAI TRANG THAI PINB RJMP MAIN ;**********************CHUONG TRINH CON************************ ; **************subroutine kiem tra gioi hang (tu 0 den 9) cua so dem SOSANH: CPI R25, 10 BREQ RESET0 ;NEU GIA TRI DEM=10 THI TRA VE 0 CPI R25, 255 BREQ RESET9 ;NEU GIA TRI DEM =255 THI TRA VE 9 RJMP QUAYVE ;NHAY DEN NHAN QUAYVE RESET0: LDI R25,$0 ;TRA GIA TRI DEM VE 0 RJMP QUAYVE RESET9: LDI R25,$9 ;GAN 9 CHO GIA TRI DEM QUAYVE: RET

45 46 47 48 49 50 51 52 53 54 55 56 57

; ************************************************************ ; **************subroutine tang so dem 1 don vi neu dieu kien thoa TANG: SBRS R20,0 RET INC R25 RET ; **************subroutine giam so dem 1 don vi neu dieu kien thoa GIAM: SBRS R20,1 RET DEC R25 RET

Trong v ny ny, chng ta s dng 2 PORT ca chip ATMega8, PORTD dng xut d liu (s m) ra chip 7447 v sau hin th trn LED 7 on. PORTB dng nh ng nhp, tn hiu t cc button s c chip ATMega8 nhn thng qua 2 chn PB0 v PB1 ca PORTB. Hot ng ca cac PORT v vic xc lp 1 PORT nh cc ng xut chng ta kho st trong bi 1. y chng ta kho st thm v xc lp PORT nh 1 ng nhp, trc ht bn hy quan st mch in tng ng ca 1 chn trong cc PORT xut nhp ca AVR trong hnh 10.

Hnh 10. Cu trc chn trong PORT ca AVR. Trong mch in hnh 10, cc diode v t in ch c chc nng bo v chn PORT, nhng in tr Rpu (R Pull up) ng vai tr quan trng nh l in tr ko ln khi chn ca PORT lm nhim v nhn tn hiu (ng nhp). Tuy nhin trong AVR, in tr ko ln ny khng phi lun kch hot, chng ta bit rng mi PORT ca AVR c 3 thanh ghi: DDRx, PORTx v PINx, nu DDRx=0 th PORT x l ng nhp, lc ny thanh ghi PINx l thanh ghi cha d liu nhn v, c bit thanh ghi PORTx vn c s dng trong mode ny, l thanh ghi xc lp in tr ko ln, nh th nu DDRx=0 v PORTx=0xFF th cc chn PORTx l ng nhp v c ko ln bi 1 in tr trong chip, ngha l cc chn ca PORTx lun mc cao, mun kch thay i trng thi chn ny chng ta cn ni chn trc tip vi GND, y l l do ti sao cc button trong mch in ca chng ta c 1 u ni vi chn ca chip cn u kia c ni vi GND. y cng l ngha ca khi nim in tr ko ln (Pull up resistor) trong k thut in t. on code trong phn KHOI DONG CAC PORT ca v d ny xc lp PORTD l ng xut (DDRD=0xFF) , PORTB l ng nhp c s

dng in tr ko ln (DDRB=0, PORTB=0xFF). Chng ta s gii thch hot ng ca on chng trnh chnh v cc on chng trnh con. Trc ht, trong chng trnh ny, chng ta s dng 3 thanh ghi chnh l R20, R21 v R25, trong R25 l thanh ghi cha s m, gi tr ca thanh ghi R25 s c xut ra PORTD ca chip, thanh ghi R21 cha trng thi ca thanh ghi PINB v cng l trng thi ca cc button, thanh ghi R20 kt hp vi thanh ghi R21 to thnh 1 b m cnh xung ca cc button. hiu thu o hot ng m (cng l hot ng chnh ca v d ny) chng ta xt trng thi chn PB0 nh trong hnh 11.

Hnh 11. Thay i trng thi cc chn I/O. Trong trng thi bnh thng (button khng c nhn), chn PB0 mc cao (do in tr ko ln), b m khng hot ng, gi tr m khng thay i, by gi nu nhn button, chn PB0 c ni trc tip vi GND, chn ny s b ko xung mc thp, bng cch kim tra trng thi chn PB0, nu PB0=0 ta tng gi tr m 1 n v. tng nh th c v hp l, tuy nhin nu p dng th chng trnh s hot ng khng ng chc nng, khi bn nhn 1 ln gi, tr m c th tng n c trm hoc khng kim sot c, hiu ng ny tng t khi bn nhn v gi 1 phm trn bn phm my tnh, l do l v chng ta s dng phng php kim tra mc m, thi gian qut ca chng trnh rt ngn so vi thi gian chng ta gi button. khc phc, chng ta dng phng php kim tra cnh xung, ch khi no pht hin chn PB0 thay i t 1 xung 0 th mi tng gi tr m 1 n v, kt qu l mi ln nhn button th gi tr m ch tng 1 (ngay c khi ta nhn v gi button), thanh ghi R20 c s dng lu trng thi trc ca PINB (cng l trng thi ca cc button). Trong chng trnh, ti s dng 2 istruction mi l SBRC v SBRS kim tra trng thi cc chn ca PORTB (button). SBRC Skip if Bit in Register is Clear, lnh ny s b qua 1 dng lnh ngay sau (ch b qua 1 dng duy nht) nu 1 bit trong thanh ghi mc 0, SBRC Skip if Bit in Register is Set- hot ng tng t SBRC nhng skip s xy ra nu bit trong thanh ghi mc 1. Da vo y chng ta gii thch 4 dng sau: SBRS R21,0 ;NEU BIT 0 CUA R21 (TUC CHAN PB0) =1 THI BO QUA DONG ;TIEP THEO RCALL TANG ;NHAY DEN CHUONG TRINH CON TANG GIA TRI DEM SBRS R21,1 ;NEU BIT 1 CUA R21 (TUC CHAN PB1) =1 THI BO QUA DONG ;TIEP THEO RCALL GIAM ;NHAY DEN CHUONG TRINH CON GIAM GIA TRI DEM Dng 1 dng kim tra trng thi bit 0 trong R21 (ch R21 cha gi tr ca PINB), nu bit ny bng 1 (set), tc chn PB0=1 hay button khng c nhn, th nhy b qua dng lnh tip theo n dng 3. dng 3 chng trnh kim tra trng

thi chn PB1 (button th 2). Quay li dng 1, nu chng trnh kim tra pht hin chn PB0=0 (button th nht c nhn) th dng lnh th 2 c thc thi, kt qu l chng trnh nhy n chng trnh con TANG. TANG: SBRS R20,0 RET INC R25 RET Dng u tin ca chng trnh con TANG l kim tra trng thi trc ca chn PB0 (c lu bit 0 trong thanh ghi R20), nu trng thi ny bng 0, ngha l khng c s chuyn t 1 xung 0 chn PB0, dng 2 (lnh RET) s c thc thi quay v chng trnh chnh. Nhng nu PB0 trc bng 1, ngha l c s thay i t 1->0 chn ny, gi tr m s c tng thm 1 nh INC R25, sau quay v chng trnh chnh. Tm li mun tng gi tr m thm 1 n v cn tha mn 2 iu kin: chn PB0 hin ti =0 (button ang c nhn) v trng thi trc ca PB0 phi l 1 (trnh trng hp tng lin tc). Phng php ny c th p dng cho rt nhiu trng hp m dng m xung. Qu trnh gim gi tr m c hiu tng t, phn cn li ca v d ny bn c hy t gii thch theo nhng gi trn.

[Top]

Copyright 2011 Bn quyn thuc v Cng hc AVR (AVR tutorial) - Ti liu hc lp trnh AVR bng ting Vit. AVR is a registered trademark of Atmel Corporation This site is founded by Thanhtam Ho