V d 1: PROCESS(x) SUBTYPE smallreal IS REAL RANGE -1.0E6 TO 1.0E6; VARIABLE q : real; BEGIN q := smallrealLEFT; -- use of left returns -- -1.

0E6 END test; V d 2: PROCESS(a) TYPE bit_range IS ARRAY(31 DOWNTO 0) OF BIT; VARIABLE left_range, right_range, uprange, lowrange : integer; BEGIN left_range := bit_rangeLEFT; -- returns 31 right_range := bit_rangeRIGHT; -- returns 0 uprange := bit_rangeHIGH; -- returns 31 lowrange := bit_rangeLOW; -- returns 0 END PROCESS; V d 3: ARCHITECTURE b OF a IS TYPE color IS (blue, cyan, green, yellow, red, magenta); SUBTYPE reverse_color IS color RANGE red DOWNTO green; SIGNAL color1, color2, color3, color4, color5, color6, color7, color8 : color; BEGIN color1 <= colorLEFT; -- returns blue color2 <= colorRIGHT; -- returns magenta color3 <= colorHIGH; -- returns magenta color4 <= colorLOW; -- returns blue color5 <= reverse_colorLEFT;

-- returns red color6 <= reverse_colorRIGHT; -- returns green color7 <= reverse_colorHIGH; -- returns red color8 <= reverse_colorLOW; -- returns green END b; V d 4: PROCESS(a) TYPE bit4 IS ARRAY(0 TO 3) of BIT; TYPE bit_strange IS ARRAY(10 TO 20) OF BIT; VARIABLE len1, len2 : INTEGER; BEGIN len1 := bit4LENGTH; -- returns 4 len2 := bit_strangeLENGTH; -- returns 11 END PROCESS; V d 5: PACKAGE p_4val IS TYPE t_4val IS (x, 0, 1, z); TYPE t_4valX1 IS ARRAY(t_4valLOW TO t_4valHIGH) OF t_4val; TYPE t_4valX2 IS ARRAY(t_4valLOW TO t_4valHIGH) OF t_4valX1; TYPE t_4valmd IS ARRAY(t_4valLOW TO t_4valHIGH, t_4valLOW TO t_4valHIGH) OF t_4val; CONSTANT andsd : t_4valX2 := ((x, -- xx 0, -- x0 x, -- x1 (Notice this is an x), -- xz array of arrays.) (0, -- 0x 0, -- 00 0, -- 01 0), -- 0z (x, -- 1x 0, -- 10 1, -- 11 x), -- 1z (x, -- zx

0, -- z0 x, -- z1 x)); -- zz CONSTANT andmd : t_4valmd := ((x, -- xx 0, -- x0 x, -- x1 x), -- xz (Notice this example (0, -- 0x is a multidimensional 0, -- 00 array.) 0, -- 01 0), -- 0z (x, -- 1x 0, -- 10 1, -- 11 x), -- 1z (x, -- zx 0, -- z0 x, -- z1 x)); -- zz END p_4val; V d 6: PROCESS(a) VARIABLE len1, len2, len3, len4 : INTEGER; BEGIN len1 := t_4valX1LENGTH; -- returns 4 len2 := t_4valX2LENGTH; -- returns 4 len3 := t_4valmdLENGTH(1); -- returns 4 len4 := t_4valmdLENGTH(2); -- returns 4 END PROCESS; V d 7: LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY shifter IS PORT( clk, left : IN std_logic; right : OUT std_logic); END shifter; ARCHITECTURE structural OF shifter IS COMPONENT dff PORT( d, clk : IN std_logic; q : OUT std_logic);

END COMPONENT; SIGNAL i1, i2, i3: std_logic; BEGIN u1: dff PORT MAP(d => left, clk => clk, q => i1); u2: dff PORT MAP(d => i1, clk => clk, q => i2); u3: dff PORT MAP(d => i2, clk => clk, q => i3); u4: dff PORT MAP(d => i3, clk => clk, q => right); checktime: PROCESS(clk) VARIABLE last_time : time := timeleft; BEGIN ASSERT (NOW - last_time = 20 ns) REPORT spike on clock SEVERITY WARNING; last_time := now; END PROCESS checktime; END structural;