Low Power Design

in CMOS

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Why worry about power?
-- Heat Dissipation
microprocessor power dissipation

source : arpa-esto
DEC 21164

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Evolution in Power Dissipation

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Why worry about power —
Portability
50

Nominal Capacity (Watt-hours / lb)

Rechargable Lithium
40
Ni-Metal Hydride
30

20 Nickel-Cadium

BATTERY 10
(40+ lbs)

0
65 70 75 80 85 90 95
Year
Multimedia Terminals Expected Battery Lifetime increase
Laptop Computers over next 5 years: 30-40%
Digital Cellular Telephony

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

Where Does Power Go in CMOS?

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Dynamic Power Consumption
Vdd

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd 2 * f

Not a function of transistor sizes!

Need to reduce CL , Vdd, and f to reduce power.
Digital Integrated Circuits Low Power Design © Prentice Hall 1995
 Dynamic Power Consumption - Revisited

Power = Energy/transition * transition rate

= CL * Vdd2 * f0→1

= CL * Vdd2 * P0→1* f
= CEFF * Vdd2 * f

Power Dissipation is Data Dependent

Function of Switching Activity

CEFF = Effective Capacitance = CL * P0→1

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Power Consumption is Data Dependent

Example: Static 2 Input NOR Gate

Assume:
P(A=1) = 1/2
P(B=1) = 1/2
Then:
P(Out=1) = 1/4
P(0 →1)
= P(Out=0).P(Out=1)
= 3/4 × 1/4 = 3/16

CEFF = 3/16 * CL

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Transition Probabilities for Basic Gates

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Transition Probability of 2-input NOR Gate

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Problem: Reconvergent Fanout

A X

B
Z

Reconvergence

P(Z=1) = P(B=1) . P(X=1 | B=1)

Becomes complex and intractable real fast

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 How about Dynamic Circuits?

VDD

φ Mp
Out

In1
In2 PDN
In3

φ Me

Power is Only Dissipated when Out=0!

CEFF = P(Out=0).CL

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 4-input NAND Gate
Example: Dynamic 2 Input NOR Gate

Assume:
P(A=1) = 1/2
P(B=1) = 1/2
Then:
P(Out=0) = 3/4

CEFF = 3/4 * CL

Switching Activity Is Always Higher in Dynamic Circuits

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Transition Probabilities for Dynamic Gates

Switching Activity for Precharged Dynamic Gates

P0→1 = P0

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Glitching in Static CMOS
also called: dynamic hazards
A X

B Z
C

ABC 101 000

Unit Delay

Observe: No glitching in dynamic circuits

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Example 1: Chain of NOR Gates
out1 out2 out3 out4 out5
1
...

6.0

out8
4.0 out6
out4
out2
V (Volt)

2.0
out1
out3
out5
out7
0.0
0 1 2 3
t (nsec)

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Example 2: Adder Circuit

Cin Add0 Add1 Add2 Add14 Add15

S0 S1 S2 S14 S15
Sum Output Voltage, Volts

4.0
4
S15

6
2.0 3
S10
Cin
5
S1
2
0.0
0 5 10
Time, ns

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 How to Cope with Glitching?

0
F1 0
1 F1 1
F2 0
0 2
F3
0 F3
0
0
F2 1
0

Equalize Lengths of Timing Paths Through Design

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Short Circuit Currents

Vdd

Vin Vout

CL

0.15

0.10
IVDD (mA)

0.05

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Impact of rise/fall times on short-circuit
currents

VDD VDD

ISC ≈ 0 ISC ≈ IMAX

Vout Vout
Vin Vin
CL CL

Large capacitive load Small capacitive load

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

Short-circuit energy as a function of slope
ratio
∆E / E W/L|P = 7.2 µm/1.2 µm
W/L|N = 2.4µ m/1.2µm
8 VDD = 5 V
7
6
5
4
3
2 VDD = 3.3 V
1
0 r
0 1 2 3 4 5

The power dissipation due to short circuit currents is

minimized by matching the
rise/fall times of the input and output signals.

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Static Power Consumption

Vdd

Istat
V out

CL
V in=5V

Pstat = P(In=1).Vdd . Istat

• Dominates over dynamic consumption

• Not a function of switching frequency

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Leakage
Vdd

Vout

Drain Junction
Leakage

Sub-Threshold
Current

Sub-Threshold Current Dominant Factor

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Sub-Threshold in MOS

√ID

VT =0.2 VT =0.6 VGS

Lower Bound on Threshold to Prevent Leakage

Digital Integrated Circuits Low Power Design © Prentice Hall 1995
 Power Analysis in SPICE
VDD Pav
C
i DD
+ Circuit k iDD R
- Under Test

Equivalent Circuit for Measuring Power in SPICE

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Design for Worst Case
V DD
VDD

1 1 B 4
A A 2
B
F C 4
2 CL
B D 2
F
2 A 2
D 1
A
B 2C 2

Here it is assumed that Rp = Rn

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Reducing Vdd
1.5
NORMALIZED POWER-DELAY PRODUCT

1.00 P x td = E t = C L * Vdd 2
0.70
0.50

0.30

0.20
0.15 quadratic dependence
E(Vdd=2) (CL) * (2)2
=
0.1
E(Vdd=5) (CL) * (5)2
51 stage ring oscillator
0.07
0.05
E(Vdd=2) ≈ 0.16 E(Vdd =5)
8-bit adder
0.03
1 2 5
Vdd (volts)

Strong function of voltage (V2 dependence).

Relatively independent of logic function and style.
Power Delay Product Improves with lowering VDD.

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Lower Vdd Increases Delay

7.50 multiplier
7.00
clock generator
2.0µ m technology CL * Vdd
6.50 Td =
6.00
I
5.50
NORMALIZED DELAY

5.00
4.50 I ~ (Vdd - Vt)2
4.00
3.50
ring oscillator
3.00
2.50
Td(Vdd=2) (2) * (5 - 0.7)2
microcoded DSP chip =
2.00 Td(Vdd=5) (5) * (2 - 0.7)2
1.50 adder
1.00 adder (SPICE) ≈ 4
2.00 4.00 6.00
V dd (volts)

Relatively independent of logic function and style.

Digital Integrated Circuits Low Power Design © Prentice Hall 1995
 Lowering the Threshold

Delay I
D

2V t Vdd Vt = 0 Vt = 0.2 VGS

Reduces the Speed Loss, But Increases Leakage

Interesting Design Approach:

DESIGN FOR PLeakage == PDynamic

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

Transistor Sizing for Power Minimization

Lower Capacitance Higher Voltage

Small W/L’s

Large W/L’s
Higher Capacitance Lower Voltage

Larger sized devices are useful only when interconnect dominated.

Minimum sized devices are usually optimal for low-power.

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Transistor Sizing for Fixed Throughput

Cg = W/L CMIN
I ∝ W/L CMIN
C MIN = Minimum sized gate (W/L=1)
W /L after sizing
CP = Cwiring + CDF
α = CP / (K C MIN)

10
7
HIGH PERFORMANCE α =0

NORMALIZED ENERGY
5
W/L >> C P / (K C MIN) 4
3 α = 0.5

LOW POWER 2
1.5 α=1
W/L = 2 CP / (K C MIN)
(if C P ≥ K CMIN) adder
1.0 α = 1.5

ELSE W/L = 1 0.7 α=2

0.5
1 3 10
W/L
Digital Integrated Circuits Low Power Design © Prentice Hall 1995
 Reducing Effective Capacitance

Global bus architecture Local bus architecture

Shared Resources incur Switching Overhead

Digital Integrated Circuits Low Power Design © Prentice Hall 1995

 Summary
• Power Dissipation is becoming Prime Design
Constraint
• Low Power Design requires Optimization at all Levels

• Sources of Power Dissipation are well characterized

• Low Power Design requires operation at lowest

possible voltage and clock speed

Digital Integrated Circuits Low Power Design © Prentice Hall 1995