EE247 Lecture 21

ADC Converters
Comparator design
Single-stage open-loop amplifier Cascade of open-loop amplifiers Problem associated with DC offset
Cascaded output series cancellation Input series cancellation Offset cancellation through additional input pair plus offset storage capacitors

Latched comparators Comparator examples

EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 1

Summary Last Lecture

ADC Converters
Sampling (continued)
Effect of clock jitter on sampling

ADC architectures and design

Serial- slope type Successive approximation Flash Flash ADC sources of error
Comparator offset Sparkle code Meta-stability
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 2

Voltage Comparators
VDD

Vi+ Vi-

+ Vout (Digital Output)

Play an important role in majority of ADCs Function: Compare the instantaneous value of two analog signals & generate a digital output voltage based on the sign of the difference: If Vi+ -Vi- > 0 If Vi+ -Vi- < 0 Vout=1 Vout=0

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Nyquist Rate ADC: Comparator Design

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Voltage Comparator Architectures

Comparator architectures: High gain amplifier with differential analog input & single-ended large swing output
Output swing has to be compatible with driving digital logic circuits Open-loop amplification no frequency compensation required Precise gain not required

Latched comparators; in response to a strobe (clock edge), input stage disabled & digital output stored in a latch till next strobe
Two options for implementation : Latch-only comparator Low-gain amplifier + high-sensitivity latch

Sample-data comparators
T/H input Offset cancellation

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Nyquist Rate ADC: Comparator Design

2007 H.K. Page 4

Comparators Built with High-Gain Amplifier

Amplify Vin(min) to VDD Vin(min) determined by ADC resolution Example: 12-bit ADC with: - VFS= 1.5V 1LSB=0.36mV - VDD=1.8V For 1.8V output & 0.5LSB precision: Av Mi n = 1.8V 0.18mV 10,000

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 5

Comparators 1-Single-Stage Amplification

fu = unity- gain fre que nc y, fo=- 3dB frequency AV Ex am ple: fu= 10GHz & AV = 10,000 1M Hz 10,000 1 se t tl in g = = 0.16 sec 2 fo A llow a fe w f or out put to se ttle 1 Max fCloc k. 1. 26M Hz 5 se t tl in g fo = 10GHz fo= fu
Gain Av fu=0.1-10GHz f0 fu frequency

Assumption: Single pole amplifier

Too slow for majority of applications! Try cascade of lower gain stages to broaden frequency of operation
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 6

Comparators 2- Cascade of Open Loop Amplifiers

The stages identical

small-signal model for the cascades:

One stage:

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 7

Open Loop Cascade of Amplifiers

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 8

Open Loop Cascade of Amplifiers

For |AT(DC)|=10,000

Example: N=3, fu=10GHz & AT ( 0 ) = 10000 foN = 10GHz

(10,000 )1/ 3

21/ 31 237MHz

settling =

1 = 0.7n sec 2 fo

Allow a few for output to settle

Max. fClock

1 290MHz 5 settling
X236

fmax improved from 1.26MHz to 290MHz

EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design

2007 H.K. Page 9

Open Loop Cascade of Amplifiers Offset Voltage

From offset point of view: high gain/stage is preferred Choice of # of stage bandwidth vs offset tradeoff

Input-referred offset
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 10

Open Loop Cascade of Amplifiers Step Response

Assuming linear behavior (not slew limited)

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 11

Open Loop Cascade of Amplifiers Step Response

Assuming linear behavior

EECS 247 Lecture 21

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Open Loop Cascade of Amplifiers Delay/(C/gm)

Minimum total delay broad function of N Relationship between # of stages resulting in minimize delay (Nop) and gain (Vout/Vin) approximately:
Delay/(C/gm)

Nopt 1 + l og2 AT f or A < 1000 Nopt 1.2l n AT for A 1000

Ref: J.T. Wu, et al., A 100-MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 13

Offset Cancellation
In sampled-data cascade of amplifiers Vos can be cancelled Store on ac-coupling caps in series with amp stages Offset associated with a specific amp can be cancelled by storing it in series with either the input or the output of that stage Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier and storing the offset on capacitors connected to the aux. inputs during offset cancellation phase
Ref: J.T. Wu, et al., A 100-MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 14

Offset Cancellation Output Series Cancellation

Amp modeled as ideal + Vos (input referred)

Store offset: S1, S4 S2, S3 open closed VC=AxVOS

Ref: J.T. Wu, et al., A 100-MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 15

Offset Cancellation Output Series Cancellation

Amplify: S1, S4 S2, S3 closed open VC=AxVOS Circuit requirements: Amp not saturate during offset storage High-impedance (C) load discharged Cc >> CL to avoid attenuation Cc >> Cswitch avoid excessive offset due to charge injection
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 16

Cc not

Offset Cancellation Cascaded Output Series Cancellation

Note: Offset storage capacitors in series with the amplifier outputs

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Nyquist Rate ADC: Comparator Design

2007 H.K. Page 17

Offset Cancellation Cascaded Output Series Cancellation

1- S1

open, S2,3,4,5 closed

VC1=A1xVos1 VC2=A2xVos2 VC3=A1xVos3

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Nyquist Rate ADC: Comparator Design

2007 H.K. Page 18

Offset Cancellation Cascaded Output Series Cancellation

2- S3 open first Feedthrough from S3 offset on X Switch offset , 3 induced on node X Since S4 remains closed, offset associated with 3

stored on C2

VX= 3 VC1=A1xVos1- 3 VC2=A2x(Vos2+ 3)

EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 19

Offset Cancellation Cascaded Output Series Cancellation

3- S4 open Feedthrough from S4 offset on Y Switch offset , 4 induces error on node Y

Since S5 remains closed, offset associated with 4

stored on C3

VY= 4 VC2=A2x(Vos2+ 3) 4 VC3=A3x(Vos3+ 4)

EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 20

Offset Cancellation Cascaded Output Series Cancellation

4- S2 open, S1 closed, S5 open S1 closed & S2 open since input connected to low impedance source charge injection not of major concern Switch offset , 5 introduced due to S5 opening

VX = A1x(Vin+Vos1) VC1 = A1x(Vin+Vos1) (A1.Vos1- 3) =A1.Vin+ 3)

EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 21

Offset Cancellation Cascaded Output Series Cancellation

Vy = A2x(Vx+Vos2) VC2 = A2x(A1Vin + 3 + Vos2) [A2.(Vos2+3) - 4] =A1.A2.Vin + 4

Vout = A3x(Vy+Vos3) VC3 = A3.(A2xA1Vin + 4 + Vos3) [A3.(Vos3+4) - 5] = A1.A2.A3.Vin + 5

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Offset Cancellation Cascaded Output Series Cancellation

Vout = A1.A2.A3.(Vin + 5 /A1.A2.A3) Input-Referred Offset = 5 /A1.A2.A3

Example: 3-stage open-loop differential amplifier with offset cancellation + output amplifier (see Ref.) ATotal(DC) = 2x106 = 126dB Input-referred offset < 5V
Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 23

Offset Cancellation Output Series Cancellation

Advantages:
Almost compete cancellation Closed-loop stability not required

Disadvantages:
Gain per stage must be small Offset storage C in the signal path- could slow down overall performance

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Nyquist Rate ADC: Comparator Design

2007 H.K. Page 24

Offset Cancellation Input Series Cancellation

Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 25

Offset Cancellation Input Series Cancellation

Store offset

Note: Mandates closed-loop stability

Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 26

Offset Cancellation Input Series Cancellation

Amplify S2, S3 open S1 closed

Example: A=4 Input-referred offset =Vos/5

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 27

Offset Cancellation Cascaded Input Series Cancellation

2 charge injection associated with opening of S4

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

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Offset Cancellation Input Series Cancellation

Advantages:
In applications such as C-array successive approximation ADCs can use C-array to store offset

Disadvantages:
Cancellation not complete Requires closed loop stability Offset storage C in the signal path- could slow down overall performance
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 29

CMOS Comparators Cascade of Gain Stages

Fully differential gain stages feedthrough offset 1st order cancellation of switch

1- Output series offset cancellation

2- Input series offset cancellation

EECS 247 Lecture 21

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CMOS Comparators Cascade of Gain Stages

3-Combined input & output series offset cancellation

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

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Offset Cancellation
Cancel offset by additional pair of inputs (Lecture 19 slide 35 -37)

EECS 247 Lecture 21

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2007 H.K. Page 32

Latched Comparators
Vi+ Vi+
-

(Digital Output)

Vout

Vi+ - Vi-

t
Latch

Compares two input voltages at time tx & generates a digital output: If Vi+ - Vi- > 0 If Vi+ - Vi- < 0

Latch t

Vout=1 Vout=0

Vout

tx

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 33

CMOS Latched Comparators

Comparator amplification need not be linear can use a latch regeneration

Latch
EECS 247 Lecture 21

Amplification + positive feedback

Nyquist Rate ADC: Comparator Design 2007 H.K. Page 34

Simplest Form of CMOS Latch

VDD VDD

M3

M4

M1

M2

M1

M2

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

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CMOS Latched Comparators Small Signal Model

Latch can be modeled as a: Single-pole amp + positive feedback
Small signal ac half circuit

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2007 H.K. Page 36

CMOS Latched Comparator Latch Delay

g mV = V dV +C RL dt gm dV 1 dt = 1 C g m RL V
V2 1 gm 1 t2 1 g R t1 dt = V 1 V dV C m L

gm dV 1 V= 1 C g m RL dt Integrating both sides: Latch Delay: tD = t2 t1 = C 1 gm 1 1 g m RL For g m RL >> 1 C V2 ln g m V1

a a a1 b dx = ln x b = ln a ln b = ln b x

V2 ln V 1

tD

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 37

CMOS Latched Comparators

Normalized Latch Delay

tD

C V2 ln g m V1

tD C gm

V2 Latch Gain = AL V1 tD C ln AL gm

D(3-state amp)=

18.2(C/gm)

Compared to a 3-stage open-loop cascade of amps for equal overall gain of 1000 Latch faster by about x3

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 38

Latch-Only Comparator
Faster compared to cascade of open-loop amplifiers Main problem associated with latch-only comparator topology: High input-referred offset voltage (as high as 100mV!) Solution:
Use preamplifier to amplify the signal and reduce overall input-referred offset
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 39

Pre-Amplifier + Latch Overall Input-Referred Offset

Vi+ ViVosPreamp VosLatch

fs

Av
Preamp

Latch

Do+ Do-

Latch offset attenuated by preamp gain when referred to preamp input. Assuming the two offset sources are uncorrelated:
2 Input Re ferred _ Offset = Vos _ Pr eamp +

1 2 Vos _ Latch 2 APr eamp & APr eamp = 10

Example : Vos _ Pr eamp = 4mV & Vos _ Latch = 50mV

Input Re ferred _ Offset = 42 +

EECS 247 Lecture 21

1 102

502 = 6.4mV

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 40

Pre-Amplifier Tradeoffs
fs
Vi+ Vi-

Av
Preamp

Latch

Do+ Do-

Example:

Latch offset Preamp DC gain Preamp input-referred latch offset Input-referred preamplifier offset Overall input-referred offset

50 to 100mV 10X 5 to 10mV 2 to 10mV 5.5 to 14mV

Addition of preamp reduces the latch input-referred offset reduced by ~7 to 9X ~extra 3-bit resolution!
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 41

Comparator Preamplifier Gain-Speed Tradeoffs

Amplifier maximum Gain-Bandwidth product (fu)for a given technology, typically a function of maximum device ft
fu =unity gain frequency, f 0 = 3dB frequency & 0 = settling time f0 = fu = Apreamp

Magnitude Av fu=0.1-10GHz f0 fu Frequency

For example assuming preamp has a gain of 10: fu 1GHz = = 100 MHz f0 = Apreamp 10

1 = = 1.6n sec 2 f 0

Tradeoff: To reduce the effect of latch offset high preamp gain desirable Fast comparator low preamp gain
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 42

Latched Comparator
fs
Vi+ Vi-

Av
Preamp

Latch

Do+ Do-

Important features:
Maximum clock rate fs settling time, slew rate, small signal bandwidth Resolution gain, offset Overdrive recovery Input capacitance (and linearity of input capacitance!) Power dissipation Input common-mode range and CMR Kickback noise
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 43

Comparators Overdrive Recovery

Linear model for a single-pole amplifier:

amplification after time ta Example: Worst case input/output waveforms Previous input max. possible e.g. VFS Current input min. input-referred signal (0.5LSB)
2007 H.K. Page 44

During reset amplifier settles exponentially to its zero input condition with 0=RC Assume Vm maximum input normalized to 1/2lsb (=1)
EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

Comparators Overdrive Recovery

Example: Worst case input/output waveforms

If recovery time is not long enough to allow output to discharge (recover) from previous state- then it may not be able to resolve the small current input error To minimize this effect: 1. Passive clamp 2. Active restore 3. Low gain/stage
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 45

Comparators Overdrive Recovery Limiting or Resetting Output

Clamp Adds parasitic capacitance

Active Restore After outputs are latched by following stage Activate R & equalize output nodes
2007 H.K. Page 46

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

CMOS Latched Comparator Delay Including Preamplifier

Latch delay found previously:

C V2 ln g m V1 Assuming gain of Av for the preamplifier: C V0 ln Av g m Vin

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 47

Latched Comparator Including Preamplifier Example

VDD
M5 M3 M4 M6

Preamplifier gain:
M3 M3 g M 1 (VGS Vth ) Av = m 3 = M M gm (VGS 1 VthM 1 )

CLK

Vo +

+ Vin -

M1

M2 M9

bias

M7

M8

Comparator delay:

C V0 ln Av g m Vin

Preamp
Nyquist Rate ADC: Comparator Design

Latch
2007 H.K. Page 48

EECS 247 Lecture 21

Comparator Dynamic Behavior

Comparator Reset Comparator Decision

CLK
TCLK

Delay
VOUT

Delay

C V0 ln Av g m Vin

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 49

Comparator Resolution
CLK

VIN =10mV 1mV

vOUT

0.1mV 10V

t = (gm/C).ln(Vin1 /Vin2)
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 50

Comparator Voltage Transfer Function Non-Idealities

Vout

VOffset

-0.5LSB

0.5LSB

Vin VOffset
Comparator offset voltage Meta-Stable region (output ambiguous)

EECS 247 Lecture 21

Nyquist Rate ADC: Comparator Design

2007 H.K. Page 51

CMOS Comparator Example

Flash ADC: 8bits, +-1/2LSB INL @ fs=15MHz (VDD=5V, Vref=3.8V, LSB~15mV) No offset cancellation
Ref: A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, JSSC June 1985, pp. 775-9
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 52

Comparator with Auto-Zero

Ref: I. Mehr and L. Singer, A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 1999, pp. 912-20.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 53

Flash ADC Comparator with Auto-Zero

Voffset

VC + VC = (VR e f + VR e f ) VO ffs et
Ref: I. Mehr and D. Dalton, A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 1999, pp. 912-20.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 54

Flash ADC Comparator with Auto-Zero

Voffset

Vo

Vo = AP1 AP2 [(VIn+ VI n ) (VC + VC ) VOff s et ] S u b st i t u t i n g f o r (VC + VC ) f r o m p r evio u s c yc le : Vo = AP1 AP2 (VIn+ VIn ) (VRe f + VRe f ) N o t e: O f fs et i s ca n cel l ed & d i f f er ence b et w een i np u t & r ef er en ce es t a b l i s hed
Ref: I. Mehr and D. Dalton, A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 1999, pp. 912-20.
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 55

Auto-Zero Implementation

Ref:I. Mehr and L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC, JSSC March 2000, pp. 318-25
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 56

Comparator Example
Variation on Yukawa latch used w/o preamp Good for low resolution ADCs (in this case 1.5bit/stage pipeline ADC + digital correction) Note: M1, M2, M11, M12 operate in triode mode M11 & M12 added to vary comparator threshold Conductance at node X is sum of GM1 & GM11
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 57

Comparator Example (continued)

M1, M2, M11, M12 operate in triode mode with all having equal L Conductance of input devices:
G1 = G2 =

Cox
L

W1 (VI1 Vt h ) + W11 (VR Vth ) W1 (VI 2 Vth ) + W11 (VR + Vt h ) W1 (VI1 VI 2 ) W11 (VR + VR )

Vo1 Vo1

Vo2

Cox
L

G =

Cox
L

To 1st order, for W1= W2 & W11=W12 where VR = VR+ - VRVthlatch = W11/W1 x VR

G1

G2

VR fixed W11, 12 varied need for resistive divider

Eliminates

Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 58

Comparator Example
Used in a pipelined ADC with digital correction no offset cancellation required Note: Differential reference M7, M8 operate in triode region Preamp gain ~10 Input buffers suppress kick-back

1 high Cs charged to VR & 2B is also high current diverted to latch comparator output in hold mode 2 high Cs connected to S/Hout & comparator input (VR-S/Hout), current sent to preamp comparator in amplify mode

Ref: S. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC ,NO. 6, Dec. 1987
EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 59

Bipolar Comparator Example

Used in 8bit 400Ms/s & 6bit 2Gb/s flash ADC Signal amplification during 1 high, latch operates when 1 low Input buffers suppress kick-back & input current Separate ground and supply buses for frontend preamp kick-back noise reduction

Preamp

Latched Comparator

Ref: Y. Akazawa, et al., "A 400MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXX, pp. 98 - 99, February 1987 Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXXI, pp. 232 - 233, February 1988 EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design 2007 H.K. Page 60