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2
9
.
1
u
F
1 2
C
2
8
.
1
u
F
C
2
8
.
1
u
F
1 2
C
2
7
.
1
u
F
C
2
7
.
1
u
F
1 2
C
2
0
.
1
u
F
C
2
0
.
1
u
F
1
2
C
2
6
.
1
u
F
C
2
6
.
1
u
F
1 2
C
2
5
.
1
u
F
C
2
5
.
1
u
F
1 2
J
P
4
J
P
4
1 2 3
R
2
7
1
2
1
1
/
1
0
W
D
o

N
o
t

I
n
s
t
a
ll
1
%
R
2
7
1
2
1
1
/
1
0
W
D
o

N
o
t

I
n
s
t
a
ll
1
%
C
2
4
.
1
u
F
C
2
4
.
1
u
F
1 2
R
5
9
8
2
.
5
R
5
9
8
2
.
5
U
2
C
D
C
M
1
8
0
3
U
2
C
D
C
M
1
8
0
3
I
N
4
V S S
7
V
D
D
P
E
C
L
5
Y
1
1
5
Y
1
1
6
V
D
D
1
1
7
V
D
D
1
1
4
E
N
1
V
D
D
P
E
C
L
2
I
N
3
V
S
S
1
3
V
B
B
6
V D D 2
8
Y 2
9
Y 2
1 0
V D D 2
1 1
N C
1 2
S
0
1
8
S 1
1 9
V D D 0
2 0
Y 0
2 1
Y 0
2 2
V D D 0
2 3
S 2
2 4
G N D
2 5
C
2
3
.
1
u
F
C
2
3
.
1
u
F
1 2
T
3
T
C
1
-
1
T
T
3
T
C
1
-
1
T
3 2 1
6 5 4
C
1
8
.
1
u
F
1
6
V
C
1
8
.
1
u
F
1
6
V
1
2
C
3
3
.
1
u
F
1
6
V
C
3
3
.
1
u
F
1
6
V
1
2
C
2
2
.
1
u
F
C
2
2
.
1
u
F
1 2
C
2
1
.
1
u
F
C
2
1
.
1
u
F
1 2
J
P
3
J
P
3
1 2 3
R
3
0
6
0
.
4
K
R
3
0
6
0
.
4
K
J
P
2
J
P
2
1 2 3
R
6
1
8
2
.
5
R
6
1
8
2
.
5
C
1
7
.
1
u
F
1
6
V
C
1
7
.
1
u
F
1
6
V
J
P
1
D
o

N
o
t

I
n
s
t
a
ll
J
P
1
D
o

N
o
t

I
n
s
t
a
ll
1
2




D12_D13_P SH2
D12_D13_M SH2
D10_D11_P SH2
D10_D11_M SH2
D8_D9_P SH2
D8_D9_M SH2
CLKOUTP SH2
CLKOUTM SH2
D6_D7_P SH2
D6_D7_M SH2
D4_D5_P SH2
D4_D5_M SH2
D2_D3_P SH2
D2_D3_M SH2
D0_D1_P SH2
D0_D1_M SH2
CDC_CLKP SH3
CDC_CLKM SH3
FPGA_SCLK SH2
FPGA_SEN SH2
FPGA_SDATA SH2
J10
CONN_QTH_30X2-D-A
J10
CONN_QTH_30X2-D-A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
G1 G2
G3 G4
G5 G6
G7 G8
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120




+
3
.
3
V
D
_
I
N
5
V
_
I
N
+
3
.
3
V
A
_
I
N
+
3
.
3
V
A
+
3
.
3
V
D
5
V
+
5
V
_
A
M
P
C
3
1
u
F
C
3
1
u
F
1 2
C
4
.
1
u
F
C
4
.
1
u
F
1 2
J
1
3
R
E
D
+
3
.
3
V
A
_
I
N
J
1
3
R
E
D
+
3
.
3
V
A
_
I
N
C
3
0
1
0
u
F
6
.
3
V
C
3
0
1
0
u
F
6
.
3
V
1 2
L
1
6
8
L
1
6
8
1
2
+
C
8
3
3
u
F
+
C
8
3
3
u
F
1 2
+
C
5
2
3
3
U
F
1
0
V
+
C
5
2
3
3
U
F
1
0
V
1 2
+
C
1
3
3
u
F
+
C
1
3
3
u
F
1 2
L
2
6
8
L
2
6
8
1
2
C
5
3
.
1
u
F
1
6
V
C
5
3
.
1
u
F
1
6
V
+
C
5
3
3
u
F
+
C
5
3
3
u
F
1 2
J
2
0
R
E
D
+
5
V
_
I
N
J
2
0
R
E
D
+
5
V
_
I
N
C
3
1
1
u
F
1
0
V
C
3
1
1
u
F
1
0
V
1 2
C
6
1
u
F
C
6
1
u
F
1 2
J
1
1
R
E
D
+
3
.
3
V
D
_
I
N
J
1
1
R
E
D
+
3
.
3
V
D
_
I
N
R
6
5
0

O
H
M
R
6
5
0

O
H
M
J
1
4
B
L
K
G
N
D
J
1
4
B
L
K
G
N
D
C
7
.
1
u
F
C
7
.
1
u
F
1 2
C
9
1
0
u
F
6
.
3
V
C
9
1
0
u
F
6
.
3
V
1 2
L
8
6
8
L
8
6
8
1
2
C
5
7
1
0
u
F
6
.
3
V
C
5
7
1
0
u
F
6
.
3
V
1 2
L
3
6
8
L
3
6
8
1
2
J
1
2
B
L
K
G
N
D
J
1
2
B
L
K
G
N
D
C
2
1
0
u
F
6
.
3
V
C
2
1
0
u
F
6
.
3
V
1 2
-
5
V
_
I
N
+
3
.
3
V
_
A
U
X
5
V
-
V
S
S
_
A
M
P
C
6
7
.
1
u
F
1
6
V
C
6
7
.
1
u
F
1
6
V
C
5
5
.
1
u
F
1
6
V
C
5
5
.
1
u
F
1
6
V
C
6
6
.
1
u
F
1
6
V
C
6
6
.
1
u
F
1
6
V
J
1
6
R
E
D
-
V
S
S
_
A
M
P
J
1
6
R
E
D
-
V
S
S
_
A
M
P
L
9
6
8
L
9
6
8
1
2
U
1
0
T
P
S
7
3
2
3
3
U
1
0
T
P
S
7
3
2
3
3
E
N
3
I
N
1
G
N
D
2
O
U
T
5
N
C
/
F
B
4
C
5
6
1
0
u
F
6
.
3
V
C
5
6
1
0
u
F
6
.
3
V
1 2
+
C
5
4
3
3
U
F
1
0
V
+
C
5
4
3
3
U
F
1
0
V
1 2




GND
D6
D9
D1
D3
D7
D5
CLK
D13
D0
D2
D8
D10
D12
D11
D4
D7
D6
D5
D4
D3
D2
D1
D0
D13
D12
D11
D10
D9
D8
CLK
J1
CONN_QSH_30X2-D-A
J1
CONN_QSH_30X2-D-A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
G1 G2
G3 G4
G5 G6
G7 G8
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
J2
40PINIDC
DATA_OUT
J2
40PINIDC
DATA_OUT
1 2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33 34
35 36
37 38
39 40