Experiment No 1

Objective: Design the layout Ior CMOS inverter using Tanner tool


Inverter (NOT)

Figure 1. the inverter (not gate)

Figure 2. the inverter layout


NOT gate
input output
0 1
1 0

Table 1. NOT gate (inverter) output










Experiment No 2

Objective: Design the layout Ior 2-input NAND Gate using Tanner tool



Figure 4. the NAND gate













A B output
0 0 1
0 1 1
1 0 1
1 1 0

Table 2. NAND gate output





















Experiment No 3

Objective: Design the layout Ior 2-input using Tanner tool


Figure 7. the NOR gate


output Ior the NOR gate.
.





A B output
0 0 1
0 1 0
1 0 0
1 1 0

Table 3. NOR gate output



Figure 10. all gates together














Experiment No 4

Objective: Design the layout Ior 4 input NAND Gate using Tanner tool

We can create a 4-input NAND gate in two ways. The Iirst way is to layout the circuit in CMOS. Figure
11 shows the layout and Figure 12 shows the layout using L-edit.



Figure 11. the 4-input NAND gate (CMOS)

Figure 12. the 4-input NAND gate layout
Another way to create a 4-input NAND gate is to use the NAND, NOR and NOT gates we've already
created. Figure 13 shows how 2 NAND gates, a NOR gate and a NOT gate can be put together to
implement the 4-input NAND gate.

Figure 13. implementation oI a 4-input NAND gate using 2 NAND one NOR and a NOT gate.
As an extension, we laid out the gates in L-edit (see Figure 14). A comparison oI Figure 14 and Figure 12
shows how much more compact the gate would be iI it were built Irom scratch (and not using other gates).








Figure 14. the 4-input NAND gate layout using 2 NAND one NOR and a NOT gate.